From fb0491146518c24b8ded5f9afa59b1df3749dea9 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:26:49 +0900 Subject: [PATCH 01/10] ARM: S5P6440: Register apll/mpll/epll mout clocks. This patch modifies the following. 1. Registers the mout_apll clksrc_clk clock. 2. The mout_mpll and mout_epll were registered as 'struct clk' types and then their parents were setup using the s3c_set_clksrc function. This patch reduces the two steps into one by registering the mout_mpll and mout_epll clocks using the s3c_register_clksrc function. 3. As per point 2 above, the init_parents array is no longer required. So the mout clocks are now put together in a new array named 'sysclks'. The sysclks array will list the system level clocks and more clocks will be added to it in the subsequent patches. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index b2672e16e7aa..3ad63f41309e 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -574,7 +574,7 @@ static struct clksrc_clk clksrcs[] = { }; /* Clock initialisation code */ -static struct clksrc_clk *init_parents[] = { +static struct clksrc_clk *sysclks[] = { &clk_mout_apll, &clk_mout_epll, &clk_mout_mpll, @@ -652,17 +652,12 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) clk_h_low.rate = hclk_low; clk_p_low.rate = pclk_low; - for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c_set_clksrc(init_parents[ptr], true); - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); } static struct clk *clks[] __initdata = { &clk_ext, - &clk_mout_epll.clk, - &clk_mout_mpll.clk, &clk_dout_mpll, &clk_iis_cd_v40, &clk_pcm_cd, @@ -680,6 +675,9 @@ void __init s5p6440_register_clocks(void) if (ret > 0) printk(KERN_ERR "Failed to register %u clocks\n", ret); + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); From 30d58349608c3a31dbea0cc9238f6d8edc21e299 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:26:58 +0900 Subject: [PATCH 02/10] ARM: S5P6440: Change dout_mpll clock type to clksrc_clk clock type. This patch modifies the following. 1. Modifies the dout_mpll clock type as clksrc_clk clock type. This modification allows the use of common clock code in managing the dout_mpll clock (which otherwise would need custom defined functions such as s5p6440_clk_doutmpll_get_rate). 2. s5p6440_clk_doutmpll_get_rate function is removed as it is no longer needed. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 28 +++++++++------------------- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index 3ad63f41309e..8bd6f15a2ac1 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -247,23 +247,13 @@ static struct clk_ops s5p6440_clkarm_ops = { .round_rate = s5p6440_armclk_round_rate, }; -static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - - if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) - rate /= 2; - - return rate; -} - -static struct clk clk_dout_mpll = { - .name = "dout_mpll", - .id = -1, - .parent = &clk_mout_mpll.clk, - .ops = &(struct clk_ops) { - .get_rate = s5p6440_clk_doutmpll_get_rate, +static struct clksrc_clk clk_dout_mpll = { + .clk = { + .name = "dout_mpll", + .id = -1, + .parent = &clk_mout_mpll.clk, }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 }, }; int s5p6440_clk48m_ctrl(struct clk *clk, int enable) @@ -490,7 +480,7 @@ static struct clk clk_pcm_cd = { static struct clk *clkset_spi_mmc_list[] = { &clk_mout_epll.clk, - &clk_dout_mpll, + &clk_dout_mpll.clk, &clk_fin_epll, }; @@ -501,7 +491,7 @@ static struct clksrc_sources clkset_spi_mmc = { static struct clk *clkset_uart_list[] = { &clk_mout_epll.clk, - &clk_dout_mpll + &clk_dout_mpll.clk, }; static struct clksrc_sources clkset_uart = { @@ -578,6 +568,7 @@ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, &clk_mout_epll, &clk_mout_mpll, + &clk_dout_mpll, }; void __init_or_cpufreq s5p6440_setup_clocks(void) @@ -658,7 +649,6 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) static struct clk *clks[] __initdata = { &clk_ext, - &clk_dout_mpll, &clk_iis_cd_v40, &clk_pcm_cd, &clk_p_low, From 9c72d016e2b556e7d8f739b21404f32333fbc5e4 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:27:04 +0900 Subject: [PATCH 03/10] ARM: S5P6440: Remove usage of clk_arm and add clk_armclk clock The clk_arm clock is of type 'struct clk' whereas on S5P6440, the arm clock is more suitable to be of type 'struct clksrc_clk' (since arm clock is divided version of apll clock). This patch modifies the following. 1. Removes the usage of clk_arm clock (defined in plat-s5p) and defines the new clock 'clk_armclk' of type 'struct clksrc_clk'. 2. Rearranges the assignment of clock rate for the fout_a/m/epll clocks. This will help in calculating the clock rate of fclk from clk_armclk clock and setup the clock rate for fout_m/epll for subsequent patches which depend on it. 3. Modifies the clock rate calculation of fclk to be based on the newly added clk_armclk clock. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index 8bd6f15a2ac1..2c6dd544ff62 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -247,6 +247,16 @@ static struct clk_ops s5p6440_clkarm_ops = { .round_rate = s5p6440_armclk_round_rate, }; +static struct clksrc_clk clk_armclk = { + .clk = { + .name = "armclk", + .id = 1, + .parent = &clk_mout_apll.clk, + .ops = &s5p6440_clkarm_ops, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk clk_dout_mpll = { .clk = { .name = "dout_mpll", @@ -569,6 +579,7 @@ static struct clksrc_clk *sysclks[] = { &clk_mout_epll, &clk_mout_mpll, &clk_dout_mpll, + &clk_armclk, }; void __init_or_cpufreq s5p6440_setup_clocks(void) @@ -592,8 +603,6 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) clk_fout_epll.ops = &s5p6440_epll_ops; /* Set S5P6440 functions for arm clock */ - clk_arm.parent = &clk_mout_apll.clk; - clk_arm.ops = &s5p6440_clkarm_ops; clk_48m.enable = s5p6440_clk48m_ctrl; clkdiv0 = __raw_readl(S5P_CLK_DIV0); @@ -610,11 +619,15 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_apll.rate = apll; + printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ " E=%ld.%ldMHz\n", print_mhz(apll), print_mhz(mpll), print_mhz(epll)); - fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); + fclk = clk_get_rate(&clk_armclk.clk); hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); @@ -633,10 +646,6 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) print_mhz(hclk), print_mhz(hclk_low), print_mhz(pclk), print_mhz(pclk_low)); - clk_fout_mpll.rate = mpll; - clk_fout_epll.rate = epll; - clk_fout_apll.rate = apll; - clk_f.rate = fclk; clk_h.rate = hclk; clk_p.rate = pclk; From e4f44f82691e927a2f5eb582793454e052b920c7 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:27:09 +0900 Subject: [PATCH 04/10] ARM: S5P6440: Remove usage of clk_h and add clk_hclk clock The clk_h clock is of type 'struct clk' whereas on S5P6440, the hclk is more suitable to be of type 'struct clksrc_clk' (since hclk clock is divided version of armclk) This patch modifies the following. 1. Adds the 'clk_hclk' clock which is of type 'struct clksrc_clk'. 2. Removes all references to the clk_h clock. 3. Addes clk_hclk into the list of sysclks. 4. The clock rate 'hclk' is modified to be derived from clk_hclk. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index 2c6dd544ff62..bc0458e6d420 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -266,6 +266,15 @@ static struct clksrc_clk clk_dout_mpll = { .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 }, }; +static struct clksrc_clk clk_hclk = { + .clk = { + .name = "clk_hclk", + .id = -1, + .parent = &clk_armclk.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 }, +}; + int s5p6440_clk48m_ctrl(struct clk *clk, int enable) { unsigned long flags; @@ -321,7 +330,7 @@ static struct clk init_clocks_disable[] = { { .name = "nand", .id = -1, - .parent = &clk_h, + .parent = &clk_hclk.clk, .enable = s5p6440_mem_ctrl, .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, }, { @@ -580,6 +589,7 @@ static struct clksrc_clk *sysclks[] = { &clk_mout_mpll, &clk_dout_mpll, &clk_armclk, + &clk_hclk, }; void __init_or_cpufreq s5p6440_setup_clocks(void) @@ -628,7 +638,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) print_mhz(apll), print_mhz(mpll), print_mhz(epll)); fclk = clk_get_rate(&clk_armclk.clk); - hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); + hclk = clk_get_rate(&clk_hclk.clk); pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { From 47051461ab1cc8049e676902bf1972268bed4b9a Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:27:13 +0900 Subject: [PATCH 05/10] ARM: S5P6440: Remove usage of clk_p and add clk_pclk clock The clk_p clock is of type 'struct clk' whereas on S5P6440, the pclk is more suitable to be of type 'struct clksrc_clk' (since pclk clock is divided version of hclk). This patch modifies the following. 1. Adds the 'clk_pclk' clock which is of type 'struct clksrc_clk'. 2. Adds clk_pclk into the list of sysclks. 3. The clock rate 'pclk' is modified to be derived from clk_pclk. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index bc0458e6d420..61bc85b098ff 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -275,6 +275,15 @@ static struct clksrc_clk clk_hclk = { .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 }, }; +static struct clksrc_clk clk_pclk = { + .clk = { + .name = "clk_pclk", + .id = -1, + .parent = &clk_hclk.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 }, +}; + int s5p6440_clk48m_ctrl(struct clk *clk, int enable) { unsigned long flags; @@ -590,6 +599,7 @@ static struct clksrc_clk *sysclks[] = { &clk_dout_mpll, &clk_armclk, &clk_hclk, + &clk_pclk, }; void __init_or_cpufreq s5p6440_setup_clocks(void) @@ -639,7 +649,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) fclk = clk_get_rate(&clk_armclk.clk); hclk = clk_get_rate(&clk_hclk.clk); - pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); + pclk = clk_get_rate(&clk_pclk.clk); if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { /* Asynchronous mode */ From 93ad94db5509ccac65a57f6fc599d61a61767efc Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:27:17 +0900 Subject: [PATCH 06/10] ARM: S5P6440: Remove usage of clk_h_low and add clk_hclk_low clock The clk_h_low clock is of type 'struct clk' whereas on S5P6440, the hclk_low clock is more suitable to be of type 'struct clksrc_clk' (since hclk_low clock is derived from a choice of clock sources and then divided by a divisor). This patch modifies the following. 1. Removes the definition and usage of clk_h_clk clock. 2. Adds the clk_hclk_low clock of type 'struct clksrc_clk' clock. 3. Adds clk_hclk_low to the list of system clocks. 4. The clock rate of hclk_low is derived from the clk_hclk_low clock. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 54 ++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index 61bc85b098ff..c70b3a4075e9 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -134,15 +134,6 @@ static struct clksrc_clk clk_mout_mpll = { .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, }; -static struct clk clk_h_low = { - .name = "hclk_low", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .ops = &clk_ops_def_setrate, -}; - static struct clk clk_p_low = { .name = "pclk_low", .id = -1, @@ -284,6 +275,26 @@ static struct clksrc_clk clk_pclk = { .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 }, }; +static struct clk *clkset_hclklow_list[] = { + &clk_mout_apll.clk, + &clk_mout_mpll.clk, +}; + +static struct clksrc_sources clkset_hclklow = { + .sources = clkset_hclklow_list, + .nr_sources = ARRAY_SIZE(clkset_hclklow_list), +}; + +static struct clksrc_clk clk_hclk_low = { + .clk = { + .name = "hclk_low", + .id = -1, + }, + .sources = &clkset_hclklow, + .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, +}; + int s5p6440_clk48m_ctrl(struct clk *clk, int enable) { unsigned long flags; @@ -405,37 +416,37 @@ static struct clk init_clocks_disable[] = { }, { .name = "otg", .id = -1, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_USB }, { .name = "post", .id = -1, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_POST0 }, { .name = "lcd", .id = -1, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk1_ctrl, .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, }, { .name = "hsmmc", .id = 0, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, }, { .name = "hsmmc", .id = 1, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, }, { .name = "hsmmc", .id = 2, - .parent = &clk_h_low, + .parent = &clk_hclk_low.clk, .enable = s5p6440_hclk0_ctrl, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, }, { @@ -600,6 +611,7 @@ static struct clksrc_clk *sysclks[] = { &clk_armclk, &clk_hclk, &clk_pclk, + &clk_hclk_low, }; void __init_or_cpufreq s5p6440_setup_clocks(void) @@ -650,15 +662,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) fclk = clk_get_rate(&clk_armclk.clk); hclk = clk_get_rate(&clk_hclk.clk); pclk = clk_get_rate(&clk_pclk.clk); - - if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { - /* Asynchronous mode */ - hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); - } else { - /* Synchronous mode */ - hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); - } - + hclk_low = clk_get_rate(&clk_hclk_low.clk); pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW); printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ @@ -669,7 +673,6 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) clk_f.rate = fclk; clk_h.rate = hclk; clk_p.rate = pclk; - clk_h_low.rate = hclk_low; clk_p_low.rate = pclk_low; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) @@ -681,7 +684,6 @@ static struct clk *clks[] __initdata = { &clk_iis_cd_v40, &clk_pcm_cd, &clk_p_low, - &clk_h_low, }; void __init s5p6440_register_clocks(void) From 697f8a9fe7835ba24f2da855c5de4ddbe27aa554 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:27:29 +0900 Subject: [PATCH 07/10] ARM: S5P6440: Remove usage of clk_p_low and add clk_pclk_low clock The pclk_low clock is of type 'struct clk' whereas on S5P6440, the pclk_low clock is more suitable to be of type 'struct clksrc_clk' (since pclk_low clock is a divided clock of hclk_low clock). This patch modifies the following. 1. Removes the definition and usage of clk_p_clk clock. 2. Adds the clk_pclk_low clock of type 'struct clksrc_clk' clock. 3. Adds clk_pclk_low to the list of system clocks. 4. The clock rate of pclk_low is derived from the clk_pclk_low clock. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 55 +++++++++++++++-------------------- 1 file changed, 24 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index c70b3a4075e9..80d18f54ee70 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -134,15 +134,6 @@ static struct clksrc_clk clk_mout_mpll = { .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, }; -static struct clk clk_p_low = { - .name = "pclk_low", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .ops = &clk_ops_def_setrate, -}; - enum perf_level { L0 = 532*1000, L1 = 266*1000, @@ -295,6 +286,15 @@ static struct clksrc_clk clk_hclk_low = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, }; +static struct clksrc_clk clk_pclk_low = { + .clk = { + .name = "pclk_low", + .id = -1, + .parent = &clk_hclk_low.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, +}; + int s5p6440_clk48m_ctrl(struct clk *clk, int enable) { unsigned long flags; @@ -356,31 +356,31 @@ static struct clk init_clocks_disable[] = { }, { .name = "adc", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_TSADC, }, { .name = "i2c", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_IIC0, }, { .name = "i2s_v40", .id = 0, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_IIS2, }, { .name = "spi", .id = 0, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_SPI0, }, { .name = "spi", .id = 1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_SPI1, }, { @@ -452,19 +452,19 @@ static struct clk init_clocks_disable[] = { }, { .name = "rtc", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_RTC, }, { .name = "watchdog", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_WDT, }, { .name = "timers", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_PWM, } @@ -477,31 +477,31 @@ static struct clk init_clocks[] = { { .name = "gpio", .id = -1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_GPIO, }, { .name = "uart", .id = 0, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART0, }, { .name = "uart", .id = 1, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART1, }, { .name = "uart", .id = 2, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART2, }, { .name = "uart", .id = 3, - .parent = &clk_p_low, + .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART3, } @@ -612,6 +612,7 @@ static struct clksrc_clk *sysclks[] = { &clk_hclk, &clk_pclk, &clk_hclk_low, + &clk_pclk_low, }; void __init_or_cpufreq s5p6440_setup_clocks(void) @@ -627,19 +628,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) unsigned long apll; unsigned long mpll; unsigned int ptr; - u32 clkdiv0; - u32 clkdiv3; /* Set S5P6440 functions for clk_fout_epll */ clk_fout_epll.enable = s5p6440_epll_enable; clk_fout_epll.ops = &s5p6440_epll_ops; - /* Set S5P6440 functions for arm clock */ clk_48m.enable = s5p6440_clk48m_ctrl; - clkdiv0 = __raw_readl(S5P_CLK_DIV0); - clkdiv3 = __raw_readl(S5P_CLK_DIV3); - xtal_clk = clk_get(NULL, "ext_xtal"); BUG_ON(IS_ERR(xtal_clk)); @@ -663,7 +658,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) hclk = clk_get_rate(&clk_hclk.clk); pclk = clk_get_rate(&clk_pclk.clk); hclk_low = clk_get_rate(&clk_hclk_low.clk); - pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW); + pclk_low = clk_get_rate(&clk_pclk_low.clk); printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", @@ -673,7 +668,6 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) clk_f.rate = fclk; clk_h.rate = hclk; clk_p.rate = pclk; - clk_p_low.rate = pclk_low; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); @@ -683,7 +677,6 @@ static struct clk *clks[] __initdata = { &clk_ext, &clk_iis_cd_v40, &clk_pcm_cd, - &clk_p_low, }; void __init s5p6440_register_clocks(void) From 213907dc1b974019f5eb9c94a1c62b11a515564c Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:27:47 +0900 Subject: [PATCH 08/10] ARM: S5P6440: Add clocks of type 'struct clk'. Add definitions of clocks of type 'struct clk'. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 82 ++++++++++++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index 80d18f54ee70..26b02d43a252 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -467,7 +467,73 @@ static struct clk init_clocks_disable[] = { .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_PWM, - } + }, { + .name = "hclk_fimgvg", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk1_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "tsi", + .id = -1, + .parent = &clk_hclk_low.clk, + .enable = s5p6440_hclk1_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "pclk_fimgvg", + .id = -1, + .parent = &clk_pclk.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 31), + }, { + .name = "dmc0", + .id = -1, + .parent = &clk_pclk.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 30), + }, { + .name = "etm", + .id = -1, + .parent = &clk_pclk.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 29), + }, { + .name = "dsim", + .id = -1, + .parent = &clk_pclk_low.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 28), + }, { + .name = "gps", + .id = -1, + .parent = &clk_pclk_low.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 25), + }, { + .name = "pcm", + .id = -1, + .parent = &clk_pclk_low.clk, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "irom", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 25), + }, { + .name = "dma", + .id = -1, + .parent = &clk_hclk_low.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "2d", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 8), + }, }; /* @@ -504,7 +570,19 @@ static struct clk init_clocks[] = { .parent = &clk_pclk_low.clk, .enable = s5p6440_pclk_ctrl, .ctrlbit = S5P_CLKCON_PCLK_UART3, - } + }, { + .name = "mem", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 21), + }, { + .name = "intc", + .id = -1, + .parent = &clk_hclk.clk, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = (1 << 1), + }, }; static struct clk clk_iis_cd_v40 = { From 39b7781b16614c65a53f275ff63440ea806230e2 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:27:49 +0900 Subject: [PATCH 09/10] ARM: S5P6440: Rename clkset_mmc_spi to clkset_group1 The clock source options avaialable in the clkset_mmc_spi are applicable to clocks such as sclk_post, sclk_dispcon and sclk_fimgvg. So this set is renamed as clkset_group1 to indicate that it can be used as clock sources for other clocks and not just for sclk_spi and sclk_mmc clocks. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index 26b02d43a252..b47f77d9c849 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -595,15 +595,15 @@ static struct clk clk_pcm_cd = { .id = -1, }; -static struct clk *clkset_spi_mmc_list[] = { +static struct clk *clkset_group1_list[] = { &clk_mout_epll.clk, &clk_dout_mpll.clk, &clk_fin_epll, }; -static struct clksrc_sources clkset_spi_mmc = { - .sources = clkset_spi_mmc_list, - .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), +static struct clksrc_sources clkset_group1 = { + .sources = clkset_group1_list, + .nr_sources = ARRAY_SIZE(clkset_group1_list), }; static struct clk *clkset_uart_list[] = { @@ -624,7 +624,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_MMC0, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, }, { @@ -634,7 +634,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_MMC1, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, }, { @@ -644,7 +644,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_MMC2, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, }, { @@ -664,7 +664,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_SPI0, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, }, { @@ -674,7 +674,7 @@ static struct clksrc_clk clksrcs[] = { .ctrlbit = S5P_CLKCON_SCLK0_SPI1, .enable = s5p6440_sclk_ctrl, }, - .sources = &clkset_spi_mmc, + .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, } From b3b84d652da3aba06ec26c0570ca138d8c7f1b65 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Thu, 13 May 2010 09:27:54 +0900 Subject: [PATCH 10/10] ARM: S5P6440: Add clocks of type 'struct clksrc_clk'. This patch adds the following. 1. Add new definitions of clock of type 'struct clksrc_clk'. 2. Add gate control function for GATE_SCLK1 which is required for new clock additions. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim Signed-off-by: Ben Dooks --- arch/arm/mach-s5p6440/clock.c | 60 ++++++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index b47f77d9c849..ca6e48dce777 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c @@ -336,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); } +static int s5p6440_sclk1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable); +} + static int s5p6440_mem_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); @@ -616,6 +621,19 @@ static struct clksrc_sources clkset_uart = { .nr_sources = ARRAY_SIZE(clkset_uart_list), }; +static struct clk *clkset_audio_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll.clk, + &clk_fin_epll, + &clk_iis_cd_v40, + &clk_pcm_cd, +}; + +static struct clksrc_sources clkset_audio = { + .sources = clkset_audio_list, + .nr_sources = ARRAY_SIZE(clkset_audio_list), +}; + static struct clksrc_clk clksrcs[] = { { .clk = { @@ -677,7 +695,47 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, - } + }, { + .clk = { + .name = "sclk_post", + .id = -1, + .ctrlbit = (1 << 10), + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_dispcon", + .id = -1, + .ctrlbit = (1 << 1), + .enable = s5p6440_sclk1_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimgvg", + .id = -1, + .ctrlbit = (1 << 2), + .enable = s5p6440_sclk1_ctrl, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_audio2", + .id = -1, + .ctrlbit = (1 << 11), + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_audio, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 }, + }, }; /* Clock initialisation code */