forcedeth bug fix: vitesse phy
This patch contains errata fixes for the vitesse phy. Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -550,6 +550,7 @@ union ring_type {
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/* PHY defines */
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#define PHY_OUI_MARVELL 0x5043
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#define PHY_OUI_CICADA 0x03f1
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#define PHY_OUI_VITESSE 0x01c1
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#define PHYID1_OUI_MASK 0x03ff
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#define PHYID1_OUI_SHFT 6
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#define PHYID2_OUI_MASK 0xfc00
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@ -563,6 +564,23 @@ union ring_type {
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#define PHY_CICADA_INIT4 0x0200
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#define PHY_CICADA_INIT5 0x0004
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#define PHY_CICADA_INIT6 0x02000
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#define PHY_VITESSE_INIT_REG1 0x1f
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#define PHY_VITESSE_INIT_REG2 0x10
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#define PHY_VITESSE_INIT_REG3 0x11
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#define PHY_VITESSE_INIT_REG4 0x12
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#define PHY_VITESSE_INIT_MSK1 0xc
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#define PHY_VITESSE_INIT_MSK2 0x0180
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#define PHY_VITESSE_INIT1 0x52b5
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#define PHY_VITESSE_INIT2 0xaf8a
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#define PHY_VITESSE_INIT3 0x8
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#define PHY_VITESSE_INIT4 0x8f8a
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#define PHY_VITESSE_INIT5 0xaf86
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#define PHY_VITESSE_INIT6 0x8f86
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#define PHY_VITESSE_INIT7 0xaf82
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#define PHY_VITESSE_INIT8 0x0100
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#define PHY_VITESSE_INIT9 0x8f82
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#define PHY_VITESSE_INIT10 0x0
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#define PHY_GIGABIT 0x0100
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#define PHY_TIMEOUT 0x1
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@ -1162,6 +1180,76 @@ static int phy_init(struct net_device *dev)
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return PHY_ERROR;
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}
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}
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if (np->phy_oui == PHY_OUI_VITESSE) {
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
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phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
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phy_reserved |= PHY_VITESSE_INIT3;
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
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phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
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phy_reserved |= PHY_VITESSE_INIT3;
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
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phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
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phy_reserved |= PHY_VITESSE_INIT8;
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
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printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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return PHY_ERROR;
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}
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}
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/* some phys clear out pause advertisment on reset, set it back */
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mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
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