gxfb: clean up register definitions
This does the following in preparation for register saving:
- moves the register definitions from video_gx.h and display_gx.h into
gxfb.h.
- renames GX_* registers to match their section (ie, VP_).
- renames register bitfields to match the data sheet (ie,
DC_DCFG_TGEN -> DC_DISPLAY_CFG_TGEN).
- for DC registers, rather than defining to specific addresses, use
an enum to number them sequentially and just multiply by 4(bytes) to
access them (in read_dc/write_dc).
- for VP and FP registers, use an enum and multiple by 8 (bytes). They're
64bit registers.
Signed-off-by: Andres Salomon <dilinger@debian.org>
Cc: Jordan Crouse <jordan.crouse@amd.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Andres Salomon
Linus Torvalds
parent
ab06aaf6a6
commit
d255114f22
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@ -51,20 +51,21 @@ static void gx_set_mode(struct fb_info *info)
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int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
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/* Unlock the display controller registers. */
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write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE);
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write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
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gcfg = read_dc(par, DC_GENERAL_CFG);
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dcfg = read_dc(par, DC_DISPLAY_CFG);
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/* Disable the timing generator. */
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dcfg &= ~(DC_DCFG_TGEN);
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dcfg &= ~DC_DISPLAY_CFG_TGEN;
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write_dc(par, DC_DISPLAY_CFG, dcfg);
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/* Wait for pending memory requests before disabling the FIFO load. */
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udelay(100);
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/* Disable FIFO load and compression. */
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gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
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gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
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DC_GENERAL_CFG_DECE);
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write_dc(par, DC_GENERAL_CFG, gcfg);
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/* Setup DCLK and its divisor. */
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@ -75,12 +76,13 @@ static void gx_set_mode(struct fb_info *info)
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*/
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/* Clear all unused feature bits. */
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gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
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gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
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dcfg = 0;
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/* Set FIFO priority (default 6/5) and enable. */
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/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
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gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
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gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
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(5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
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/* Framebuffer start offset. */
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write_dc(par, DC_FB_ST_OFFSET, 0);
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@ -92,25 +94,25 @@ static void gx_set_mode(struct fb_info *info)
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/* Enable graphics and video data and unmask address lines. */
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dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
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dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
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DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
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/* Set pixel format. */
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switch (info->var.bits_per_pixel) {
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case 8:
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dcfg |= DC_DCFG_DISP_MODE_8BPP;
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
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break;
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case 16:
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dcfg |= DC_DCFG_DISP_MODE_16BPP;
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dcfg |= DC_DCFG_16BPP_MODE_565;
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
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break;
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case 32:
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dcfg |= DC_DCFG_DISP_MODE_24BPP;
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dcfg |= DC_DCFG_PALB;
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
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dcfg |= DC_DISPLAY_CFG_PALB;
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break;
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}
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/* Enable timing generator. */
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dcfg |= DC_DCFG_TGEN;
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dcfg |= DC_DISPLAY_CFG_TGEN;
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/* Horizontal and vertical timings. */
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hactive = info->var.xres;
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@ -148,7 +150,7 @@ static void gx_set_mode(struct fb_info *info)
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par->vid_ops->configure_display(info);
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/* Relock display controller registers */
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write_dc(par, DC_UNLOCK, 0);
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write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
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}
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static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
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@ -19,82 +19,4 @@ extern struct geode_dc_ops gx_dc_ops;
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/* MSR that tells us if a TFT or CRT is attached */
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#define GLD_MSR_CONFIG_DM_FP 0x40
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/* Display controller registers */
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#define DC_UNLOCK 0x00
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# define DC_UNLOCK_CODE 0x00004758
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#define DC_GENERAL_CFG 0x04
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# define DC_GCFG_DFLE 0x00000001
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# define DC_GCFG_CURE 0x00000002
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# define DC_GCFG_ICNE 0x00000004
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# define DC_GCFG_VIDE 0x00000008
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# define DC_GCFG_CMPE 0x00000020
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# define DC_GCFG_DECE 0x00000040
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# define DC_GCFG_VGAE 0x00000080
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# define DC_GCFG_DFHPSL_MASK 0x00000F00
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# define DC_GCFG_DFHPSL_POS 8
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# define DC_GCFG_DFHPEL_MASK 0x0000F000
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# define DC_GCFG_DFHPEL_POS 12
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# define DC_GCFG_STFM 0x00010000
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# define DC_GCFG_FDTY 0x00020000
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# define DC_GCFG_VGAFT 0x00040000
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# define DC_GCFG_VDSE 0x00080000
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# define DC_GCFG_YUVM 0x00100000
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# define DC_GCFG_VFSL 0x00800000
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# define DC_GCFG_SIGE 0x01000000
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# define DC_GCFG_SGRE 0x02000000
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# define DC_GCFG_SGFR 0x04000000
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# define DC_GCFG_CRC_MODE 0x08000000
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# define DC_GCFG_DIAG 0x10000000
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# define DC_GCFG_CFRW 0x20000000
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#define DC_DISPLAY_CFG 0x08
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# define DC_DCFG_TGEN 0x00000001
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# define DC_DCFG_GDEN 0x00000008
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# define DC_DCFG_VDEN 0x00000010
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# define DC_DCFG_TRUP 0x00000040
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# define DC_DCFG_DISP_MODE_MASK 0x00000300
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# define DC_DCFG_DISP_MODE_8BPP 0x00000000
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# define DC_DCFG_DISP_MODE_16BPP 0x00000100
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# define DC_DCFG_DISP_MODE_24BPP 0x00000200
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# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
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# define DC_DCFG_16BPP_MODE_565 0x00000000
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# define DC_DCFG_16BPP_MODE_555 0x00000100
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# define DC_DCFG_16BPP_MODE_444 0x00000200
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# define DC_DCFG_DCEN 0x00080000
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# define DC_DCFG_PALB 0x02000000
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# define DC_DCFG_FRLK 0x04000000
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# define DC_DCFG_VISL 0x08000000
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# define DC_DCFG_FRSL 0x20000000
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# define DC_DCFG_A18M 0x40000000
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# define DC_DCFG_A20M 0x80000000
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#define DC_FB_ST_OFFSET 0x10
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#define DC_LINE_SIZE 0x30
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# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
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# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
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# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
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# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
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# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
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# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24
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#define DC_GFX_PITCH 0x34
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# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
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# define DC_GFX_PITCH_FB_PITCH_POS 0
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# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
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# define DC_GFX_PITCH_CB_PITCH_POS 16
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#define DC_H_ACTIVE_TIMING 0x40
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#define DC_H_BLANK_TIMING 0x44
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#define DC_H_SYNC_TIMING 0x48
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#define DC_V_ACTIVE_TIMING 0x50
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#define DC_V_BLANK_TIMING 0x54
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#define DC_V_SYNC_TIMING 0x58
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#define DC_PAL_ADDRESS 0x70
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#define DC_PAL_DATA 0x74
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#define DC_GLIU0_MEM_OFFSET 0x84
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#endif /* !__DISPLAY_GX1_H__ */
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@ -13,35 +13,243 @@
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#include <linux/io.h>
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/* Display Controller registers (table 6-38 from the data book) */
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enum dc_registers {
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DC_UNLOCK = 0,
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DC_GENERAL_CFG,
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DC_DISPLAY_CFG,
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DC_RSVD_0,
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DC_FB_ST_OFFSET,
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DC_CB_ST_OFFSET,
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DC_CURS_ST_OFFSET,
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DC_ICON_ST_OFFSET,
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DC_VID_Y_ST_OFFSET,
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DC_VID_U_ST_OFFSET,
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DC_VID_V_ST_OFFSET,
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DC_RSVD_1,
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DC_LINE_SIZE,
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DC_GFX_PITCH,
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DC_VID_YUV_PITCH,
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DC_RSVD_2,
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DC_H_ACTIVE_TIMING,
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DC_H_BLANK_TIMING,
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DC_H_SYNC_TIMING,
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DC_RSVD_3,
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DC_V_ACTIVE_TIMING,
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DC_V_BLANK_TIMING,
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DC_V_SYNC_TIMING,
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DC_RSVD_4,
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DC_CURSOR_X,
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DC_CURSOR_Y,
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DC_ICON_X,
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DC_LINE_CNT,
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DC_PAL_ADDRESS,
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DC_PAL_DATA,
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DC_DFIFO_DIAG,
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DC_CFIFO_DIAG,
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DC_VID_DS_DELTA,
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DC_GLIU0_MEM_OFFSET,
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DC_RSVD_5,
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DC_DV_ACC, /* 0x8c */
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};
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#define DC_UNLOCK_LOCK 0x00000000
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#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
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#define DC_GENERAL_CFG_YUVM (1 << 20)
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#define DC_GENERAL_CFG_VDSE (1 << 19)
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#define DC_GENERAL_CFG_DFHPEL_SHIFT 12
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#define DC_GENERAL_CFG_DFHPSL_SHIFT 8
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#define DC_GENERAL_CFG_DECE (1 << 6)
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#define DC_GENERAL_CFG_CMPE (1 << 5)
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#define DC_GENERAL_CFG_VIDE (1 << 3)
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#define DC_GENERAL_CFG_ICNE (1 << 2)
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#define DC_GENERAL_CFG_CURE (1 << 1)
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#define DC_GENERAL_CFG_DFLE (1 << 0)
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#define DC_DISPLAY_CFG_A20M (1 << 31)
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#define DC_DISPLAY_CFG_A18M (1 << 30)
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#define DC_DISPLAY_CFG_PALB (1 << 25)
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#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
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#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
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#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
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#define DC_DISPLAY_CFG_VDEN (1 << 4)
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#define DC_DISPLAY_CFG_GDEN (1 << 3)
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#define DC_DISPLAY_CFG_TGEN (1 << 0)
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/*
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* Video Processor registers (table 6-54).
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* There is space for 64 bit values, but we never use more than the
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* lower 32 bits. The actual register save/restore code only bothers
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* to restore those 32 bits.
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*/
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enum vp_registers {
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VP_VCFG = 0,
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VP_DCFG,
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VP_VX,
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VP_VY,
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VP_VS,
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VP_VCK,
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VP_VCM,
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VP_GAR,
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VP_GDR,
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VP_RSVD_0,
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VP_MISC,
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VP_CCS,
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VP_RSVD_1,
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VP_RSVD_2,
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VP_RSVD_3,
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VP_VDC,
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VP_VCO,
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VP_CRC,
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VP_CRC32,
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VP_VDE,
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VP_CCK,
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VP_CCM,
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VP_CC1,
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VP_CC2,
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VP_A1X,
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VP_A1Y,
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VP_A1C,
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VP_A1T,
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VP_A2X,
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VP_A2Y,
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VP_A2C,
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VP_A2T,
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VP_A3X,
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VP_A3Y,
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VP_A3C,
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VP_A3T,
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VP_VRR,
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VP_AWT,
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VP_VTM, /* 0x130 */
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};
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#define VP_VCFG_VID_EN (1 << 0)
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#define VP_DCFG_DAC_VREF (1 << 26)
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#define VP_DCFG_GV_GAM (1 << 21)
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#define VP_DCFG_VG_CK (1 << 20)
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#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
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#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
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#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
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#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
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#define VP_DCFG_FP_DATA_EN (1 << 7) /* undocumented */
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#define VP_DCFG_FP_PWR_EN (1 << 6) /* undocumented */
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#define VP_DCFG_DAC_BL_EN (1 << 3)
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#define VP_DCFG_VSYNC_EN (1 << 2)
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#define VP_DCFG_HSYNC_EN (1 << 1)
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#define VP_DCFG_CRT_EN (1 << 0)
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#define VP_MISC_GAM_EN (1 << 0)
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#define VP_MISC_DACPWRDN (1 << 10)
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#define VP_MISC_APWRDN (1 << 11)
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/*
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* Flat Panel registers (table 6-55).
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* Also 64 bit registers; see above note about 32-bit handling.
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*/
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/* we're actually in the VP register space, starting at address 0x400 */
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#define VP_FP_START 0x400
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enum fp_registers {
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FP_PT1 = 0,
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FP_PT2,
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FP_PM,
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FP_DFC,
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FP_BLFSR,
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FP_RLFSR,
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FP_FMI,
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FP_FMD,
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FP_RSVD_0,
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FP_DCA,
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FP_DMD,
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FP_CRC,
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FP_FBB, /* 0x460 */
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};
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#define FP_PT1_VSIZE_SHIFT 16 /* undocumented? */
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#define FP_PT1_VSIZE_MASK 0x7FF0000 /* undocumented? */
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#define FP_PT2_HSP (1 << 22)
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#define FP_PT2_VSP (1 << 23)
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#define FP_PM_P (1 << 24) /* panel power on */
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#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
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#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
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#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
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#define FP_PM_PANEL_ON (1 << 0) /* r/o */
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#define FP_DFC_NFI ((1 << 4) | (1 << 5) | (1 << 6))
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/* register access functions */
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static inline uint32_t read_dc(struct geodefb_par *par, int reg)
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{
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return readl(par->dc_regs + reg);
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return readl(par->dc_regs + 4*reg);
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}
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static inline void write_dc(struct geodefb_par *par, int reg, uint32_t val)
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{
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writel(val, par->dc_regs + reg);
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writel(val, par->dc_regs + 4*reg);
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}
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static inline uint32_t read_vp(struct geodefb_par *par, int reg)
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{
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return readl(par->vid_regs + reg);
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return readl(par->vid_regs + 8*reg);
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}
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static inline void write_vp(struct geodefb_par *par, int reg, uint32_t val)
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{
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writel(val, par->vid_regs + reg);
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writel(val, par->vid_regs + 8*reg);
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}
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static inline uint32_t read_fp(struct geodefb_par *par, int reg)
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{
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return readl(par->vid_regs + reg);
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return readl(par->vid_regs + 8*reg + VP_FP_START);
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}
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static inline void write_fp(struct geodefb_par *par, int reg, uint32_t val)
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{
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writel(val, par->vid_regs + reg);
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writel(val, par->vid_regs + 8*reg + VP_FP_START);
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}
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#endif
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@ -193,16 +193,16 @@ gx_configure_tft(struct fb_info *info)
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/* Turn off the panel */
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fp = read_fp(par, GX_FP_PM);
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fp &= ~GX_FP_PM_P;
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write_fp(par, GX_FP_PM, fp);
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fp = read_fp(par, FP_PM);
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fp &= ~FP_PM_P;
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write_fp(par, FP_PM, fp);
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||||
|
||||
/* Set timing 1 */
|
||||
|
||||
fp = read_fp(par, GX_FP_PT1);
|
||||
fp &= GX_FP_PT1_VSIZE_MASK;
|
||||
fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT;
|
||||
write_fp(par, GX_FP_PT1, fp);
|
||||
fp = read_fp(par, FP_PT1);
|
||||
fp &= FP_PT1_VSIZE_MASK;
|
||||
fp |= info->var.yres << FP_PT1_VSIZE_SHIFT;
|
||||
write_fp(par, FP_PT1, fp);
|
||||
|
||||
/* Timing 2 */
|
||||
/* Set bits that are always on for TFT */
|
||||
|
|
@ -212,27 +212,27 @@ gx_configure_tft(struct fb_info *info)
|
|||
/* Configure sync polarity */
|
||||
|
||||
if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
|
||||
fp |= GX_FP_PT2_VSP;
|
||||
fp |= FP_PT2_VSP;
|
||||
|
||||
if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
|
||||
fp |= GX_FP_PT2_HSP;
|
||||
fp |= FP_PT2_HSP;
|
||||
|
||||
write_fp(par, GX_FP_PT2, fp);
|
||||
write_fp(par, FP_PT2, fp);
|
||||
|
||||
/* Set the dither control */
|
||||
write_fp(par, GX_FP_DFC, 0x70);
|
||||
write_fp(par, FP_DFC, FP_DFC_NFI);
|
||||
|
||||
/* Enable the FP data and power (in case the BIOS didn't) */
|
||||
|
||||
fp = read_vp(par, GX_DCFG);
|
||||
fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN;
|
||||
write_vp(par, GX_DCFG, fp);
|
||||
fp = read_vp(par, VP_DCFG);
|
||||
fp |= VP_DCFG_FP_PWR_EN | VP_DCFG_FP_DATA_EN;
|
||||
write_vp(par, VP_DCFG, fp);
|
||||
|
||||
/* Unblank the panel */
|
||||
|
||||
fp = read_fp(par, GX_FP_PM);
|
||||
fp |= GX_FP_PM_P;
|
||||
write_fp(par, GX_FP_PM, fp);
|
||||
fp = read_fp(par, FP_PM);
|
||||
fp |= FP_PM_P;
|
||||
write_fp(par, FP_PM, fp);
|
||||
}
|
||||
|
||||
static void gx_configure_display(struct fb_info *info)
|
||||
|
|
@ -241,55 +241,55 @@ static void gx_configure_display(struct fb_info *info)
|
|||
u32 dcfg, misc;
|
||||
|
||||
/* Write the display configuration */
|
||||
dcfg = read_vp(par, GX_DCFG);
|
||||
dcfg = read_vp(par, VP_DCFG);
|
||||
|
||||
/* Disable hsync and vsync */
|
||||
dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
|
||||
write_vp(par, GX_DCFG, dcfg);
|
||||
dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
|
||||
write_vp(par, VP_DCFG, dcfg);
|
||||
|
||||
/* Clear bits from existing mode. */
|
||||
dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
|
||||
| GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
|
||||
| GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
|
||||
dcfg &= ~(VP_DCFG_CRT_SYNC_SKW
|
||||
| VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL
|
||||
| VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
|
||||
|
||||
/* Set default sync skew. */
|
||||
dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
|
||||
dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT;
|
||||
|
||||
/* Enable hsync and vsync. */
|
||||
dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
|
||||
dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN;
|
||||
|
||||
misc = read_vp(par, GX_MISC);
|
||||
misc = read_vp(par, VP_MISC);
|
||||
|
||||
/* Disable gamma correction */
|
||||
misc |= GX_MISC_GAM_EN;
|
||||
misc |= VP_MISC_GAM_EN;
|
||||
|
||||
if (par->enable_crt) {
|
||||
|
||||
/* Power up the CRT DACs */
|
||||
misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
|
||||
write_vp(par, GX_MISC, misc);
|
||||
misc &= ~(VP_MISC_APWRDN | VP_MISC_DACPWRDN);
|
||||
write_vp(par, VP_MISC, misc);
|
||||
|
||||
/* Only change the sync polarities if we are running
|
||||
* in CRT mode. The FP polarities will be handled in
|
||||
* gxfb_configure_tft */
|
||||
if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
|
||||
dcfg |= GX_DCFG_CRT_HSYNC_POL;
|
||||
dcfg |= VP_DCFG_CRT_HSYNC_POL;
|
||||
if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
|
||||
dcfg |= GX_DCFG_CRT_VSYNC_POL;
|
||||
dcfg |= VP_DCFG_CRT_VSYNC_POL;
|
||||
} else {
|
||||
/* Power down the CRT DACs if in FP mode */
|
||||
misc |= (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
|
||||
write_vp(par, GX_MISC, misc);
|
||||
misc |= (VP_MISC_APWRDN | VP_MISC_DACPWRDN);
|
||||
write_vp(par, VP_MISC, misc);
|
||||
}
|
||||
|
||||
/* Enable the display logic */
|
||||
/* Set up the DACS to blank normally */
|
||||
|
||||
dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN;
|
||||
dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN;
|
||||
|
||||
/* Enable the external DAC VREF? */
|
||||
|
||||
write_vp(par, GX_DCFG, dcfg);
|
||||
write_vp(par, VP_DCFG, dcfg);
|
||||
|
||||
/* Set up the flat panel (if it is enabled) */
|
||||
|
||||
|
|
@ -323,26 +323,26 @@ static int gx_blank_display(struct fb_info *info, int blank_mode)
|
|||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
dcfg = read_vp(par, GX_DCFG);
|
||||
dcfg &= ~(GX_DCFG_DAC_BL_EN
|
||||
| GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN);
|
||||
dcfg = read_vp(par, VP_DCFG);
|
||||
dcfg &= ~(VP_DCFG_DAC_BL_EN
|
||||
| VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN);
|
||||
if (!blank)
|
||||
dcfg |= GX_DCFG_DAC_BL_EN;
|
||||
dcfg |= VP_DCFG_DAC_BL_EN;
|
||||
if (hsync)
|
||||
dcfg |= GX_DCFG_HSYNC_EN;
|
||||
dcfg |= VP_DCFG_HSYNC_EN;
|
||||
if (vsync)
|
||||
dcfg |= GX_DCFG_VSYNC_EN;
|
||||
write_vp(par, GX_DCFG, dcfg);
|
||||
dcfg |= VP_DCFG_VSYNC_EN;
|
||||
write_vp(par, VP_DCFG, dcfg);
|
||||
|
||||
/* Power on/off flat panel. */
|
||||
|
||||
if (par->enable_crt == 0) {
|
||||
fp_pm = read_fp(par, GX_FP_PM);
|
||||
fp_pm = read_fp(par, FP_PM);
|
||||
if (blank_mode == FB_BLANK_POWERDOWN)
|
||||
fp_pm &= ~GX_FP_PM_P;
|
||||
fp_pm &= ~FP_PM_P;
|
||||
else
|
||||
fp_pm |= GX_FP_PM_P;
|
||||
write_fp(par, GX_FP_PM, fp_pm);
|
||||
fp_pm |= FP_PM_P;
|
||||
write_fp(par, FP_PM, fp_pm);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -17,45 +17,6 @@ extern struct geode_vid_ops gx_vid_ops;
|
|||
#define GX_VP_PAD_SELECT_MASK 0x3FFFFFFF
|
||||
#define GX_VP_PAD_SELECT_TFT 0x1FFFFFFF
|
||||
|
||||
/* Geode GX video processor registers */
|
||||
|
||||
#define GX_DCFG 0x0008
|
||||
# define GX_DCFG_CRT_EN 0x00000001
|
||||
# define GX_DCFG_HSYNC_EN 0x00000002
|
||||
# define GX_DCFG_VSYNC_EN 0x00000004
|
||||
# define GX_DCFG_DAC_BL_EN 0x00000008
|
||||
# define GX_DCFG_FP_PWR_EN 0x00000040
|
||||
# define GX_DCFG_FP_DATA_EN 0x00000080
|
||||
# define GX_DCFG_CRT_HSYNC_POL 0x00000100
|
||||
# define GX_DCFG_CRT_VSYNC_POL 0x00000200
|
||||
# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
|
||||
# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000
|
||||
# define GX_DCFG_VG_CK 0x00100000
|
||||
# define GX_DCFG_GV_GAM 0x00200000
|
||||
# define GX_DCFG_DAC_VREF 0x04000000
|
||||
|
||||
/* Geode GX MISC video configuration */
|
||||
|
||||
#define GX_MISC 0x50
|
||||
#define GX_MISC_GAM_EN 0x00000001
|
||||
#define GX_MISC_DAC_PWRDN 0x00000400
|
||||
#define GX_MISC_A_PWRDN 0x00000800
|
||||
|
||||
/* Geode GX flat panel display control registers */
|
||||
|
||||
#define GX_FP_PT1 0x0400
|
||||
#define GX_FP_PT1_VSIZE_MASK 0x7FF0000
|
||||
#define GX_FP_PT1_VSIZE_SHIFT 16
|
||||
|
||||
#define GX_FP_PT2 0x408
|
||||
#define GX_FP_PT2_VSP (1 << 23)
|
||||
#define GX_FP_PT2_HSP (1 << 22)
|
||||
|
||||
#define GX_FP_PM 0x410
|
||||
# define GX_FP_PM_P 0x01000000
|
||||
|
||||
#define GX_FP_DFC 0x418
|
||||
|
||||
/* Geode GX clock control MSRs */
|
||||
|
||||
# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull)
|
||||
|
|
|
|||
Loading…
Reference in New Issue