PCI: Rename PCIe capability definitions to follow convention
All other PCIe capability register fields include "PCI_EXP" + <reg-name> + <field-name>. This renames PCI_EXP_OBFF_MASK, PCI_EXP_IDO_REQ_EN, PCI_EXP_LTR_EN, and related fields using the same convention. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Samuel Ortiz <sameo@linux.intel.com> # for MFD driver
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@ -44,7 +44,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
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/* Configure LTR */
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pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
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if (cap & PCI_EXP_LTR_EN)
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if (cap & PCI_EXP_DEVCTL2_LTR_EN)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
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/* Configure OBFF */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
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@ -2095,9 +2095,9 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type)
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u16 ctrl = 0;
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if (type & PCI_EXP_IDO_REQUEST)
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ctrl |= PCI_EXP_IDO_REQ_EN;
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ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
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if (type & PCI_EXP_IDO_COMPLETION)
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ctrl |= PCI_EXP_IDO_CMP_EN;
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ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
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if (ctrl)
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
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}
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@ -2113,9 +2113,9 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type)
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u16 ctrl = 0;
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if (type & PCI_EXP_IDO_REQUEST)
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ctrl |= PCI_EXP_IDO_REQ_EN;
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ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
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if (type & PCI_EXP_IDO_COMPLETION)
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ctrl |= PCI_EXP_IDO_CMP_EN;
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ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
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if (ctrl)
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
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}
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@ -2147,7 +2147,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
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int ret;
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pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
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if (!(cap & PCI_EXP_OBFF_MASK))
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if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK))
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return -ENOTSUPP; /* no OBFF support at all */
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/* Make sure the topology supports OBFF as well */
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@ -2158,17 +2158,17 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
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}
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pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
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if (cap & PCI_EXP_OBFF_WAKE)
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ctrl |= PCI_EXP_OBFF_WAKE_EN;
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if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE)
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ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
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else {
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switch (type) {
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case PCI_EXP_OBFF_SIGNAL_L0:
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if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
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ctrl |= PCI_EXP_OBFF_MSGA_EN;
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if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN))
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ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN;
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break;
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case PCI_EXP_OBFF_SIGNAL_ALWAYS:
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ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
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ctrl |= PCI_EXP_OBFF_MSGB_EN;
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ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
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ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN;
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break;
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default:
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WARN(1, "bad OBFF signal type\n");
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@ -2189,7 +2189,8 @@ EXPORT_SYMBOL(pci_enable_obff);
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*/
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void pci_disable_obff(struct pci_dev *dev)
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{
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_OBFF_WAKE_EN);
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}
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EXPORT_SYMBOL(pci_disable_obff);
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@ -2237,7 +2238,8 @@ int pci_enable_ltr(struct pci_dev *dev)
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return ret;
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}
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return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
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return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_LTR_EN);
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}
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EXPORT_SYMBOL(pci_enable_ltr);
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@ -2254,7 +2256,8 @@ void pci_disable_ltr(struct pci_dev *dev)
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if (!pci_ltr_supported(dev))
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return;
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_LTR_EN);
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}
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EXPORT_SYMBOL(pci_disable_ltr);
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@ -550,19 +550,19 @@
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* to use these fields safely.
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*/
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#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
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#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
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#define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */
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#define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */
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#define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */
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#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
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#define PCI_EXP_DEVCAP2_OBFF_MASK 0xc0000 /* OBFF support mechanism */
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x40000 /* New message signaling */
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#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
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#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
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#define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */
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#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
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#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
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#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
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#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
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#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
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#define PCI_EXP_DEVCTL2_LTR_EN 0x400 /* Latency tolerance reporting */
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#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
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#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
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#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
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#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
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#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
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