mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllers
commit60d5356610
upstream. A UHS setting of SDR25 can give better results for High Speed mode. This is because there is no setting corresponding to high speed. Currently SDHCI sets no value, which means zero which is also the setting for SDR12. There was an attempt to change this in sdhci.c but it caused problems for some drivers, so it was reverted and the change was made to sdhci-brcmstb in commit2fefc7c5f7
("mmc: sdhci-brcmstb: Fix incorrect switch to HS mode"). Several other drivers also do this. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v5.4+ Link: https://lore.kernel.org/r/20201112133656.20317-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -669,6 +669,15 @@ static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
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}
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}
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}
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}
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static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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/* Set UHS timing to SDR25 for High Speed mode */
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if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
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timing = MMC_TIMING_UHS_SDR25;
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sdhci_set_uhs_signaling(host, timing);
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}
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#define INTEL_HS400_ES_REG 0x78
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#define INTEL_HS400_ES_REG 0x78
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#define INTEL_HS400_ES_BIT BIT(0)
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#define INTEL_HS400_ES_BIT BIT(0)
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@ -725,7 +734,7 @@ static const struct sdhci_ops sdhci_intel_byt_ops = {
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.enable_dma = sdhci_pci_enable_dma,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.set_uhs_signaling = sdhci_intel_set_uhs_signaling,
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.hw_reset = sdhci_pci_hw_reset,
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.hw_reset = sdhci_pci_hw_reset,
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};
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};
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@ -735,7 +744,7 @@ static const struct sdhci_ops sdhci_intel_glk_ops = {
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.enable_dma = sdhci_pci_enable_dma,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_cqhci_reset,
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.reset = sdhci_cqhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.set_uhs_signaling = sdhci_intel_set_uhs_signaling,
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.hw_reset = sdhci_pci_hw_reset,
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.hw_reset = sdhci_pci_hw_reset,
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.irq = sdhci_cqhci_irq,
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.irq = sdhci_cqhci_irq,
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};
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};
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