ARM: tegra: SoC-specific core code changes
This branch contains various miscellaneous changes to code in the mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict with anything else. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSr3IGAAoJEMzrak5tbycxVVUP/09VfeFYOidIm6mgbWSMlL4l DEPzrGBOvyO60og4LIbDIgwDzkcEsxIF9erlrVTz1Fvh2p0P0sQycIKjvyhvNXeh Ft9TQ1kDHjoJcfHI9f8tapkmwhOG+6vy2gDrTPmyxjnLpiE5ccM18CCr5CMK+y2v Ojzmf2paPBFyI84gcdWuwF4Ze2YmwdHmG7TksG/PZrpicizSxe+d9wNVDBMkJnP6 QFicMU6DEFZVwwDkFx4qPYrFDJPk8dqcAmNl+F+9jGEqTmxA+7M8eOF/SQa62lwa OJrVugD8YigT5NjRW/9btOVY/jUHbg0Ekj5DXd7Q9rO5KNUrFDRSia5XiWmms/S8 QNJezmjNgA83OQDefuAkpsKydf1XGoyIQ9EjDUb4i807PRwTO4En+1pD0EpEWSet 0c1mfDvU5uC6L9A5VvR0pzyGz2U2EhNhkUz03WAqtWYdrR68vIZHNZVIvHOLuwWF fDkS26KxziOmKM1ePdL7wemuNOod8ACeyzXMa2dhR68l6LH1X1pnMaoxvk2AjETk SMat9tsxY827+TtQlAQ+4bdR3qXqYsQLD7VWOPO0V3fs5T08jVZrpJ9pHDRYW88K dGHmIW4sHXKXP4Qw9rDGWSkWZeOVJYr72U6uH9vbg8hK6Wi2eAMxZ27ngFiqahSK PIhnAfsdM2/FX+C+vu58 =Oztt -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc From Stephen Warren: ARM: tegra: SoC-specific core code changes This branch contains various miscellaneous changes to code in the mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict with anything else. * tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC ARM: tegra: use section-sized static mappings for LPAE too ARM: tegra: don't hard-code DEBUG_LL baud rate ARM: tegra: fix DEBUG_LL combined with LPAE ARM: tegra: switch FUSE clock on before usage Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
d578759ed8
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@ -46,10 +46,10 @@
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#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
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/*
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* Must be 1MB-aligned since a 1MB mapping is used early on.
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* Must be section-aligned since a section mapping is used early on.
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* Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
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*/
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#define UART_VIRTUAL_BASE 0xfe100000
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#define UART_VIRTUAL_BASE 0xfe800000
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#define checkuart(rp, rv, lhu, bit, uart) \
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/* Load address of CLK_RST register */ \
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@ -156,28 +156,6 @@
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92: and \rv, \rp, #0xffffff @ offset within 1MB section
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add \rv, \rv, #UART_VIRTUAL_BASE
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str \rv, [\tmp, #8] @ Store in tegra_uart_virt
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movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
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movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
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ldr \rv, [\rv, #0] @ Load HIDREV
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ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
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cmp \rv, #0x20 @ Tegra20?
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moveq \rv, #0x75 @ Tegra20 divisor
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movne \rv, #0xdd @ Tegra30 divisor
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str \rv, [\tmp, #12] @ Save divisor to scratch
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/* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
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mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
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str \rv, [\rp, #UART_LCR << UART_SHIFT]
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/* uart[UART_DLL] = div & 0xff; */
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ldr \rv, [\tmp, #12]
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and \rv, \rv, #0xff
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str \rv, [\rp, #UART_DLL << UART_SHIFT]
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/* uart[UART_DLM] = div >> 8; */
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ldr \rv, [\tmp, #12]
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lsr \rv, \rv, #8
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str \rv, [\rp, #UART_DLM << UART_SHIFT]
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/* uart[UART_LCR] = UART_LCR_WLEN8; */
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mov \rv, #UART_LCR_WLEN8
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str \rv, [\rp, #UART_LCR << UART_SHIFT]
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b 100f
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.align
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@ -205,8 +183,8 @@
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cmp \rx, #0
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beq 1002f
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1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
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and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
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teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
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and \rd, \rd, #UART_LSR_THRE
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teq \rd, #UART_LSR_THRE
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bne 1001b
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1002:
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.endm
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@ -225,7 +203,7 @@
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/*
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* Storage for the state maintained by the macros above.
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*
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* In the kernel proper, this data is located in arch/arm/mach-tegra/common.c.
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* In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
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* That's because this header is included from multiple files, and we only
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* want a single copy of the data. In particular, the UART probing code above
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* assumes it's running using physical addresses. This is true when this file
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@ -247,6 +225,4 @@ tegra_uart_config:
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.word 0
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/* Debug UART virtual address */
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.word 0
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/* Scratch space for debug macro */
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.word 0
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#endif
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@ -65,6 +65,7 @@ config ARCH_TEGRA_124_SOC
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bool "Enable support for Tegra124 family"
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select ARM_L1_CACHE_SHIFT_6
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA124
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help
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Support for NVIDIA Tegra T124 processor family, based on the
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ARM CortexA15MP CPU
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@ -22,6 +22,7 @@
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/random.h>
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#include <linux/clk.h>
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#include <linux/tegra-soc.h>
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#include "fuse.h"
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@ -54,6 +55,7 @@ int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
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int tegra_soc_speedo_id;
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enum tegra_revision tegra_revision;
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static struct clk *fuse_clk;
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static int tegra_fuse_spare_bit;
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static void (*tegra_init_speedo_data)(void);
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@ -77,6 +79,22 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
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[TEGRA_REVISION_A04] = "A04",
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};
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static void tegra_fuse_enable_clk(void)
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{
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if (IS_ERR(fuse_clk))
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fuse_clk = clk_get_sys(NULL, "fuse");
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if (IS_ERR(fuse_clk))
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return;
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clk_prepare_enable(fuse_clk);
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}
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static void tegra_fuse_disable_clk(void)
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{
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if (IS_ERR(fuse_clk))
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return;
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clk_disable_unprepare(fuse_clk);
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}
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u32 tegra_fuse_readl(unsigned long offset)
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{
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return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
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@ -84,7 +102,15 @@ u32 tegra_fuse_readl(unsigned long offset)
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bool tegra_spare_fuse(int bit)
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{
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return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
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bool ret;
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tegra_fuse_enable_clk();
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ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
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tegra_fuse_disable_clk();
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return ret;
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}
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static enum tegra_revision tegra_get_revision(u32 id)
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@ -113,10 +139,14 @@ static void tegra_get_process_id(void)
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{
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u32 reg;
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tegra_fuse_enable_clk();
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reg = tegra_fuse_readl(tegra_fuse_spare_bit);
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tegra_cpu_process_id = (reg >> 6) & 3;
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reg = tegra_fuse_readl(tegra_fuse_spare_bit);
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tegra_core_process_id = (reg >> 12) & 3;
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tegra_fuse_disable_clk();
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}
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u32 tegra_read_chipid(void)
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@ -159,6 +189,15 @@ void __init tegra_init_fuse(void)
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reg |= 1 << 28;
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writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
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/*
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* Enable FUSE clock. This needs to be hardcoded because the clock
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* subsystem is not active during early boot.
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*/
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reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
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reg |= 1 << 7;
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writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
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fuse_clk = ERR_PTR(-EINVAL);
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reg = tegra_fuse_readl(FUSE_SKU_INFO);
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randomness[0] = reg;
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tegra_sku_id = reg & 0xFF;
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@ -19,6 +19,7 @@
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#ifndef __MACH_TEGRA_IOMAP_H
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#define __MACH_TEGRA_IOMAP_H
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#include <asm/pgtable.h>
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#include <asm/sizes.h>
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#define TEGRA_IRAM_BASE 0x40000000
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@ -115,27 +116,26 @@
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* two 256MB io windows (that actually only use about 64KB
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* at the start of each).
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*
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* We will just map the first 1MB of each window (to minimize
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* We will just map the first MMU section of each window (to minimize
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* pt entries needed) and provide a macro to transform physical
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* io addresses to an appropriate void __iomem *.
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*
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*/
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#define IO_IRAM_PHYS 0x40000000
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#define IO_IRAM_VIRT IOMEM(0xFE400000)
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#define IO_IRAM_SIZE SZ_256K
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#define IO_CPU_PHYS 0x50040000
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#define IO_CPU_VIRT IOMEM(0xFE000000)
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#define IO_CPU_PHYS 0x50040000
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#define IO_CPU_VIRT IOMEM(0xFE440000)
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#define IO_CPU_SIZE SZ_16K
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#define IO_PPSB_PHYS 0x60000000
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#define IO_PPSB_VIRT IOMEM(0xFE200000)
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#define IO_PPSB_SIZE SZ_1M
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#define IO_PPSB_SIZE SECTION_SIZE
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#define IO_APB_PHYS 0x70000000
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#define IO_APB_VIRT IOMEM(0xFE300000)
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#define IO_APB_SIZE SZ_1M
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#define IO_APB_VIRT IOMEM(0xFE000000)
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#define IO_APB_SIZE SECTION_SIZE
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#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
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#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
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@ -60,15 +60,13 @@
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* kernel is loaded. The data is declared here rather than debug-macro.S so
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* that multiple inclusions of debug-macro.S point at the same data.
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*/
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u32 tegra_uart_config[4] = {
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u32 tegra_uart_config[3] = {
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/* Debug UART initialization required */
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1,
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/* Debug UART physical address */
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0,
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/* Debug UART virtual address */
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0,
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/* Scratch space for debug macro */
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0,
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};
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static void __init tegra_init_cache(void)
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