arm64 fixes for 5.0
- Fix handling of PSTATE.SSBS bit in sigreturn() - Fix version checking of the GIC during early boot - Fix clang builds failing due to use of NEON in the crypto code -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAlxtk30ACgkQt6xw3ITB YzSGygf/U9P//TbPwGP2ZrCLHelJ8okYMZgJB3R/MLpGrV/MPWbN39JNMydXUPNT Kn21TzQeYnGp4blIC5S8RQMJnrqbR03L4ch6DVrFWGJZVkfI3WFefASHUe+Hg/WB d8GCkiqIMO+qX9+o6e+kPts3bgGsGvYEQF0vvdX6DbNXVkqusJ6TSIEAgEYUQH97 NzIqEfu6xYgmjultmMemfstaWaHI5Mfwx0fSdFhVfCDYKfoAj3U7LDRT9NFEAkTc cxxZ3Z/BnJYPOhoqboIceZz499g++1SnISTEIIrGHKa51tK/Nuunaarsr1ZbB4gz BLQhrJxbxxtbdkfDGA7u2mSQupCRbA== =ujCB -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull late arm64 fixes from Will Deacon: "Three small arm64 fixes for 5.0. They fix a build breakage with clang introduced in 4.20, an oversight in our sigframe restoration relating to the SSBS bit and a boot fix for systems with newer revisions of our interrupt controller. Summary: - Fix handling of PSTATE.SSBS bit in sigreturn() - Fix version checking of the GIC during early boot - Fix clang builds failing due to use of NEON in the crypto code" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Relax GIC version check during early boot arm64/neon: Disable -Wincompatible-pointer-types when building with Clang arm64: fix SSBS sanitization
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d6622d913a
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@ -36,4 +36,8 @@
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#include <arm_neon.h>
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#include <arm_neon.h>
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#endif
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#endif
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#ifdef CONFIG_CC_IS_CLANG
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#pragma clang diagnostic ignored "-Wincompatible-pointer-types"
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#endif
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#endif /* __ASM_NEON_INTRINSICS_H */
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#endif /* __ASM_NEON_INTRINSICS_H */
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@ -539,8 +539,7 @@ set_hcr:
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/* GICv3 system register access */
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/* GICv3 system register access */
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mrs x0, id_aa64pfr0_el1
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #24, #4
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ubfx x0, x0, #24, #4
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cmp x0, #1
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cbz x0, 3f
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b.ne 3f
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mrs_s x0, SYS_ICC_SRE_EL2
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mrs_s x0, SYS_ICC_SRE_EL2
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orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
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orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
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@ -1702,19 +1702,20 @@ void syscall_trace_exit(struct pt_regs *regs)
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}
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}
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/*
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/*
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* SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487C.a
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* SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a.
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* We also take into account DIT (bit 24), which is not yet documented, and
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* We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is
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* treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may be
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* not described in ARM DDI 0487D.a.
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* allocated an EL0 meaning in future.
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* We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may
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* be allocated an EL0 meaning in future.
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* Userspace cannot use these until they have an architectural meaning.
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* Userspace cannot use these until they have an architectural meaning.
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* Note that this follows the SPSR_ELx format, not the AArch32 PSR format.
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* Note that this follows the SPSR_ELx format, not the AArch32 PSR format.
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* We also reserve IL for the kernel; SS is handled dynamically.
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* We also reserve IL for the kernel; SS is handled dynamically.
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*/
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*/
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#define SPSR_EL1_AARCH64_RES0_BITS \
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#define SPSR_EL1_AARCH64_RES0_BITS \
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(GENMASK_ULL(63,32) | GENMASK_ULL(27, 25) | GENMASK_ULL(23, 22) | \
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(GENMASK_ULL(63, 32) | GENMASK_ULL(27, 25) | GENMASK_ULL(23, 22) | \
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GENMASK_ULL(20, 10) | GENMASK_ULL(5, 5))
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GENMASK_ULL(20, 13) | GENMASK_ULL(11, 10) | GENMASK_ULL(5, 5))
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#define SPSR_EL1_AARCH32_RES0_BITS \
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#define SPSR_EL1_AARCH32_RES0_BITS \
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(GENMASK_ULL(63,32) | GENMASK_ULL(23, 22) | GENMASK_ULL(20,20))
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(GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20))
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static int valid_compat_regs(struct user_pt_regs *regs)
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static int valid_compat_regs(struct user_pt_regs *regs)
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{
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{
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