alpha: dp264: Convert irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Matt Turner <mattst88@gmail.com>
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118b4691da
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d677f4508a
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@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask)
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}
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static void
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dp264_enable_irq(unsigned int irq)
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dp264_enable_irq(struct irq_data *d)
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{
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spin_lock(&dp264_irq_lock);
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cached_irq_mask |= 1UL << irq;
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cached_irq_mask |= 1UL << d->irq;
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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}
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static void
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dp264_disable_irq(unsigned int irq)
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dp264_disable_irq(struct irq_data *d)
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{
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spin_lock(&dp264_irq_lock);
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cached_irq_mask &= ~(1UL << irq);
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cached_irq_mask &= ~(1UL << d->irq);
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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}
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static void
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clipper_enable_irq(unsigned int irq)
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clipper_enable_irq(struct irq_data *d)
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{
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spin_lock(&dp264_irq_lock);
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cached_irq_mask |= 1UL << (irq - 16);
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cached_irq_mask |= 1UL << (d->irq - 16);
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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}
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static void
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clipper_disable_irq(unsigned int irq)
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clipper_disable_irq(struct irq_data *d)
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{
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spin_lock(&dp264_irq_lock);
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cached_irq_mask &= ~(1UL << (irq - 16));
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cached_irq_mask &= ~(1UL << (d->irq - 16));
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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}
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@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
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}
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static int
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dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
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dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
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bool force)
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{
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spin_lock(&dp264_irq_lock);
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cpu_set_irq_affinity(irq, *affinity);
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cpu_set_irq_affinity(d->irq, *affinity);
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
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}
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static int
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clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
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clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
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bool force)
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{
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spin_lock(&dp264_irq_lock);
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cpu_set_irq_affinity(irq - 16, *affinity);
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cpu_set_irq_affinity(d->irq - 16, *affinity);
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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@ -172,18 +174,18 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
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static struct irq_chip dp264_irq_type = {
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.name = "DP264",
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.unmask = dp264_enable_irq,
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.mask = dp264_disable_irq,
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.mask_ack = dp264_disable_irq,
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.set_affinity = dp264_set_affinity,
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.irq_unmask = dp264_enable_irq,
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.irq_mask = dp264_disable_irq,
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.irq_mask_ack = dp264_disable_irq,
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.irq_set_affinity = dp264_set_affinity,
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};
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static struct irq_chip clipper_irq_type = {
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.name = "CLIPPER",
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.unmask = clipper_enable_irq,
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.mask = clipper_disable_irq,
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.mask_ack = clipper_disable_irq,
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.set_affinity = clipper_set_affinity,
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.irq_unmask = clipper_enable_irq,
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.irq_mask = clipper_disable_irq,
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.irq_mask_ack = clipper_disable_irq,
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.irq_set_affinity = clipper_set_affinity,
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};
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static void
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@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
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{
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long i;
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for (i = imin; i <= imax; ++i) {
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irq_to_desc(i)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(i, ops, handle_level_irq);
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irq_set_status_flags(i, IRQ_LEVEL);
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}
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}
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