ARM i.MX23: remove reserved register defines
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Wolfram Sang <w.sang@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
0e8b462de0
commit
d69934bc7b
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@ -33,10 +33,6 @@
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#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
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#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
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#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30
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#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000
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#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
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(((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
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#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
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#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
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#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
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@ -45,10 +41,6 @@
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#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
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#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
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#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
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#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26
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#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000
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#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \
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(((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
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#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
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#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
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#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
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@ -57,10 +49,6 @@
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#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
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#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
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#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
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#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22
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#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000
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#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \
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(((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
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#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
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#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
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#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
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@ -69,23 +57,13 @@
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#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
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#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
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#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
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#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000
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#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
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#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000
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#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
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#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0
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#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF
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#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \
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(((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
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#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
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#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
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#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
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#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16
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#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000
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#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \
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(((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
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#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
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#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
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#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
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@ -96,29 +74,15 @@
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#define HW_CLKCTRL_CPU_CLR (0x00000028)
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#define HW_CLKCTRL_CPU_TOG (0x0000002c)
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#define BP_CLKCTRL_CPU_RSRVD5 30
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#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
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#define BF_CLKCTRL_CPU_RSRVD5(v) \
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(((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
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#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
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#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
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#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
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#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
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#define BP_CLKCTRL_CPU_DIV_XTAL 16
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#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
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#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
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(((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
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#define BP_CLKCTRL_CPU_RSRVD3 13
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#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
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#define BF_CLKCTRL_CPU_RSRVD3(v) \
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(((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
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#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
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#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
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#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
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#define BP_CLKCTRL_CPU_RSRVD1 6
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#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
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#define BF_CLKCTRL_CPU_RSRVD1(v) \
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(((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
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#define BP_CLKCTRL_CPU_DIV_CPU 0
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#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
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#define BF_CLKCTRL_CPU_DIV_CPU(v) \
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@ -129,10 +93,6 @@
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#define HW_CLKCTRL_HBUS_CLR (0x00000038)
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#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
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#define BP_CLKCTRL_HBUS_RSRVD4 30
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#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000
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#define BF_CLKCTRL_HBUS_RSRVD4(v) \
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(((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
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#define BM_CLKCTRL_HBUS_BUSY 0x20000000
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#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
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#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
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@ -143,7 +103,6 @@
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#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
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#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
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#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
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#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000
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#define BP_CLKCTRL_HBUS_SLOW_DIV 16
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#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
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#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
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@ -154,10 +113,6 @@
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
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#define BP_CLKCTRL_HBUS_RSRVD1 6
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#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
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#define BF_CLKCTRL_HBUS_RSRVD1(v) \
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(((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
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#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
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#define BP_CLKCTRL_HBUS_DIV 0
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#define BM_CLKCTRL_HBUS_DIV 0x0000001F
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@ -167,10 +122,6 @@
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#define HW_CLKCTRL_XBUS (0x00000040)
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#define BM_CLKCTRL_XBUS_BUSY 0x80000000
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#define BP_CLKCTRL_XBUS_RSRVD1 11
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#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800
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#define BF_CLKCTRL_XBUS_RSRVD1(v) \
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(((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
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#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
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#define BP_CLKCTRL_XBUS_DIV 0
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#define BM_CLKCTRL_XBUS_DIV 0x000003FF
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@ -192,10 +143,6 @@
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#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
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#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
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#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
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#define BP_CLKCTRL_XTAL_RSRVD1 2
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#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
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#define BF_CLKCTRL_XTAL_RSRVD1(v) \
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(((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
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#define BP_CLKCTRL_XTAL_DIV_UART 0
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#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
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#define BF_CLKCTRL_XTAL_DIV_UART(v) \
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@ -205,12 +152,7 @@
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#define BP_CLKCTRL_PIX_CLKGATE 31
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#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
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#define BM_CLKCTRL_PIX_RSRVD2 0x40000000
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#define BM_CLKCTRL_PIX_BUSY 0x20000000
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#define BP_CLKCTRL_PIX_RSRVD1 13
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#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000
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#define BF_CLKCTRL_PIX_RSRVD1(v) \
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(((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
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#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
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#define BP_CLKCTRL_PIX_DIV 0
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#define BM_CLKCTRL_PIX_DIV 0x00000FFF
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@ -221,12 +163,7 @@
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#define BP_CLKCTRL_SSP_CLKGATE 31
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#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
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#define BM_CLKCTRL_SSP_RSRVD2 0x40000000
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#define BM_CLKCTRL_SSP_BUSY 0x20000000
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#define BP_CLKCTRL_SSP_RSRVD1 10
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#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00
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#define BF_CLKCTRL_SSP_RSRVD1(v) \
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(((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
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#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
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#define BP_CLKCTRL_SSP_DIV 0
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#define BM_CLKCTRL_SSP_DIV 0x000001FF
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@ -237,12 +174,7 @@
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#define BP_CLKCTRL_GPMI_CLKGATE 31
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#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
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#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
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#define BM_CLKCTRL_GPMI_BUSY 0x20000000
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#define BP_CLKCTRL_GPMI_RSRVD1 11
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#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
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#define BF_CLKCTRL_GPMI_RSRVD1(v) \
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(((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
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#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
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#define BP_CLKCTRL_GPMI_DIV 0
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#define BM_CLKCTRL_GPMI_DIV 0x000003FF
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@ -252,10 +184,6 @@
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#define HW_CLKCTRL_SPDIF (0x00000090)
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#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
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#define BP_CLKCTRL_SPDIF_RSRVD 0
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#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
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#define BF_CLKCTRL_SPDIF_RSRVD(v) \
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(((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
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#define HW_CLKCTRL_EMI (0x000000a0)
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@ -266,24 +194,12 @@
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#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
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#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
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#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
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#define BP_CLKCTRL_EMI_RSRVD3 18
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#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
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#define BF_CLKCTRL_EMI_RSRVD3(v) \
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(((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
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#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
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#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
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#define BP_CLKCTRL_EMI_RSRVD2 12
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#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
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#define BF_CLKCTRL_EMI_RSRVD2(v) \
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(((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
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#define BP_CLKCTRL_EMI_DIV_XTAL 8
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#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
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#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
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(((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
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#define BP_CLKCTRL_EMI_RSRVD1 6
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#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
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#define BF_CLKCTRL_EMI_RSRVD1(v) \
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(((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
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#define BP_CLKCTRL_EMI_DIV_EMI 0
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#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
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#define BF_CLKCTRL_EMI_DIV_EMI(v) \
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@ -292,22 +208,13 @@
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#define HW_CLKCTRL_IR (0x000000b0)
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#define BM_CLKCTRL_IR_CLKGATE 0x80000000
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#define BM_CLKCTRL_IR_RSRVD3 0x40000000
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#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
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#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
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#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
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#define BP_CLKCTRL_IR_RSRVD2 25
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#define BM_CLKCTRL_IR_RSRVD2 0x06000000
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#define BF_CLKCTRL_IR_RSRVD2(v) \
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(((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
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#define BP_CLKCTRL_IR_IROV_DIV 16
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#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
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#define BF_CLKCTRL_IR_IROV_DIV(v) \
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(((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
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#define BP_CLKCTRL_IR_RSRVD1 10
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#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00
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#define BF_CLKCTRL_IR_RSRVD1(v) \
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(((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
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#define BP_CLKCTRL_IR_IR_DIV 0
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#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
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#define BF_CLKCTRL_IR_IR_DIV(v) \
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@ -316,12 +223,7 @@
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#define HW_CLKCTRL_SAIF (0x000000c0)
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#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
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#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000
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#define BM_CLKCTRL_SAIF_BUSY 0x20000000
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#define BP_CLKCTRL_SAIF_RSRVD1 17
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#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000
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#define BF_CLKCTRL_SAIF_RSRVD1(v) \
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(((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
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#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
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#define BP_CLKCTRL_SAIF_DIV 0
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#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
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@ -332,20 +234,11 @@
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#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
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#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
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#define BP_CLKCTRL_TV_RSRVD 0
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#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF
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#define BF_CLKCTRL_TV_RSRVD(v) \
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(((v) << 0) & BM_CLKCTRL_TV_RSRVD)
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#define HW_CLKCTRL_ETM (0x000000e0)
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#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
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#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
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#define BM_CLKCTRL_ETM_BUSY 0x20000000
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#define BP_CLKCTRL_ETM_RSRVD1 7
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#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80
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#define BF_CLKCTRL_ETM_RSRVD1(v) \
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(((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
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#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
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#define BP_CLKCTRL_ETM_DIV 0
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#define BM_CLKCTRL_ETM_DIV 0x0000003F
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@ -393,36 +286,23 @@
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#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
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#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
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#define BP_CLKCTRL_FRAC1_RSRVD1 0
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#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
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#define BF_CLKCTRL_FRAC1_RSRVD1(v) \
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(((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
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#define HW_CLKCTRL_CLKSEQ (0x00000110)
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#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
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#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
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#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
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#define BP_CLKCTRL_CLKSEQ_RSRVD1 9
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#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00
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#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
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(((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
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#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
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#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
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#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
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#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
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#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
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#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
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#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004
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#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
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#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
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#define HW_CLKCTRL_RESET (0x00000120)
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#define BP_CLKCTRL_RESET_RSRVD 2
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#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC
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#define BF_CLKCTRL_RESET_RSRVD(v) \
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(((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
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#define BM_CLKCTRL_RESET_CHIP 0x00000002
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#define BM_CLKCTRL_RESET_DIG 0x00000001
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@ -432,10 +312,6 @@
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#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
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#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
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(((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
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#define BP_CLKCTRL_STATUS_RSRVD 0
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#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
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#define BF_CLKCTRL_STATUS_RSRVD(v) \
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(((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
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#define HW_CLKCTRL_VERSION (0x00000140)
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