staging: brcm80211: cleaned up softmac nicpci.c/nicpci.h macro's
Substituted macro's. Reported-by: Johannes Berg <johannes@sipsolutions.net> Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Roland Vossen
Greg Kroah-Hartman
parent
0d62b4db56
commit
d708438019
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@ -127,6 +127,18 @@
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/* PCIE protocol TLP diagnostic registers */
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#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
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/* Sonics to PCI translation types */
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#define SBTOPCI_PREF 0x4 /* prefetch enable */
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#define SBTOPCI_BURST 0x8 /* burst enable */
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#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
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#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */
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/* PCI core index in SROM shadow area */
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#define SRSH_PI_OFFSET 0 /* first word */
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#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
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#define SRSH_PI_SHIFT 12 /* bit 15:12 */
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/* Sonics side: PCI core and host control registers */
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struct sbpciregs {
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u32 control; /* PCI control */
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@ -211,18 +223,17 @@ struct pcicore_info {
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bool pmecap; /* Capable of generating PME */
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};
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/* debug/trace */
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#define PCI_ERROR(args)
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#define PCIE_PUB(sih) ((sih)->buscoretype == PCIE_CORE_ID)
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#define PCIE_ASPM(sih) \
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((PCIE_PUB(sih)) && \
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(((sih)->buscoretype == PCIE_CORE_ID) && \
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(((sih)->buscorerev >= 3) && \
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((sih)->buscorerev <= 5)))
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/* delay needed between the mdio control/ mdiodata register data access */
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#define PR28829_DELAY() udelay(10)
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static void pr28829_delay(void)
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{
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udelay(10);
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}
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/* Initialize the PCI core.
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* It's caller's responsibility to make sure that this is done only once
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@ -235,7 +246,6 @@ struct pcicore_info *pcicore_init(struct si_pub *sih, struct pci_dev *pdev,
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/* alloc struct pcicore_info */
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pi = kzalloc(sizeof(struct pcicore_info), GFP_ATOMIC);
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if (pi == NULL) {
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PCI_ERROR(("pci_attach: malloc failed!\n"));
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return NULL;
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}
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@ -375,7 +385,7 @@ static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
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(blk << 4));
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W_REG(&pcieregs->mdiodata, mdiodata);
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PR28829_DELAY();
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pr28829_delay();
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/* retry till the transaction is complete */
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while (i < pcie_serdes_spinwait) {
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if (R_REG(&pcieregs->mdiocontrol) & MDIOCTL_ACCESS_DONE)
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@ -386,7 +396,6 @@ static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
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}
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if (i >= pcie_serdes_spinwait) {
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PCI_ERROR(("pcie_mdiosetblock: timed out\n"));
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return false;
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}
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@ -427,13 +436,13 @@ pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
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W_REG(&pcieregs->mdiodata, mdiodata);
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PR28829_DELAY();
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pr28829_delay();
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/* retry till the transaction is complete */
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while (i < pcie_serdes_spinwait) {
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if (R_REG(&pcieregs->mdiocontrol) & MDIOCTL_ACCESS_DONE) {
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if (!write) {
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PR28829_DELAY();
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pr28829_delay();
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*val = (R_REG(&pcieregs->mdiodata) &
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MDIODATA_MASK);
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}
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@ -445,8 +454,7 @@ pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
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i++;
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}
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PCI_ERROR(("pcie_mdioop: timed out op: %d\n", write));
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/* Disable mdio access to SERDES */
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/* Timed out. Disable mdio access to SERDES. */
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W_REG(&pcieregs->mdiocontrol, 0);
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return 1;
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}
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@ -498,7 +506,7 @@ static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
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struct si_pub *sih = pi->sih;
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struct sbpcieregs *pcieregs = pi->regs.pcieregs;
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if (!PCIE_PUB(sih) || sih->buscorerev < 7)
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if (sih->buscoretype != PCIE_CORE_ID || sih->buscorerev < 7)
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return;
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w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
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@ -736,7 +744,7 @@ void pcicore_attach(struct pcicore_info *pi, char *pvars, int state)
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void pcicore_hwup(struct pcicore_info *pi)
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{
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if (!pi || !PCIE_PUB(pi->sih))
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if (!pi || pi->sih->buscoretype != PCIE_CORE_ID)
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return;
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pcie_war_pci_setup(pi);
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@ -744,7 +752,7 @@ void pcicore_hwup(struct pcicore_info *pi)
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void pcicore_up(struct pcicore_info *pi, int state)
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{
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if (!pi || !PCIE_PUB(pi->sih))
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if (!pi || pi->sih->buscoretype != PCIE_CORE_ID)
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return;
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/* Restore L1 timer for better performance */
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@ -772,7 +780,7 @@ void pcicore_sleep(struct pcicore_info *pi)
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void pcicore_down(struct pcicore_info *pi, int state)
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{
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if (!pi || !PCIE_PUB(pi->sih))
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if (!pi || pi->sih->buscoretype != PCIE_CORE_ID)
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return;
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pcie_clkreq_upd(pi, state);
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@ -58,18 +58,6 @@
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/* bar0 + 12K accesses chipc core registers */
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#define PCI_16KB0_CCREGS_OFFSET (12 * 1024)
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#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */
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/* Sonics to PCI translation types */
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#define SBTOPCI_PREF 0x4 /* prefetch enable */
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#define SBTOPCI_BURST 0x8 /* burst enable */
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#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
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/* PCI core index in SROM shadow area */
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#define SRSH_PI_OFFSET 0 /* first word */
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#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
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#define SRSH_PI_SHIFT 12 /* bit 15:12 */
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struct sbpciregs;
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struct sbpcieregs;
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