ARCv2: MMUv4: TLB programming Model changes
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -267,6 +267,7 @@ choice
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prompt "MMU Version"
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default ARC_MMU_V3 if ARC_CPU_770
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default ARC_MMU_V2 if ARC_CPU_750D
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default ARC_MMU_V4 if ARC_CPU_HS
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config ARC_MMU_V1
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bool "MMU v1"
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@ -287,6 +288,10 @@ config ARC_MMU_V3
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Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
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Shared Address Spaces (SASID)
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config ARC_MMU_V4
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bool "MMU v4"
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depends on ISA_ARCV2
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endchoice
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@ -326,7 +326,7 @@ struct bcr_generic {
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*/
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struct cpuinfo_arc_mmu {
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unsigned int ver:4, pg_sz_k:8, pad:8, u_dtlb:6, u_itlb:6;
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unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, u_dtlb:6, u_itlb:6;
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unsigned int num_tlb:16, sets:12, ways:4;
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};
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@ -15,24 +15,41 @@
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#elif defined(CONFIG_ARC_MMU_V4)
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#define CONFIG_ARC_MMU_VER 4
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#endif
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/* MMU Management regs */
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#define ARC_REG_MMU_BCR 0x06f
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#if (CONFIG_ARC_MMU_VER < 4)
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#define ARC_REG_TLBPD0 0x405
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#define ARC_REG_TLBPD1 0x406
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#define ARC_REG_TLBINDEX 0x407
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#define ARC_REG_TLBCOMMAND 0x408
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#define ARC_REG_PID 0x409
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#define ARC_REG_SCRATCH_DATA0 0x418
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#else
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#define ARC_REG_TLBPD0 0x460
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#define ARC_REG_TLBPD1 0x461
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#define ARC_REG_TLBINDEX 0x464
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#define ARC_REG_TLBCOMMAND 0x465
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#define ARC_REG_PID 0x468
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#define ARC_REG_SCRATCH_DATA0 0x46c
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#endif
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/* Bits in MMU PID register */
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#define MMU_ENABLE (1 << 31) /* Enable MMU for process */
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#define __TLB_ENABLE (1 << 31)
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#define __PROG_ENABLE (1 << 30)
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#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
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/* Error code if probe fails */
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#define TLB_LKUP_ERR 0x80000000
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#if (CONFIG_ARC_MMU_VER < 4)
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#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001)
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#else
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#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000)
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#endif
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/* TLB Commands */
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#define TLBWrite 0x1
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@ -45,6 +62,11 @@
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#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
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#endif
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#if (CONFIG_ARC_MMU_VER >= 4)
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#define TLBInsertEntry 0x7
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#define TLBDeleteEntry 0x8
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#endif
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#ifndef __ASSEMBLY__
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typedef struct {
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@ -72,8 +72,18 @@
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#define _PAGE_READ (1<<3) /* Page has user read perm (H) */
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#define _PAGE_ACCESSED (1<<4) /* Page is accessed (S) */
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#define _PAGE_MODIFIED (1<<5) /* Page modified (dirty) (S) */
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#if (CONFIG_ARC_MMU_VER >= 4)
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#define _PAGE_WTHRU (1<<7) /* Page cache mode write-thru (H) */
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#endif
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#define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
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#define _PAGE_PRESENT (1<<9) /* TLB entry is valid (H) */
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#if (CONFIG_ARC_MMU_VER >= 4)
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#define _PAGE_SZ (1<<10) /* Page Size indicator (H) */
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#endif
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#define _PAGE_SHARED_CODE (1<<11) /* Shared Code page with cmn vaddr
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usable for shared TLB entries (H) */
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#endif
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@ -113,6 +113,8 @@ static inline void __tlb_entry_erase(void)
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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#if (CONFIG_ARC_MMU_VER < 4)
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static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
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{
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unsigned int idx;
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@ -210,6 +212,28 @@ static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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#else /* CONFIG_ARC_MMU_VER >= 4) */
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static void utlb_invalidate(void)
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{
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/* No need since uTLB is always in sync with JTLB */
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}
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static void tlb_entry_erase(unsigned int vaddr_n_asid)
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{
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write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
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}
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static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
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{
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write_aux_reg(ARC_REG_TLBPD0, pd0);
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write_aux_reg(ARC_REG_TLBPD1, pd1);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
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}
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#endif
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/*
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* Un-conditionally (without lookup) erase the entire MMU contents
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*/
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@ -582,6 +606,17 @@ void read_decode_mmu_bcr(void)
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#endif
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} *mmu3;
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struct bcr_mmu_4 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
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n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
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#else
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/* DTLB ITLB JES JE JA */
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unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
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pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
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#endif
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} *mmu4;
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tmp = read_aux_reg(ARC_REG_MMU_BCR);
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mmu->ver = (tmp >> 24);
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@ -592,13 +627,21 @@ void read_decode_mmu_bcr(void)
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mmu->ways = 1 << mmu2->ways;
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mmu->u_dtlb = mmu2->u_dtlb;
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mmu->u_itlb = mmu2->u_itlb;
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} else {
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} else if (mmu->ver == 3) {
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mmu3 = (struct bcr_mmu_3 *)&tmp;
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mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
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mmu->sets = 1 << mmu3->sets;
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mmu->ways = 1 << mmu3->ways;
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mmu->u_dtlb = mmu3->u_dtlb;
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mmu->u_itlb = mmu3->u_itlb;
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} else {
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mmu4 = (struct bcr_mmu_4 *)&tmp;
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mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
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mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
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mmu->sets = 64 << mmu4->n_entry;
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mmu->ways = mmu4->n_ways * 2;
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mmu->u_dtlb = mmu4->u_dtlb * 4;
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mmu->u_itlb = mmu4->u_itlb * 4;
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}
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mmu->num_tlb = mmu->sets * mmu->ways;
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@ -608,10 +651,15 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
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{
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int n = 0;
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struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
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char super_pg[64] = "";
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if (p_mmu->s_pg_sz_m)
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scnprintf(super_pg, 64, "%dM Super Page%s, ",
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p_mmu->s_pg_sz_m, " (not used)");
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n += scnprintf(buf + n, len - n,
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"MMU [v%x]\t: %dk PAGE, JTLB %d (%dx%d), uDTLB %d, uITLB %d %s\n",
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p_mmu->ver, p_mmu->pg_sz_k,
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"MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d %s\n",
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p_mmu->ver, p_mmu->pg_sz_k, super_pg,
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p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
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p_mmu->u_dtlb, p_mmu->u_itlb,
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IS_ENABLED(CONFIG_ARC_MMU_SASID) ? ",SASID" : "");
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@ -44,6 +44,7 @@
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#include <asm/processor.h>
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#include <asm/tlb-mmu1.h>
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#ifdef CONFIG_ISA_ARCOMPACT
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;-----------------------------------------------------------------
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; ARC700 Exception Handling doesn't auto-switch stack and it only provides
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; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
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#endif
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.endm
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#else /* ARCv2 */
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.macro TLBMISS_FREEUP_REGS
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PUSH r0
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PUSH r1
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PUSH r2
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PUSH r3
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.endm
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.macro TLBMISS_RESTORE_REGS
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POP r3
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POP r2
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POP r1
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POP r0
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.endm
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#endif
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;============================================================================
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; Troubleshooting Stuff
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;============================================================================
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; Commit the TLB entry into MMU
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.macro COMMIT_ENTRY_TO_MMU
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#if (CONFIG_ARC_MMU_VER < 4)
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/* Get free TLB slot: Set = computed from vaddr, way = random */
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sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
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#else
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sr TLBWrite, [ARC_REG_TLBCOMMAND]
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#endif
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#else
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sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
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#endif
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.endm
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