Merge tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull some non-critical i.MX clk fixes from Shawn Guo:
* Fix the commit 3713e3f5e9
("clk: imx35: define two clocks for rtc")
which messed up the clock enumeration when adding new clock.
* tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx35: restore existing used clock enumeration
clk: imx6q: fix typo in CAN clock definition
This commit is contained in:
commit
d8609a3a2e
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@ -94,6 +94,7 @@ clocks and IDs.
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csi_sel 79
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iim_gate 80
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gpu2d_gate 81
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ckli_gate 82
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Examples:
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@ -66,7 +66,7 @@ static const char *std_sel[] = {"ppll", "arm"};
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static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
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enum mx35_clks {
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ckih, ckil, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
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ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
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arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
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esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
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spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
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@ -79,7 +79,7 @@ enum mx35_clks {
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rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
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ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
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wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
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gpu2d_gate, clk_max
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gpu2d_gate, ckil, clk_max
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};
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static struct clk *clk[clk_max];
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@ -394,7 +394,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
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} else {
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clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
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clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60", base + 0x20, 2, 6);
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clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
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clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
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clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
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clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
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