[MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
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" addu %1, %0, 1 \n"
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" sc %1, %2 \n"
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" beqz %1, 1b \n"
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" sync \n"
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__WEAK_LLSC_MB
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: "=&r" (result), "=&r" (temp), "=m" (*pv)
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: "m" (*pv)
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: "memory");
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