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[ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK 

All current Simtec designs source the DCLK outputs from
the UPLL. This means the DCLK's parent must be set to UPLL
so that anything enabling and disabling an UPLL sourced
clock does not shutdown the DCLK due to missing open counts.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks 2008-04-16 00:12:39 +01:00 committed by Russell King
parent 1017be88d3
commit d96a980441
4 changed files with 8 additions and 7 deletions
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4
arch/arm/mach-s3c2410/mach-bast.c
View File

@ -592,10 +592,10 @@ static void __init bast_map_io(void)
{
/* initialise the clocks */
s3c24xx_dclk0.parent = NULL;
s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
s3c24xx_dclk1.parent = NULL;
s3c24xx_dclk1.parent = &clk_upll;
s3c24xx_dclk1.rate = 24*1000*1000;
s3c24xx_clkout0.parent = &s3c24xx_dclk0;

2
arch/arm/mach-s3c2410/mach-vr1000.c
View File

@ -393,7 +393,7 @@ static void __init vr1000_map_io(void)
{
/* initialise clock sources */
s3c24xx_dclk0.parent = NULL;
s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
s3c24xx_dclk1.parent = NULL;

4
arch/arm/mach-s3c2440/mach-anubis.c
View File

@ -413,10 +413,10 @@ static void __init anubis_map_io(void)
{
/* initialise the clocks */
s3c24xx_dclk0.parent = NULL;
s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
s3c24xx_dclk1.parent = NULL;
s3c24xx_dclk1.parent = &clk_upll;
s3c24xx_dclk1.rate = 24*1000*1000;
s3c24xx_clkout0.parent = &s3c24xx_dclk0;

5
arch/arm/mach-s3c2440/mach-osiris.c
View File

@ -18,6 +18,7 @@
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/clk.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -344,10 +345,10 @@ static void __init osiris_map_io(void)
/* initialise the clocks */
s3c24xx_dclk0.parent = NULL;
s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
s3c24xx_dclk1.parent = NULL;
s3c24xx_dclk1.parent = &clk_upll;
s3c24xx_dclk1.rate = 24*1000*1000;
s3c24xx_clkout0.parent = &s3c24xx_dclk0;