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xtensa: xtfpga: fix ethernet controller endianness 

Ethernet controller is attached to XTFPGA boards as native endian device,
mark it as such in DTS and pass correct endianness in platform data.
This makes network functional on big-endian CPUs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2015-08-25 09:04:12 +03:00 committed by Chris Zankel
parent abfbd89595
commit d99434e176
2 changed files with 2 additions and 0 deletions
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1
arch/xtensa/boot/dts/xtfpga.dtsi
View File

@ -69,6 +69,7 @@
enet0: ethoc@0d030000 {
compatible = "opencores,ethoc";
reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
native-endian;
interrupts = <1 1>; /* external irq 1 */
local-mac-address = [00 50 c2 13 6f 00];
clocks = <&osc>;

1
arch/xtensa/platforms/xtfpga/setup.c
View File

@ -223,6 +223,7 @@ static struct ethoc_platform_data ethoc_pdata = {
*/
.hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
.phy_id = -1,
.big_endian = XCHAL_HAVE_BE,
};
static struct platform_device ethoc_device = {