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tmio_mmc: fix clock setup 

This patch fixes the clock setup in tmio_mmc.

  * Incorrect divider setting
  * Cruft written to the clock registers (seemingly harmless but Not
Good (tm))

It also eliminates some unnecessary ifs and tidies the loop syntax.

Thanks to Philipp Zabel who discovered the divider issue, commenting

   "Except for the SDCLK = HCLK (divider bypassed) case, the clock
    setting resulted in double the requested frequency.
    The smallest possible frequency (f_max/512) is configured with
    a divider setting 0x80, not 0x40."

Signed-off-by: Ian Molton <ian@mnementh.co.uk>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
This commit is contained in:
Ian Molton 2009-06-12 21:53:05 +01:00 committed by Pierre Ossman
parent 544f277bb8
commit da46a0bd42
1 changed files with 5 additions and 10 deletions
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15
drivers/mmc/host/tmio_mmc.c
View File

@ -37,22 +37,17 @@
static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
{
u32 clk = 0, clock, f_min = host->mmc->f_min;
u32 clk = 0, clock;
if (new_clock) {
for (clock = f_min, clk = 0x100; new_clock >= (clock<<1); ) {
for (clock = host->mmc->f_min, clk = 0x80000080;
new_clock >= (clock<<1); clk >>= 1)
clock <<= 1;
clk >>= 1;
}
if (clk & 0x1)
clk = 0x20000;
clk >>= 2;
sd_config_write8(host, CNF_SD_CLK_MODE, (clk & 0x8000) ? 0 : 1);
clk |= 0x100;
}
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk);
sd_config_write8(host, CNF_SD_CLK_MODE, clk >> 22);
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
}
static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)