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drm/nouveau/fifo/gk104: fix engine status register offset 

The offset should be 8 on Kepler and later.

Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Vince Hsu 2015-11-16 15:38:30 +08:00 committed by Ben Skeggs
parent 864d55f407
commit da4ee13cd5
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
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@ -196,7 +196,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
spin_lock_irqsave(&fifo->base.lock, flags);
for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) {
u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));
u32 busy = (stat & 0x80000000);
u32 next = (stat & 0x07ff0000) >> 16;
u32 chsw = (stat & 0x00008000);