MIPS fixes for 4.14
A selection of important MIPS fixes for 4.14, and some MAINTAINERS / email address updates: - Update imgtec.com -> mips.com email addresses (this trivially updates comments in quite a few files, as well as MAINTAINERS) - Update Pistachio SoC maintainership - Fix NI 169445 build (new platform in 4.14) - Fix EVA regression (4.14) - Fix SMP-CPS build & preemption regressions (4.14) - Fix SMP/hotplug deadlock & race (deadlock reintroduced 4.13) - Fix ebpf_jit error return (4.13) - Fix SMP-CMP build regressions (4.11 and 4.14) - Fix bad UASM microMIPS encoding (3.16) - Fix CM definitions (3.15) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEd80NauSabkiESfLYbAtpk944dnoFAln8oQ0ACgkQbAtpk944 dnoYohAAlw4Ui09K7fgpwGcmquwoo5h4FYRE2dkd3RvITl73m7GI+3rML6RzxINV o5DG6WWJWWROKBVkfXMkJ+lksoSSMfBlSSE+MdvWdWUbWm+Oh15rXOtzZSbNTqWG Y+pghJq2XGpOBe8Bp4EVDJjPnsQMLYK+tmw/jWxtCYLzp+j4I40WHnNPgtT/Tci8 NzAn7J9jTft3rWd4/dqQFhAnZrNAv/Udx2QGNPPRfe1TOrMVP/2T5gSLW+yjuOA6 NG10DennLfTjtpGFlCeF/pGHXqRJ629AzOq5nKJthGjc/QPk6T+vnSpH/wcgZra/ sw4bAqEo769x6KHgJzTqvES2j6rTAqJYeqxc2/GaH9HGcTzvqDCwynUr860BIv+7 MCiLhyf73ivZNqh5ntJfXCXkKex0oDDFu9eze1wZ76qJYlyEKPx6cSCvvUIWBOU5 7/jzQ3wIiHcPIp48uqZ5c6vxuY0ppbD5feilMDuXcNTDVGOJIFr43agB94Ynr+yM KnKlgosrRsvTHvcTYRsgG3qC/0pllRmlsNKKUrwtlu2gfIIvpWBFAJWR3pqHiZB6 UYu0AIHg0ctMOCLoOAT9jD0iUS3sCzqdvFufTrLwak0UZgw/nvFAYNWZqN0ZRmpB 6NR6U6o2r8ld6cGfzSi8BQtIZvxqwNl0qlVUVBcxUeR8OUUkBJA= =nqbK -----END PGP SIGNATURE----- Merge tag 'mips_fixes_4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips Pull MIPS fixes from James Hogan: "A selection of important MIPS fixes for 4.14, and some MAINTAINERS / email address updates: Maintainership updates: - imgtec.com -> mips.com email addresses (this trivially updates comments in quite a few files, as well as MAINTAINERS) - Pistachio SoC maintainership update Fixes: - NI 169445 build (new platform in 4.14) - EVA regression (4.14) - SMP-CPS build & preemption regressions (4.14) - SMP/hotplug deadlock & race (deadlock reintroduced 4.13) - ebpf_jit error return (4.13) - SMP-CMP build regressions (4.11 and 4.14) - bad UASM microMIPS encoding (3.16) - CM definitions (3.15)" [ I had taken the email address updates separately, because I didn't expect James to send a pull request, so those got applied twice. - Linus] * tag 'mips_fixes_4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: MIPS: Update email address for Marcin Nowakowski MIPS: smp-cmp: Fix vpe_id build error MAINTAINERS: Update Pistachio platform maintainers MIPS: smp-cmp: Use right include for task_struct MIPS: Update Goldfish RTC driver maintainer email address MIPS: Update RINT emulation maintainer email address MIPS: CPS: Fix use of current_cpu_data in preemptible code MIPS: SMP: Fix deadlock & online race MIPS: bpf: Fix a typo in build_one_insn() MIPS: microMIPS: Fix incorrect mask in insn_table_MM MIPS: Fix CM region target definitions MIPS: generic: Fix compilation error from include asm/mips-cpc.h MIPS: Fix exception entry when CONFIG_EVA enabled MIPS: generic: Fix NI 169445 its build Update MIPS email addresses
This commit is contained in:
commit
dab30d5531
3
.mailmap
3
.mailmap
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@ -15,6 +15,7 @@ Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>
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Alan Cox <alan@lxorguk.ukuu.org.uk>
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Alan Cox <root@hraefn.swansea.linux.org.uk>
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Aleksey Gorelov <aleksey_gorelov@phoenix.com>
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Aleksandar Markovic <aleksandar.markovic@mips.com> <aleksandar.markovic@imgtec.com>
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Al Viro <viro@ftp.linux.org.uk>
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Al Viro <viro@zenIV.linux.org.uk>
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Andreas Herrmann <aherrman@de.ibm.com>
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@ -101,6 +102,7 @@ Leonid I Ananiev <leonid.i.ananiev@intel.com>
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Linas Vepstas <linas@austin.ibm.com>
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Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
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Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
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Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>
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Mark Brown <broonie@sirena.org.uk>
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Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
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Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
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@ -119,6 +121,7 @@ Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
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Mayuresh Janorkar <mayur@ti.com>
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Michael Buesch <m@bues.ch>
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Michel Dänzer <michel@tungstengraphics.com>
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Miodrag Dinic <miodrag.dinic@mips.com> <miodrag.dinic@imgtec.com>
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Mitesh shah <mshah@teja.com>
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Mohit Kumar <mohit.kumar@st.com> <mohit.kumar.dhaka@gmail.com>
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Morten Welinder <terra@gnome.org>
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@ -873,7 +873,7 @@ F: drivers/android/
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F: drivers/staging/android/
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ANDROID GOLDFISH RTC DRIVER
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M: Miodrag Dinic <miodrag.dinic@imgtec.com>
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M: Miodrag Dinic <miodrag.dinic@mips.com>
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S: Supported
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F: Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
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F: drivers/rtc/rtc-goldfish.c
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@ -9019,7 +9019,7 @@ F: drivers/*/*loongson1*
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F: drivers/*/*/*loongson1*
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MIPS RINT INSTRUCTION EMULATION
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M: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
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M: Aleksandar Markovic <aleksandar.markovic@mips.com>
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L: linux-mips@linux-mips.org
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S: Supported
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F: arch/mips/math-emu/sp_rint.c
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@ -10683,10 +10683,9 @@ S: Maintained
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F: drivers/pinctrl/spear/
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PISTACHIO SOC SUPPORT
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M: James Hartley <james.hartley@imgtec.com>
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M: Ionela Voinescu <ionela.voinescu@imgtec.com>
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M: James Hartley <james.hartley@sondrel.com>
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L: linux-mips@linux-mips.org
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S: Maintained
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S: Odd Fixes
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F: arch/mips/pistachio/
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F: arch/mips/include/asm/mach-pistachio/
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F: arch/mips/boot/dts/img/pistachio*
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@ -1,4 +1,4 @@
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{
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/ {
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images {
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fdt@ni169445 {
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description = "NI 169445 device tree";
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@ -20,7 +20,7 @@
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#include <asm/fw/fw.h>
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#include <asm/irq_cpu.h>
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#include <asm/machine.h>
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#include <asm/mips-cpc.h>
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#include <asm/mips-cps.h>
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#include <asm/prom.h>
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#include <asm/smp-ops.h>
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#include <asm/time.h>
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 2016 Imagination Technologies
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* Author: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
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* Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -142,8 +142,8 @@ GCR_ACCESSOR_RO(64, 0x000, config)
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GCR_ACCESSOR_RW(64, 0x008, base)
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#define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)
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#define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
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#define CM_GCR_BASE_CMDEFTGT_DISABLED 0
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#define CM_GCR_BASE_CMDEFTGT_MEM 1
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#define CM_GCR_BASE_CMDEFTGT_MEM 0
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#define CM_GCR_BASE_CMDEFTGT_RESERVED 1
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#define CM_GCR_BASE_CMDEFTGT_IOCU0 2
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#define CM_GCR_BASE_CMDEFTGT_IOCU1 3
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@ -199,6 +199,10 @@
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sll k0, 3 /* extract cu0 bit */
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.set noreorder
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bltz k0, 8f
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move k0, sp
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.if \docfi
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.cfi_register sp, k0
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.endif
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#ifdef CONFIG_EVA
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/*
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* Flush interAptiv's Return Prediction Stack (RPS) by writing
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@ -225,10 +229,6 @@
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MTC0 k0, CP0_ENTRYHI
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#endif
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.set reorder
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move k0, sp
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.if \docfi
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.cfi_register sp, k0
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.endif
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/* Called from user mode, new stack. */
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get_saved_sp docfi=\docfi tosp=1
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8:
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) 2016 Imagination Technologies
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* Author: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
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* Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -19,7 +19,7 @@
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/sched/task_stack.h>
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#include <linux/smp.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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@ -50,8 +50,8 @@ static void cmp_init_secondary(void)
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#ifdef CONFIG_MIPS_MT_SMP
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if (cpu_has_mipsmt)
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c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
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TCBIND_CURVPE;
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cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
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TCBIND_CURVPE);
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#endif
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}
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@ -306,7 +306,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
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int err;
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/* We don't yet support booting CPUs in other clusters */
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if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(¤t_cpu_data))
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if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
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return -ENOSYS;
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vpe_cfg->pc = (unsigned long)&smp_bootstrap;
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@ -42,7 +42,7 @@
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#include <asm/processor.h>
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#include <asm/idle.h>
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#include <asm/r4k-timer.h>
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#include <asm/mips-cpc.h>
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#include <asm/mips-cps.h>
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#include <asm/mmu_context.h>
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#include <asm/time.h>
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#include <asm/setup.h>
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@ -66,6 +66,7 @@ EXPORT_SYMBOL(cpu_sibling_map);
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cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_core_map);
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static DECLARE_COMPLETION(cpu_starting);
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static DECLARE_COMPLETION(cpu_running);
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/*
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cpumask_set_cpu(cpu, &cpu_coherent_mask);
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notify_cpu_starting(cpu);
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/* Notify boot CPU that we're starting & ready to sync counters */
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complete(&cpu_starting);
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synchronise_count_slave(cpu);
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/* The CPU is running and counters synchronised, now mark it online */
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set_cpu_online(cpu, true);
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set_cpu_sibling_map(cpu);
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calculate_cpu_foreign_map();
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/*
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* Notify boot CPU that we're up & online and it can safely return
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* from __cpu_up
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*/
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complete(&cpu_running);
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synchronise_count_slave(cpu);
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/*
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* irq will be enabled in ->smp_finish(), enabling it too early
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if (err)
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return err;
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/*
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* We must check for timeout here, as the CPU will not be marked
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* online until the counters are synchronised.
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*/
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if (!wait_for_completion_timeout(&cpu_running,
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/* Wait for CPU to start and be ready to sync counters */
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if (!wait_for_completion_timeout(&cpu_starting,
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msecs_to_jiffies(1000))) {
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pr_crit("CPU%u: failed to start\n", cpu);
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return -EIO;
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}
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synchronise_count_master(cpu);
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/* Wait for CPU to finish startup & mark itself online before return */
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wait_for_completion(&cpu_running);
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return 0;
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}
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[insn_jr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},
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[insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
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[insn_ld] = {0, 0},
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[insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM},
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[insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
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[insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
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[insn_lld] = {0, 0},
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[insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},
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}
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src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
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if (src < 0)
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return dst;
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return src;
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if (BPF_MODE(insn->code) == BPF_XADD) {
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switch (BPF_SIZE(insn->code)) {
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case BPF_W:
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