arm64: Add APM X-Gene SoC AHCI SATA host controller DTS entries
This patch adds APM X-Gene SoC AHCI SATA host controller DTS entries. Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Tuan Phan <tphan@apm.com> Signed-off-by: Suman Tripathi <stripathi@apm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Tejun Heo <tj@kernel.org>
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@ -218,6 +218,45 @@
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enable-offset = <0x0>;
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enable-mask = <0x06>;
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};
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sata01clk: sata01clk@1f21c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f21c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sata01clk";
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csr-offset = <0x4>;
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csr-mask = <0x05>;
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enable-offset = <0x0>;
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enable-mask = <0x39>;
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};
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sata23clk: sata23clk@1f22c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f22c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sata23clk";
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csr-offset = <0x4>;
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csr-mask = <0x05>;
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enable-offset = <0x0>;
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enable-mask = <0x39>;
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};
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sata45clk: sata45clk@1f23c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f23c000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "sata45clk";
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csr-offset = <0x4>;
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csr-mask = <0x05>;
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enable-offset = <0x0>;
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enable-mask = <0x39>;
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};
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};
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serial0: serial@1c020000 {
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@ -259,5 +298,46 @@
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apm,tx-boost-gain = <31 31 31 31 31 31>;
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apm,tx-eye-tuning = <2 10 10 2 10 10>;
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};
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sata1: sata@1a000000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a000000 0x0 0x1000>,
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<0x0 0x1f210000 0x0 0x1000>,
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<0x0 0x1f21d000 0x0 0x1000>,
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<0x0 0x1f21e000 0x0 0x1000>,
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<0x0 0x1f217000 0x0 0x1000>;
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interrupts = <0x0 0x86 0x4>;
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status = "disabled";
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clocks = <&sata01clk 0>;
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phys = <&phy1 0>;
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phy-names = "sata-phy";
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};
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sata2: sata@1a400000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a400000 0x0 0x1000>,
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<0x0 0x1f220000 0x0 0x1000>,
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<0x0 0x1f22d000 0x0 0x1000>,
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<0x0 0x1f22e000 0x0 0x1000>,
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<0x0 0x1f227000 0x0 0x1000>;
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interrupts = <0x0 0x87 0x4>;
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status = "ok";
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clocks = <&sata23clk 0>;
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phys = <&phy2 0>;
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phy-names = "sata-phy";
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};
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sata3: sata@1a800000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a800000 0x0 0x1000>,
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<0x0 0x1f230000 0x0 0x1000>,
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<0x0 0x1f23d000 0x0 0x1000>,
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<0x0 0x1f23e000 0x0 0x1000>;
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interrupts = <0x0 0x88 0x4>;
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status = "ok";
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clocks = <&sata45clk 0>;
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phys = <&phy3 0>;
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phy-names = "sata-phy";
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};
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};
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};
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