spi: dw-spi: Convert 16bit accesses to 32bit accesses
Altera's Arria10 SoC interconnect requires a 32-bit write for APB peripherals. The current spi-dw driver uses 16-bit accesses in some locations. This patch converts all the 16-bit reads and writes to 32-bit reads and writes. Additional Documentation to Support this Change: The DW_apb_ssi databook states: "All registers in the DW_apb_ssi are addressed at 32-bit boundaries to remain consistent with the AHB bus. Where the physical size of any register is less than 32-bits wide, the upper unused bits of the 32-bit boundary are reserved. Writing to these bits has no effect; reading from these bits returns 0." [1] [1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a) Request for test with platforms using the DesignWare SPI IP. Tested On: Altera CycloneV development kit Altera Arria10 development kit Compile tested for build errors on x86_64 (allyesconfigs) Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Reviewed-and-tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -98,12 +98,12 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
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static irqreturn_t dma_transfer(struct dw_spi *dws)
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{
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u16 irq_status = dw_readw(dws, DW_SPI_ISR);
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u16 irq_status = dw_readl(dws, DW_SPI_ISR);
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if (!irq_status)
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return IRQ_NONE;
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dw_readw(dws, DW_SPI_ICR);
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dw_readl(dws, DW_SPI_ICR);
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spi_reset_chip(dws);
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dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
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@ -228,14 +228,14 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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u16 dma_ctrl = 0;
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dw_writew(dws, DW_SPI_DMARDLR, 0xf);
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dw_writew(dws, DW_SPI_DMATDLR, 0x10);
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dw_writel(dws, DW_SPI_DMARDLR, 0xf);
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dw_writel(dws, DW_SPI_DMATDLR, 0x10);
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if (xfer->tx_buf)
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dma_ctrl |= SPI_DMA_TDMAE;
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if (xfer->rx_buf)
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dma_ctrl |= SPI_DMA_RDMAE;
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dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
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dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
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/* Set the interrupt mask */
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spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);
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@ -157,7 +157,7 @@ static inline u32 tx_max(struct dw_spi *dws)
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u32 tx_left, tx_room, rxtx_gap;
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tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
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tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
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tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
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/*
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* Another concern is about the tx/rx mismatch, we
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@ -178,7 +178,7 @@ static inline u32 rx_max(struct dw_spi *dws)
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{
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u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
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return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR));
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return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
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}
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static void dw_writer(struct dw_spi *dws)
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@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws)
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else
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txw = *(u16 *)(dws->tx);
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}
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dw_writew(dws, DW_SPI_DR, txw);
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dw_writel(dws, DW_SPI_DR, txw);
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dws->tx += dws->n_bytes;
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}
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}
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@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws)
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u16 rxw;
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while (max--) {
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rxw = dw_readw(dws, DW_SPI_DR);
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rxw = dw_readl(dws, DW_SPI_DR);
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/* Care rx only if the transfer's original "rx" is not null */
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if (dws->rx_end - dws->len) {
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if (dws->n_bytes == 1)
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@ -228,11 +228,11 @@ static void int_error_stop(struct dw_spi *dws, const char *msg)
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static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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{
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u16 irq_status = dw_readw(dws, DW_SPI_ISR);
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u16 irq_status = dw_readl(dws, DW_SPI_ISR);
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/* Error handling */
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if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
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dw_readw(dws, DW_SPI_ICR);
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dw_readl(dws, DW_SPI_ICR);
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int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
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return IRQ_HANDLED;
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}
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@ -257,7 +257,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct dw_spi *dws = spi_master_get_devdata(master);
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u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
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u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
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if (!irq_status)
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return IRQ_NONE;
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@ -354,7 +354,7 @@ static int dw_spi_transfer_one(struct spi_master *master,
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cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
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}
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dw_writew(dws, DW_SPI_CTRL0, cr0);
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dw_writel(dws, DW_SPI_CTRL0, cr0);
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/* Check if current transfer is a DMA transaction */
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if (master->can_dma && master->can_dma(master, spi, transfer))
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@ -375,7 +375,7 @@ static int dw_spi_transfer_one(struct spi_master *master,
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}
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} else if (!chip->poll_mode) {
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txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
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dw_writew(dws, DW_SPI_TXFLTR, txlevel);
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dw_writel(dws, DW_SPI_TXFLTR, txlevel);
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/* Set the interrupt mask */
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imask |= SPI_INT_TXEI | SPI_INT_TXOI |
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@ -499,11 +499,11 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws)
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u32 fifo;
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for (fifo = 1; fifo < 256; fifo++) {
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dw_writew(dws, DW_SPI_TXFLTR, fifo);
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if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
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dw_writel(dws, DW_SPI_TXFLTR, fifo);
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if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
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break;
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}
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dw_writew(dws, DW_SPI_TXFLTR, 0);
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dw_writel(dws, DW_SPI_TXFLTR, 0);
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dws->fifo_len = (fifo == 1) ? 0 : fifo;
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dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
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@ -150,16 +150,6 @@ static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
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__raw_writel(val, dws->regs + offset);
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}
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static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
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{
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return __raw_readw(dws->regs + offset);
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}
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static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
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{
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__raw_writew(val, dws->regs + offset);
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}
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static inline void spi_enable_chip(struct dw_spi *dws, int enable)
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{
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dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
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