Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer fixes from Thomas Gleixner:
 "A rather small update for the time(r) subsystem:

   - A new clocksource driver IMX-TPM

   - Minor fixes to the alarmtimer facility

   - Device tree cleanups for Renesas drivers

   - A new kselftest and fixes for the timer related tests

   - Conversion of the clocksource drivers to use %pOF

   - Use the proper helpers to access rlimits in the posix-cpu-timer
     code"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  alarmtimer: Ensure RTC module is not unloaded
  clocksource: Convert to using %pOF instead of full_name
  clocksource/drivers/bcm2835: Remove message for a memory allocation failure
  devicetree: bindings: Remove deprecated properties
  devicetree: bindings: Remove unused 32-bit CMT bindings
  devicetree: bindings: Deprecate property, update example
  devicetree: bindings: r8a73a4 and R-Car Gen2 CMT bindings
  devicetree: bindings: R-Car Gen2 CMT0 and CMT1 bindings
  devicetree: bindings: Remove sh7372 CMT binding
  clocksource/drivers/imx-tpm: Add imx tpm timer support
  dt-bindings: timer: Add nxp tpm timer binding doc
  posix-cpu-timers: Use dedicated helper to access rlimit values
  alarmtimer: Fix unavailable wake-up source in sysfs
  timekeeping: Use proper timekeeper for debug code
  kselftests: timers: set-timer-lat: Add one-shot timer test cases
  kselftests: timers: set-timer-lat: Tweak reporting when timer fires early
  kselftests: timers: freq-step: Fix build warning
  kselftests: timers: freq-step: Define ADJ_SETOFFSET if device has older kernel headers
This commit is contained in:
Linus Torvalds 2017-09-04 13:06:34 -07:00
commit dd90cccffc
15 changed files with 440 additions and 84 deletions

View File

@ -0,0 +1,28 @@
NXP Low Power Timer/Pulse Width Modulation Module (TPM)
The Timer/PWM Module (TPM) supports input capture, output compare,
and the generation of PWM signals to control electric motor and power
management applications. The counter, compare and capture registers
are clocked by an asynchronous clock that can remain enabled in low
power modes. TPM can support global counter bus where one TPM drives
the counter bus for the others, provided bit width is the same.
Required properties:
- compatible : should be "fsl,imx7ulp-tpm"
- reg : Specifies base physical address and size of the register sets
for the clock event device and clock source device.
- interrupts : Should be the clock event device interrupt.
- clocks : The clocks provided by the SoC to drive the timer, must contain
an entry for each entry in clock-names.
- clock-names : Must include the following entries: "igp" and "per".
Example:
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
<&clks IMX7ULP_CLK_LPTPM5>;
clock-names = "ipg", "per";
};

View File

@ -12,46 +12,29 @@ datasheets.
Required Properties:
- compatible: must contain one or more of the following:
- "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT
(CMT0)
- "renesas,cmt-32-sh7372" for the sh7372 32-bit CMT
(CMT0)
- "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT
(CMT0)
- "renesas,cmt-32" for all 32-bit CMT without fast clock support
(CMT0 on sh7372, sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-32-* entries.
- "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast
clock support (CMT[234])
- "renesas,cmt-32-fast-sh7372" for the sh7372 32-bit CMT with fast
clock support (CMT[234])
- "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast
clock support (CMT[234])
- "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support
(CMT[234] on sh7372, sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-32-fast-* entries.
- "renesas,cmt-48-sh7372" for the sh7372 48-bit CMT
(CMT1)
- "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
(CMT1)
- "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
(CMT1)
- "renesas,cmt-48" for all non-second generation 48-bit CMT
(CMT1 on sh7372, sh73a0 and r8a7740)
(CMT1 on sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-48-* entries.
- "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT
(CMT[01])
- "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT
(CMT[01])
- "renesas,cmt-48-r8a7791" for the r8a7791 48-bit CMT
(CMT[01])
- "renesas,cmt-48-gen2" for all second generation 48-bit CMT
(CMT[01] on r8a73a4, r8a7790 and r8a7791)
This is a fallback for the renesas,cmt-48-r8a73a4,
renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries.
- "renesas,cmt0-r8a73a4" for the 32-bit CMT0 device included in r8a73a4.
- "renesas,cmt1-r8a73a4" for the 48-bit CMT1 device included in r8a73a4.
- "renesas,cmt0-r8a7790" for the 32-bit CMT0 device included in r8a7790.
- "renesas,cmt1-r8a7790" for the 48-bit CMT1 device included in r8a7790.
- "renesas,cmt0-r8a7791" for the 32-bit CMT0 device included in r8a7791.
- "renesas,cmt1-r8a7791" for the 48-bit CMT1 device included in r8a7791.
- "renesas,cmt0-r8a7793" for the 32-bit CMT0 device included in r8a7793.
- "renesas,cmt1-r8a7793" for the 48-bit CMT1 device included in r8a7793.
- "renesas,cmt0-r8a7794" for the 32-bit CMT0 device included in r8a7794.
- "renesas,cmt1-r8a7794" for the 48-bit CMT1 device included in r8a7794.
- "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2.
- "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2.
These are fallbacks for r8a73a4 and all the R-Car Gen2
entries listed above.
- reg: base address and length of the registers block for the timer module.
- interrupts: interrupt-specifier for the timer, one per channel.
@ -59,21 +42,29 @@ Required Properties:
in clock-names.
- clock-names: must contain "fck" for the functional clock.
- renesas,channels-mask: bitmask of the available channels.
Example: R8A7790 (R-Car H2) CMT0 node
CMT0 on R8A7790 implements hardware channels 5 and 6 only and names
them channels 0 and 1 in the documentation.
Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes
cmt0: timer@ffca0000 {
compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
compatible = "renesas,cmt0-r8a7790", "renesas,rcar-gen2-cmt0";
reg = <0 0xffca0000 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
<0 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
renesas,channels-mask = <0x60>;
};
cmt1: timer@e6130000 {
compatible = "renesas,cmt1-r8a7790", "renesas,rcar-gen2-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
<0 121 IRQ_TYPE_LEVEL_HIGH>,
<0 122 IRQ_TYPE_LEVEL_HIGH>,
<0 123 IRQ_TYPE_LEVEL_HIGH>,
<0 124 IRQ_TYPE_LEVEL_HIGH>,
<0 125 IRQ_TYPE_LEVEL_HIGH>,
<0 126 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
clock-names = "fck";
};

View File

@ -598,6 +598,14 @@ config CLKSRC_IMX_GPT
depends on ARM && CLKDEV_LOOKUP
select CLKSRC_MMIO
config CLKSRC_IMX_TPM
bool "Clocksource using i.MX TPM" if COMPILE_TEST
depends on ARM && CLKDEV_LOOKUP && GENERIC_CLOCKEVENTS
select CLKSRC_MMIO
help
Enable this option to use IMX Timer/PWM Module (TPM) timer as
clocksource.
config CLKSRC_ST_LPC
bool "Low power clocksource found in the LPC" if COMPILE_TEST
select TIMER_OF if OF

View File

@ -67,6 +67,7 @@ obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o
obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o
obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o

View File

@ -114,7 +114,6 @@ static int __init bcm2835_timer_init(struct device_node *node)
timer = kzalloc(sizeof(*timer), GFP_KERNEL);
if (!timer) {
pr_err("Can't allocate timer struct\n");
ret = -ENOMEM;
goto err_iounmap;
}

View File

@ -26,13 +26,13 @@ static int __init tango_clocksource_init(struct device_node *np)
xtal_in_cnt = of_iomap(np, 0);
if (xtal_in_cnt == NULL) {
pr_err("%s: invalid address\n", np->full_name);
pr_err("%pOF: invalid address\n", np);
return -ENXIO;
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
pr_err("%s: invalid clock\n", np->full_name);
pr_err("%pOF: invalid clock\n", np);
return PTR_ERR(clk);
}
@ -43,7 +43,7 @@ static int __init tango_clocksource_init(struct device_node *np)
ret = clocksource_mmio_init(xtal_in_cnt, "tango-xtal", xtal_freq, 350,
32, clocksource_mmio_readl_up);
if (ret) {
pr_err("%s: registration failed\n", np->full_name);
pr_err("%pOF: registration failed\n", np);
return ret;
}

View File

@ -0,0 +1,239 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*/
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#define TPM_SC 0x10
#define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3)
#define TPM_SC_CMOD_DIV_DEFAULT 0x3
#define TPM_CNT 0x14
#define TPM_MOD 0x18
#define TPM_STATUS 0x1c
#define TPM_STATUS_CH0F BIT(0)
#define TPM_C0SC 0x20
#define TPM_C0SC_CHIE BIT(6)
#define TPM_C0SC_MODE_SHIFT 2
#define TPM_C0SC_MODE_MASK 0x3c
#define TPM_C0SC_MODE_SW_COMPARE 0x4
#define TPM_C0V 0x24
static void __iomem *timer_base;
static struct clock_event_device clockevent_tpm;
static inline void tpm_timer_disable(void)
{
unsigned int val;
/* channel disable */
val = readl(timer_base + TPM_C0SC);
val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE);
writel(val, timer_base + TPM_C0SC);
}
static inline void tpm_timer_enable(void)
{
unsigned int val;
/* channel enabled in sw compare mode */
val = readl(timer_base + TPM_C0SC);
val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) |
TPM_C0SC_CHIE;
writel(val, timer_base + TPM_C0SC);
}
static inline void tpm_irq_acknowledge(void)
{
writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
}
static struct delay_timer tpm_delay_timer;
static inline unsigned long tpm_read_counter(void)
{
return readl(timer_base + TPM_CNT);
}
static unsigned long tpm_read_current_timer(void)
{
return tpm_read_counter();
}
static u64 notrace tpm_read_sched_clock(void)
{
return tpm_read_counter();
}
static int __init tpm_clocksource_init(unsigned long rate)
{
tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
tpm_delay_timer.freq = rate;
register_current_timer_delay(&tpm_delay_timer);
sched_clock_register(tpm_read_sched_clock, 32, rate);
return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
rate, 200, 32, clocksource_mmio_readl_up);
}
static int tpm_set_next_event(unsigned long delta,
struct clock_event_device *evt)
{
unsigned long next, now;
next = tpm_read_counter();
next += delta;
writel(next, timer_base + TPM_C0V);
now = tpm_read_counter();
/*
* NOTE: We observed in a very small probability, the bus fabric
* contention between GPU and A7 may results a few cycles delay
* of writing CNT registers which may cause the min_delta event got
* missed, so we need add a ETIME check here in case it happened.
*/
return (int)((next - now) <= 0) ? -ETIME : 0;
}
static int tpm_set_state_oneshot(struct clock_event_device *evt)
{
tpm_timer_enable();
return 0;
}
static int tpm_set_state_shutdown(struct clock_event_device *evt)
{
tpm_timer_disable();
return 0;
}
static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
tpm_irq_acknowledge();
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct clock_event_device clockevent_tpm = {
.name = "i.MX7ULP TPM Timer",
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_state_oneshot = tpm_set_state_oneshot,
.set_next_event = tpm_set_next_event,
.set_state_shutdown = tpm_set_state_shutdown,
.rating = 200,
};
static int __init tpm_clockevent_init(unsigned long rate, int irq)
{
int ret;
ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
"i.MX7ULP TPM Timer", &clockevent_tpm);
clockevent_tpm.cpumask = cpumask_of(0);
clockevent_tpm.irq = irq;
clockevents_config_and_register(&clockevent_tpm,
rate, 300, 0xfffffffe);
return ret;
}
static int __init tpm_timer_init(struct device_node *np)
{
struct clk *ipg, *per;
int irq, ret;
u32 rate;
timer_base = of_iomap(np, 0);
if (!timer_base) {
pr_err("tpm: failed to get base address\n");
return -ENXIO;
}
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
pr_err("tpm: failed to get irq\n");
ret = -ENOENT;
goto err_iomap;
}
ipg = of_clk_get_by_name(np, "ipg");
per = of_clk_get_by_name(np, "per");
if (IS_ERR(ipg) || IS_ERR(per)) {
pr_err("tpm: failed to get igp or per clk\n");
ret = -ENODEV;
goto err_clk_get;
}
/* enable clk before accessing registers */
ret = clk_prepare_enable(ipg);
if (ret) {
pr_err("tpm: ipg clock enable failed (%d)\n", ret);
goto err_clk_get;
}
ret = clk_prepare_enable(per);
if (ret) {
pr_err("tpm: per clock enable failed (%d)\n", ret);
goto err_per_clk_enable;
}
/*
* Initialize tpm module to a known state
* 1) Counter disabled
* 2) TPM counter operates in up counting mode
* 3) Timer Overflow Interrupt disabled
* 4) Channel0 disabled
* 5) DMA transfers disabled
*/
writel(0, timer_base + TPM_SC);
writel(0, timer_base + TPM_CNT);
writel(0, timer_base + TPM_C0SC);
/* increase per cnt, div 8 by default */
writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
timer_base + TPM_SC);
/* set MOD register to maximum for free running mode */
writel(0xffffffff, timer_base + TPM_MOD);
rate = clk_get_rate(per) >> 3;
ret = tpm_clocksource_init(rate);
if (ret)
goto err_per_clk_enable;
ret = tpm_clockevent_init(rate, irq);
if (ret)
goto err_per_clk_enable;
return 0;
err_per_clk_enable:
clk_disable_unprepare(ipg);
err_clk_get:
clk_put(per);
clk_put(ipg);
err_iomap:
iounmap(timer_base);
return ret;
}
TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);

View File

@ -52,7 +52,7 @@ static __init int timer_irq_init(struct device_node *np,
of_irq->irq = irq_of_parse_and_map(np, of_irq->index);
}
if (!of_irq->irq) {
pr_err("Failed to map interrupt for %s\n", np->full_name);
pr_err("Failed to map interrupt for %pOF\n", np);
return -EINVAL;
}
@ -63,8 +63,7 @@ static __init int timer_irq_init(struct device_node *np,
of_irq->flags ? of_irq->flags : IRQF_TIMER,
np->full_name, clkevt);
if (ret) {
pr_err("Failed to request irq %d for %s\n", of_irq->irq,
np->full_name);
pr_err("Failed to request irq %d for %pOF\n", of_irq->irq, np);
return ret;
}
@ -88,20 +87,20 @@ static __init int timer_clk_init(struct device_node *np,
of_clk->clk = of_clk->name ? of_clk_get_by_name(np, of_clk->name) :
of_clk_get(np, of_clk->index);
if (IS_ERR(of_clk->clk)) {
pr_err("Failed to get clock for %s\n", np->full_name);
pr_err("Failed to get clock for %pOF\n", np);
return PTR_ERR(of_clk->clk);
}
ret = clk_prepare_enable(of_clk->clk);
if (ret) {
pr_err("Failed for enable clock for %s\n", np->full_name);
pr_err("Failed for enable clock for %pOF\n", np);
goto out_clk_put;
}
of_clk->rate = clk_get_rate(of_clk->clk);
if (!of_clk->rate) {
ret = -EINVAL;
pr_err("Failed to get clock rate for %s\n", np->full_name);
pr_err("Failed to get clock rate for %pOF\n", np);
goto out_clk_disable;
}

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@ -40,8 +40,7 @@ void __init timer_probe(void)
ret = init_func_ret(np);
if (ret) {
pr_err("Failed to initialize '%s': %d\n",
of_node_full_name(np), ret);
pr_err("Failed to initialize '%pOF': %d\n", np, ret);
continue;
}

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@ -138,7 +138,7 @@ static int __init stm32_clockevent_init(struct device_node *np)
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
ret = -EINVAL;
pr_err("%s: failed to get irq.\n", np->full_name);
pr_err("%pOF: failed to get irq.\n", np);
goto err_get_irq;
}
@ -168,12 +168,12 @@ static int __init stm32_clockevent_init(struct device_node *np)
ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,
"stm32 clockevent", data);
if (ret) {
pr_err("%s: failed to request irq.\n", np->full_name);
pr_err("%pOF: failed to request irq.\n", np);
goto err_get_irq;
}
pr_info("%s: STM32 clockevent driver initialized (%d bits)\n",
np->full_name, bits);
pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
np, bits);
return ret;

View File

@ -28,6 +28,7 @@
#include <linux/workqueue.h>
#include <linux/freezer.h>
#include <linux/compat.h>
#include <linux/module.h>
#include "posix-timers.h"
@ -56,9 +57,9 @@ static ktime_t freezer_delta;
static DEFINE_SPINLOCK(freezer_delta_lock);
#endif
#ifdef CONFIG_RTC_CLASS
static struct wakeup_source *ws;
#ifdef CONFIG_RTC_CLASS
/* rtc timer and device for setting alarm wakeups at suspend */
static struct rtc_timer rtctimer;
static struct rtc_device *rtcdev;
@ -89,6 +90,7 @@ static int alarmtimer_rtc_add_device(struct device *dev,
{
unsigned long flags;
struct rtc_device *rtc = to_rtc_device(dev);
struct wakeup_source *__ws;
if (rtcdev)
return -EBUSY;
@ -98,13 +100,25 @@ static int alarmtimer_rtc_add_device(struct device *dev,
if (!device_may_wakeup(rtc->dev.parent))
return -1;
__ws = wakeup_source_register("alarmtimer");
spin_lock_irqsave(&rtcdev_lock, flags);
if (!rtcdev) {
if (!try_module_get(rtc->owner)) {
spin_unlock_irqrestore(&rtcdev_lock, flags);
return -1;
}
rtcdev = rtc;
/* hold a reference so it doesn't go away */
get_device(dev);
ws = __ws;
__ws = NULL;
}
spin_unlock_irqrestore(&rtcdev_lock, flags);
wakeup_source_unregister(__ws);
return 0;
}
@ -860,7 +874,6 @@ static int __init alarmtimer_init(void)
error = PTR_ERR(pdev);
goto out_drv;
}
ws = wakeup_source_register("alarmtimer");
return 0;
out_drv:

View File

@ -799,7 +799,6 @@ static void check_thread_timers(struct task_struct *tsk,
struct list_head *firing)
{
struct list_head *timers = tsk->cpu_timers;
struct signal_struct *const sig = tsk->signal;
struct task_cputime *tsk_expires = &tsk->cputime_expires;
u64 expires;
unsigned long soft;
@ -823,10 +822,9 @@ static void check_thread_timers(struct task_struct *tsk,
/*
* Check for the special case thread timers.
*/
soft = READ_ONCE(sig->rlim[RLIMIT_RTTIME].rlim_cur);
soft = task_rlimit(tsk, RLIMIT_RTTIME);
if (soft != RLIM_INFINITY) {
unsigned long hard =
READ_ONCE(sig->rlim[RLIMIT_RTTIME].rlim_max);
unsigned long hard = task_rlimit_max(tsk, RLIMIT_RTTIME);
if (hard != RLIM_INFINITY &&
tsk->rt.timeout > DIV_ROUND_UP(hard, USEC_PER_SEC/HZ)) {
@ -847,7 +845,8 @@ static void check_thread_timers(struct task_struct *tsk,
*/
if (soft < hard) {
soft += USEC_PER_SEC;
sig->rlim[RLIMIT_RTTIME].rlim_cur = soft;
tsk->signal->rlim[RLIMIT_RTTIME].rlim_cur =
soft;
}
if (print_fatal_signals) {
pr_info("RT Watchdog Timeout (soft): %s[%d]\n",
@ -938,11 +937,10 @@ static void check_process_timers(struct task_struct *tsk,
SIGPROF);
check_cpu_itimer(tsk, &sig->it[CPUCLOCK_VIRT], &virt_expires, utime,
SIGVTALRM);
soft = READ_ONCE(sig->rlim[RLIMIT_CPU].rlim_cur);
soft = task_rlimit(tsk, RLIMIT_CPU);
if (soft != RLIM_INFINITY) {
unsigned long psecs = div_u64(ptime, NSEC_PER_SEC);
unsigned long hard =
READ_ONCE(sig->rlim[RLIMIT_CPU].rlim_max);
unsigned long hard = task_rlimit_max(tsk, RLIMIT_CPU);
u64 x;
if (psecs >= hard) {
/*

View File

@ -2064,7 +2064,7 @@ void update_wall_time(void)
goto out;
/* Do some additional sanity checking */
timekeeping_check_update(real_tk, offset);
timekeeping_check_update(tk, offset);
/*
* With NO_HZ we may have to accumulate many cycle_intervals

View File

@ -33,6 +33,10 @@
#define MAX_FREQ_ERROR 10e-6
#define MAX_STDDEV 1000e-9
#ifndef ADJ_SETOFFSET
#define ADJ_SETOFFSET 0x0100
#endif
struct sample {
double offset;
double time;
@ -261,7 +265,7 @@ int main(int argc, char **argv)
set_frequency(0.0);
if (fails)
ksft_exit_fail();
return ksft_exit_fail();
ksft_exit_pass();
return ksft_exit_pass();
}

View File

@ -20,6 +20,7 @@
*/
#include <errno.h>
#include <stdio.h>
#include <unistd.h>
#include <time.h>
@ -63,6 +64,7 @@ int alarmcount;
int clock_id;
struct timespec start_time;
long long max_latency_ns;
int timer_fired_early;
char *clockstring(int clockid)
{
@ -115,16 +117,23 @@ void sigalarm(int signo)
delta_ns -= NSEC_PER_SEC * TIMER_SECS * alarmcount;
if (delta_ns < 0)
printf("%s timer fired early: FAIL\n", clockstring(clock_id));
timer_fired_early = 1;
if (delta_ns > max_latency_ns)
max_latency_ns = delta_ns;
}
int do_timer(int clock_id, int flags)
void describe_timer(int flags, int interval)
{
printf("%-22s %s %s ",
clockstring(clock_id),
flags ? "ABSTIME":"RELTIME",
interval ? "PERIODIC":"ONE-SHOT");
}
int setup_timer(int clock_id, int flags, int interval, timer_t *tm1)
{
struct sigevent se;
timer_t tm1;
struct itimerspec its1, its2;
int err;
@ -136,8 +145,9 @@ int do_timer(int clock_id, int flags)
max_latency_ns = 0;
alarmcount = 0;
timer_fired_early = 0;
err = timer_create(clock_id, &se, &tm1);
err = timer_create(clock_id, &se, tm1);
if (err) {
if ((clock_id == CLOCK_REALTIME_ALARM) ||
(clock_id == CLOCK_BOOTTIME_ALARM)) {
@ -158,32 +168,97 @@ int do_timer(int clock_id, int flags)
its1.it_value.tv_sec = TIMER_SECS;
its1.it_value.tv_nsec = 0;
}
its1.it_interval.tv_sec = TIMER_SECS;
its1.it_interval.tv_sec = interval;
its1.it_interval.tv_nsec = 0;
err = timer_settime(tm1, flags, &its1, &its2);
err = timer_settime(*tm1, flags, &its1, &its2);
if (err) {
printf("%s - timer_settime() failed\n", clockstring(clock_id));
return -1;
}
while (alarmcount < 5)
sleep(1);
return 0;
}
printf("%-22s %s max latency: %10lld ns : ",
clockstring(clock_id),
flags ? "ABSTIME":"RELTIME",
max_latency_ns);
int check_timer_latency(int flags, int interval)
{
int err = 0;
describe_timer(flags, interval);
printf("timer fired early: %7d : ", timer_fired_early);
if (!timer_fired_early) {
printf("[OK]\n");
} else {
printf("[FAILED]\n");
err = -1;
}
describe_timer(flags, interval);
printf("max latency: %10lld ns : ", max_latency_ns);
timer_delete(tm1);
if (max_latency_ns < UNRESONABLE_LATENCY) {
printf("[OK]\n");
} else {
printf("[FAILED]\n");
err = -1;
}
return err;
}
int check_alarmcount(int flags, int interval)
{
describe_timer(flags, interval);
printf("count: %19d : ", alarmcount);
if (alarmcount == 1) {
printf("[OK]\n");
return 0;
}
printf("[FAILED]\n");
return -1;
}
int do_timer(int clock_id, int flags)
{
timer_t tm1;
const int interval = TIMER_SECS;
int err;
err = setup_timer(clock_id, flags, interval, &tm1);
if (err)
return err;
while (alarmcount < 5)
sleep(1);
timer_delete(tm1);
return check_timer_latency(flags, interval);
}
int do_timer_oneshot(int clock_id, int flags)
{
timer_t tm1;
const int interval = 0;
struct timeval timeout;
fd_set fds;
int err;
err = setup_timer(clock_id, flags, interval, &tm1);
if (err)
return err;
memset(&timeout, 0, sizeof(timeout));
timeout.tv_sec = 5;
FD_ZERO(&fds);
do {
err = select(FD_SETSIZE, &fds, NULL, NULL, &timeout);
} while (err == -1 && errno == EINTR);
timer_delete(tm1);
err = check_timer_latency(flags, interval);
err |= check_alarmcount(flags, interval);
return err;
}
int main(void)
{
struct sigaction act;
@ -209,6 +284,8 @@ int main(void)
ret |= do_timer(clock_id, TIMER_ABSTIME);
ret |= do_timer(clock_id, 0);
ret |= do_timer_oneshot(clock_id, TIMER_ABSTIME);
ret |= do_timer_oneshot(clock_id, 0);
}
if (ret)
return ksft_exit_fail();