Three regresions in the PowerPC code. One from v3.7 the others from
this merge window. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAABCAAGBQJRbQJxAAoJEIn5HApB1cB6wPAP/Rb/Nm9byySw12YvXz2tdPKp DFJ3J+yMhbh0Tjx5+K+iVO4lCqNk6EYXtOwCuvF9dfpp7IWtx0QwhoTM9U5VeFDT y6+wgKY3CaG9X2IQx+8mUybEiSugsWpMtzOMIOWZLM1iDUtCWtRXybbc1bYWQrOq YOdJICB8EefffghHhABMdtb9g9F/qzati4q+4jd53zJGF5jC9OVDKRCx1TiVyWHF VD0stZoQ8Tb693gC0rLKkSSmg4G2Nj9tuL28YIRW1Un+xJ3eGY2RJ4yz6Pt49tKL czvtU5zHJfIDfVAjMTScentTSBzh+5QxwnPwPYE7zirKKF6+SMSktfF36qTMDkXr nI4x8FMr1iUNOZhK7Y5AAE1sWVtpUWTrR292xGIZeK80lhJDFFuYGd2ToH6ZMwJ/ wDe8Lp2wCbmMExOoI3yAhNRcQia7AyqYBwTfnDCMlmG9OG6f+erCYt8RFBy+hAhG r+/IGrpQEldx+URWBnpc1SqjPCegM9ldw6K+xx0bg0l/dxgd7jnLSFiaOGfa5MRv tdKt+cNv7jf9AM85nJ0fnm6iJwdubbyBRHVkuJXDd5z5twuBqJV9XYxrebh3Td9G tkk5fprBbn7/mD0tr9eBju9eN+/vDDBUE3ENPufIP7j1wOcg2+1UR5BDkEBgJah0 P98LmOINkt+19poWm2P4 =I7AW -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sfr/next-fixes Pull powerpc fixes from Stephen Rothwell: "Three regresions in the PowerPC code. One from v3.7 the others from this merge window." * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sfr/next-fixes: powerpc: add a missing label in resume_kernel powerpc: Fix audit crash due to save/restore PPR changes powerpc: fix compiling CONFIG_PPC_TRANSACTIONAL_MEM when CONFIG_ALTIVEC=n
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commit
de0024b60c
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@ -304,7 +304,7 @@ syscall_exit_work:
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subi r12,r12,TI_FLAGS
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subi r12,r12,TI_FLAGS
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4: /* Anything else left to do? */
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4: /* Anything else left to do? */
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SET_DEFAULT_THREAD_PPR(r3, r9) /* Set thread.ppr = 3 */
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SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
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andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
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andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
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beq .ret_from_except_lite
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beq .ret_from_except_lite
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@ -657,7 +657,7 @@ resume_kernel:
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/* Clear _TIF_EMULATE_STACK_STORE flag */
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/* Clear _TIF_EMULATE_STACK_STORE flag */
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lis r11,_TIF_EMULATE_STACK_STORE@h
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lis r11,_TIF_EMULATE_STACK_STORE@h
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addi r5,r9,TI_FLAGS
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addi r5,r9,TI_FLAGS
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ldarx r4,0,r5
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0: ldarx r4,0,r5
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andc r4,r4,r11
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andc r4,r4,r11
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stdcx. r4,0,r5
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stdcx. r4,0,r5
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bne- 0b
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bne- 0b
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@ -555,10 +555,12 @@ static inline void tm_recheckpoint_new_task(struct task_struct *new)
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new->thread.regs->msr |=
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new->thread.regs->msr |=
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(MSR_FP | new->thread.fpexc_mode);
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(MSR_FP | new->thread.fpexc_mode);
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}
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}
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#ifdef CONFIG_ALTIVEC
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if (msr & MSR_VEC) {
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if (msr & MSR_VEC) {
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do_load_up_transact_altivec(&new->thread);
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do_load_up_transact_altivec(&new->thread);
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new->thread.regs->msr |= MSR_VEC;
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new->thread.regs->msr |= MSR_VEC;
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}
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}
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#endif
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/* We may as well turn on VSX too since all the state is restored now */
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/* We may as well turn on VSX too since all the state is restored now */
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if (msr & MSR_VSX)
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if (msr & MSR_VSX)
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new->thread.regs->msr |= MSR_VSX;
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new->thread.regs->msr |= MSR_VSX;
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@ -866,10 +866,12 @@ static long restore_tm_user_regs(struct pt_regs *regs,
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do_load_up_transact_fpu(¤t->thread);
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do_load_up_transact_fpu(¤t->thread);
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regs->msr |= (MSR_FP | current->thread.fpexc_mode);
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regs->msr |= (MSR_FP | current->thread.fpexc_mode);
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}
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}
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#ifdef CONFIG_ALTIVEC
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if (msr & MSR_VEC) {
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if (msr & MSR_VEC) {
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do_load_up_transact_altivec(¤t->thread);
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do_load_up_transact_altivec(¤t->thread);
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regs->msr |= MSR_VEC;
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regs->msr |= MSR_VEC;
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}
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}
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#endif
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return 0;
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return 0;
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}
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}
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@ -522,10 +522,12 @@ static long restore_tm_sigcontexts(struct pt_regs *regs,
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do_load_up_transact_fpu(¤t->thread);
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do_load_up_transact_fpu(¤t->thread);
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regs->msr |= (MSR_FP | current->thread.fpexc_mode);
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regs->msr |= (MSR_FP | current->thread.fpexc_mode);
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}
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}
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#ifdef CONFIG_ALTIVEC
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if (msr & MSR_VEC) {
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if (msr & MSR_VEC) {
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do_load_up_transact_altivec(¤t->thread);
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do_load_up_transact_altivec(¤t->thread);
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regs->msr |= MSR_VEC;
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regs->msr |= MSR_VEC;
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}
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}
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#endif
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return err;
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return err;
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}
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}
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@ -309,6 +309,7 @@ _GLOBAL(tm_recheckpoint)
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or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
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or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
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mtmsr r5
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mtmsr r5
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#ifdef CONFIG_ALTIVEC
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/* FP and VEC registers: These are recheckpointed from thread.fpr[]
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/* FP and VEC registers: These are recheckpointed from thread.fpr[]
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* and thread.vr[] respectively. The thread.transact_fpr[] version
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* and thread.vr[] respectively. The thread.transact_fpr[] version
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* is more modern, and will be loaded subsequently by any FPUnavailable
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* is more modern, and will be loaded subsequently by any FPUnavailable
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@ -323,6 +324,7 @@ _GLOBAL(tm_recheckpoint)
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REST_32VRS(0, r5, r3) /* r5 scratch, r3 THREAD ptr */
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REST_32VRS(0, r5, r3) /* r5 scratch, r3 THREAD ptr */
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ld r5, THREAD_VRSAVE(r3)
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ld r5, THREAD_VRSAVE(r3)
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mtspr SPRN_VRSAVE, r5
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mtspr SPRN_VRSAVE, r5
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#endif
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dont_restore_vec:
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dont_restore_vec:
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andi. r0, r4, MSR_FP
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andi. r0, r4, MSR_FP
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