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ARM: SoC platform changes for 3.14 

New core SoC-specific changes.
 
 New platforms:
 * Introduction of a vendor, Hisilicon, and one of their SoCs with some
   random numerical product name.
 * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m, i.e. !MMU).
 * Marvell Berlin series of SoCs, which include the one in Chromecast.
 * MOXA platform support, ARM9-based platform used mostly in industrial products
 * Support for Freescale's i.MX50 SoC.
 
 Other work:
 * Renesas work for new platforms and drivers, and conversion over to
   more multiplatform-friendly device registration schemes.
 * SMP support for Allwinner sunxi platforms.
 * ... plus a bunch of other stuff across various platforms.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New core SoC-specific changes.

  New platforms:
   * Introduction of a vendor, Hisilicon, and one of their SoCs with
     some random numerical product name.
   * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
     i.e. !MMU).
   * Marvell Berlin series of SoCs, which include the one in Chromecast.
   * MOXA platform support, ARM9-based platform used mostly in
     industrial products
   * Support for Freescale's i.MX50 SoC.

  Other work:
   * Renesas work for new platforms and drivers, and conversion over to
     more multiplatform-friendly device registration schemes.
   * SMP support for Allwinner sunxi platforms.
   * ... plus a bunch of other stuff across various platforms"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
  ARM: tegra: fix tegra_powergate_sequence_power_up() inline
  ARM: msm_defconfig: Update for multi-platform
  ARM: msm: Move MSM's DT based hardware to multi-platform support
  ARM: msm: Only build timer.c if required
  ARM: msm: Only build clock.c on proc_comm based platforms
  ARM: ux500: Enable system suspend with WFI support
  ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
  ARM: shmobile: r8a7790: Fix I2C controller names
  ARM: msm: Simplify ARCH_MSM_DT config
  ARM: msm: Add support for MSM8974 SoC
  ARM: sunxi: select ARM_PSCI
  MAINTAINERS: Update Allwinner sunXi maintainer files
  ARM: sunxi: Select RESET_CONTROLLER
  ARM: imx: improve the comment of CCM lpm SW workaround
  ARM: imx: improve status check of clock gate
  ARM: imx: add necessary interface for pfd
  ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
  ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
  ARM: imx: Add cpu frequency scaling support
  ARM i.MX35: Add devicetree support.
  ...
This commit is contained in:
Linus Torvalds 2014-01-23 18:40:49 -08:00
parent f2c73464d7 6373bb7187
commit dfd10e7ae6
169 changed files with 6135 additions and 1875 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
Documentation/arm/Marvell/README
View File

@ -211,6 +211,30 @@ MMP/MMP2 family (communication processor)
Linux kernel mach directory: arch/arm/mach-mmp
Linux kernel plat directory: arch/arm/plat-pxa
Berlin family (Digital Entertainment)
-------------------------------------
Flavors:
88DE3005, Armada 1500-mini
Design name: BG2CD
Core: ARM Cortex-A9, PL310 L2CC
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-mini/
88DE3100, Armada 1500
Design name: BG2
Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
88DE????
Design name: BG3
Core: ARM Cortex-A15, CA15 integrated L2CC
Homepage: http://www.marvell.com/digital-entertainment/
Directory: arch/arm/mach-berlin
Comments:
* This line of SoCs is based on Marvell Sheeva or ARM Cortex CPUs
with Synopsys DesignWare (IRQ, GPIO, Timers, ...) and PXA IP (SDHCI, USB, ETH, ...).
Long-term plans
---------------

32
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt Normal file
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@ -0,0 +1,32 @@
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";
Hisilicon system controller
Required properties:
- compatible : "hisilicon,sysctrl"
- reg : Register address and size
Optional properties:
- smp-offset : offset in sysctrl for notifying slave cpu booting
cpu 1, reg;
cpu 2, reg + 0x4;
cpu 3, reg + 0x8;
If reg value is not zero, cpun exit wfi and go
- resume-offset : offset in sysctrl for notifying cpu0 when resume
- reboot-offset : offset in sysctrl for system reboot
Example:
/* for Hi3620 */
sysctrl: system-controller@fc802000 {
compatible = "hisilicon,sysctrl";
reg = <0xfc802000 0x1000>;
smp-offset = <0x31c>;
resume-offset = <0x308>;
reboot-offset = <0x4>;
};

24
Documentation/devicetree/bindings/arm/marvell,berlin.txt Normal file
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@ -0,0 +1,24 @@
Marvell Berlin SoC Family Device Tree Bindings
---------------------------------------------------------------
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:
* Required root node properties:
compatible: must contain "marvell,berlin"
In addition, the above compatible shall be extended with the specific
SoC and board used. Currently known SoC compatibles are:
"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
* Example:
/ {
model = "Sony NSZ-GS7";
compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
...
}

113
Documentation/devicetree/bindings/clock/imx35-clock.txt Normal file
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@ -0,0 +1,113 @@
* Clock bindings for Freescale i.MX35
Required properties:
- compatible: Should be "fsl,imx35-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX35
clocks and IDs.
Clock ID
---------------------------
ckih 0
mpll 1
ppll 2
mpll_075 3
arm 4
hsp 5
hsp_div 6
hsp_sel 7
ahb 8
ipg 9
arm_per_div 10
ahb_per_div 11
ipg_per 12
uart_sel 13
uart_div 14
esdhc_sel 15
esdhc1_div 16
esdhc2_div 17
esdhc3_div 18
spdif_sel 19
spdif_div_pre 20
spdif_div_post 21
ssi_sel 22
ssi1_div_pre 23
ssi1_div_post 24
ssi2_div_pre 25
ssi2_div_post 26
usb_sel 27
usb_div 28
nfc_div 29
asrc_gate 30
pata_gate 31
audmux_gate 32
can1_gate 33
can2_gate 34
cspi1_gate 35
cspi2_gate 36
ect_gate 37
edio_gate 38
emi_gate 39
epit1_gate 40
epit2_gate 41
esai_gate 42
esdhc1_gate 43
esdhc2_gate 44
esdhc3_gate 45
fec_gate 46
gpio1_gate 47
gpio2_gate 48
gpio3_gate 49
gpt_gate 50
i2c1_gate 51
i2c2_gate 52
i2c3_gate 53
iomuxc_gate 54
ipu_gate 55
kpp_gate 56
mlb_gate 57
mshc_gate 58
owire_gate 59
pwm_gate 60
rngc_gate 61
rtc_gate 62
rtic_gate 63
scc_gate 64
sdma_gate 65
spba_gate 66
spdif_gate 67
ssi1_gate 68
ssi2_gate 69
uart1_gate 70
uart2_gate 71
uart3_gate 72
usbotg_gate 73
wdog_gate 74
max_gate 75
admux_gate 76
csi_gate 77
csi_div 78
csi_sel 79
iim_gate 80
gpu2d_gate 81
Examples:
clks: ccm@53f80000 {
compatible = "fsl,imx35-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
clock-names = "ipg", "ahb", "per";
};

195
Documentation/devicetree/bindings/clock/imx5-clock.txt
View File

@ -7,197 +7,8 @@ Required properties:
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX5
clocks and IDs.
Clock ID
---------------------------
dummy 0
ckil 1
osc 2
ckih1 3
ckih2 4
ahb 5
ipg 6
axi_a 7
axi_b 8
uart_pred 9
uart_root 10
esdhc_a_pred 11
esdhc_b_pred 12
esdhc_c_s 13
esdhc_d_s 14
emi_sel 15
emi_slow_podf 16
nfc_podf 17
ecspi_pred 18
ecspi_podf 19
usboh3_pred 20
usboh3_podf 21
usb_phy_pred 22
usb_phy_podf 23
cpu_podf 24
di_pred 25
tve_s 27
uart1_ipg_gate 28
uart1_per_gate 29
uart2_ipg_gate 30
uart2_per_gate 31
uart3_ipg_gate 32
uart3_per_gate 33
i2c1_gate 34
i2c2_gate 35
gpt_ipg_gate 36
pwm1_ipg_gate 37
pwm1_hf_gate 38
pwm2_ipg_gate 39
pwm2_hf_gate 40
gpt_hf_gate 41
fec_gate 42
usboh3_per_gate 43
esdhc1_ipg_gate 44
esdhc2_ipg_gate 45
esdhc3_ipg_gate 46
esdhc4_ipg_gate 47
ssi1_ipg_gate 48
ssi2_ipg_gate 49
ssi3_ipg_gate 50
ecspi1_ipg_gate 51
ecspi1_per_gate 52
ecspi2_ipg_gate 53
ecspi2_per_gate 54
cspi_ipg_gate 55
sdma_gate 56
emi_slow_gate 57
ipu_s 58
ipu_gate 59
nfc_gate 60
ipu_di1_gate 61
vpu_s 62
vpu_gate 63
vpu_reference_gate 64
uart4_ipg_gate 65
uart4_per_gate 66
uart5_ipg_gate 67
uart5_per_gate 68
tve_gate 69
tve_pred 70
esdhc1_per_gate 71
esdhc2_per_gate 72
esdhc3_per_gate 73
esdhc4_per_gate 74
usb_phy_gate 75
hsi2c_gate 76
mipi_hsc1_gate 77
mipi_hsc2_gate 78
mipi_esc_gate 79
mipi_hsp_gate 80
ldb_di1_div_3_5 81
ldb_di1_div 82
ldb_di0_div_3_5 83
ldb_di0_div 84
ldb_di1_gate 85
can2_serial_gate 86
can2_ipg_gate 87
i2c3_gate 88
lp_apm 89
periph_apm 90
main_bus 91
ahb_max 92
aips_tz1 93
aips_tz2 94
tmax1 95
tmax2 96
tmax3 97
spba 98
uart_sel 99
esdhc_a_sel 100
esdhc_b_sel 101
esdhc_a_podf 102
esdhc_b_podf 103
ecspi_sel 104
usboh3_sel 105
usb_phy_sel 106
iim_gate 107
usboh3_gate 108
emi_fast_gate 109
ipu_di0_gate 110
gpc_dvfs 111
pll1_sw 112
pll2_sw 113
pll3_sw 114
ipu_di0_sel 115
ipu_di1_sel 116
tve_ext_sel 117
mx51_mipi 118
pll4_sw 119
ldb_di1_sel 120
di_pll4_podf 121
ldb_di0_sel 122
ldb_di0_gate 123
usb_phy1_gate 124
usb_phy2_gate 125
per_lp_apm 126
per_pred1 127
per_pred2 128
per_podf 129
per_root 130
ssi_apm 131
ssi1_root_sel 132
ssi2_root_sel 133
ssi3_root_sel 134
ssi_ext1_sel 135
ssi_ext2_sel 136
ssi_ext1_com_sel 137
ssi_ext2_com_sel 138
ssi1_root_pred 139
ssi1_root_podf 140
ssi2_root_pred 141
ssi2_root_podf 142
ssi_ext1_pred 143
ssi_ext1_podf 144
ssi_ext2_pred 145
ssi_ext2_podf 146
ssi1_root_gate 147
ssi2_root_gate 148
ssi3_root_gate 149
ssi_ext1_gate 150
ssi_ext2_gate 151
epit1_ipg_gate 152
epit1_hf_gate 153
epit2_ipg_gate 154
epit2_hf_gate 155
can_sel 156
can1_serial_gate 157
can1_ipg_gate 158
owire_gate 159
gpu3d_s 160
gpu2d_s 161
gpu3d_gate 162
gpu2d_gate 163
garb_gate 164
cko1_sel 165
cko1_podf 166
cko1 167
cko2_sel 168
cko2_podf 169
cko2 170
srtc_gate 171
pata_gate 172
sata_gate 173
spdif_xtal_sel 174
spdif0_sel 175
spdif1_sel 176
spdif0_pred 177
spdif0_podf 178
spdif1_pred 179
spdif1_podf 180
spdif0_com_sel 181
spdif1_com_sel 182
spdif0_gate 183
spdif1_gate 184
spdif_ipg_gate 185
ocram 186
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
for the full list of i.MX5 clock IDs.
Examples (for mx53):
@ -212,7 +23,7 @@ can1: can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks 158>, <&clks 157>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};

2
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
View File

@ -14,5 +14,5 @@ intc: interrupt-controller {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
};

32
Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt Normal file
View File

@ -0,0 +1,32 @@
Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
Synopsys DesignWare provides interrupt controller IP for APB known as
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
APB bus, e.g. Marvell Armada 1500.
Required properties:
- compatible: shall be "snps,dw-apb-ictl"
- reg: physical base address of the controller and length of memory mapped
region starting with ENABLE_LOW register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
- interrupts: interrupt reference to primary interrupt controller
- interrupt-parent: (optional) reference specific primary interrupt controller
The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of low interrupts,
- 1 maps to bit 1 of low interrupts,
- 32 maps to bit 0 of high interrupts,
- 33 maps to bit 1 of high interrupts,
- (optional) fast interrupts start at 64.
Example:
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};

19
MAINTAINERS
View File

@ -772,7 +772,12 @@ ARM/Allwinner A1X SoC support
M: Maxime Ripard <maxime.ripard@free-electrons.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-sunxi/
N: sun[x4567]i
ARM/Allwinner SoC Clock Support
M: Emilio López <emilio@elopez.com.ar>
S: Maintained
F: drivers/clk/sunxi/
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
M: Andrew Victor <linux@maxim.org.za>
@ -873,6 +878,12 @@ S: Maintained
F: arch/arm/mach-ebsa110/
F: drivers/net/ethernet/amd/am79c961a.*
ARM/ENERGY MICRO (SILICON LABS) EFM32 SUPPORT
M: Uwe Kleine-König <kernel@pengutronix.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: efm32
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
M: Daniel Ribeiro <drwyrm@gmail.com>
M: Stefan Schmidt <stefan@openezx.org>
@ -1035,6 +1046,12 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-mvebu/
ARM/Marvell Berlin SoC support
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-berlin/
ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
M: Jason Cooper <jason@lakedaemon.net>
M: Andrew Lunn <andrew@lunn.ch>

48
arch/arm/Kconfig
View File

@ -414,6 +414,26 @@ config ARCH_EBSA110
Ethernet interface, two PCMCIA sockets, two serial ports and a
parallel port.
config ARCH_EFM32
bool "Energy Micro efm32"
depends on !MMU
select ARCH_REQUIRE_GPIOLIB
select ARM_NVIC
# CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
# i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
select CLKSRC_MMIO
select CLKSRC_OF
select COMMON_CLK
select CPU_V7M
select GENERIC_CLOCKEVENTS
select NO_DMA
select NO_IOPORT
select SPARSE_IRQ
select USE_OF
help
Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
processors.
config ARCH_EP93XX
bool "EP93xx-based"
select ARCH_HAS_HOLES_MEMORYMODEL
@ -635,10 +655,10 @@ config ARCH_PXA
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
config ARCH_MSM
config ARCH_MSM_NODT
bool "Qualcomm MSM"
select ARCH_MSM
select ARCH_REQUIRE_GPIOLIB
select CLKSRC_OF if OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
help
@ -648,8 +668,9 @@ config ARCH_MSM
stack and controls some vital subsystems
(clock and power control, etc).
config ARCH_SHMOBILE
bool "Renesas SH-Mobile / R-Mobile"
config ARCH_SHMOBILE_LEGACY
bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)"
select ARCH_SHMOBILE
select ARM_PATCH_PHYS_VIRT
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
@ -664,7 +685,8 @@ config ARCH_SHMOBILE
select PM_GENERIC_DOMAINS if PM
select SPARSE_IRQ
help
Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
Support for Renesas's SH-Mobile and R-Mobile ARM platforms using
a non-multiplatform kernel.
config ARCH_RPC
bool "RiscPC"
@ -731,7 +753,7 @@ config ARCH_S3C64XX
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select COMMON_CLK
select CPU_V6
select CPU_V6K
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_S3C2410_I2C if I2C
@ -913,6 +935,8 @@ source "arch/arm/mach-bcm/Kconfig"
source "arch/arm/mach-bcm2835/Kconfig"
source "arch/arm/mach-berlin/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"
@ -929,6 +953,8 @@ source "arch/arm/mach-gemini/Kconfig"
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-hisi/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"
@ -947,6 +973,8 @@ source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/mach-msm/Kconfig"
source "arch/arm/mach-moxart/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/mach-imx/Kconfig"
@ -1613,7 +1641,7 @@ config HZ_FIXED
default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
ARCH_S5PV210 || ARCH_EXYNOS4
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
default 0
choice
@ -1795,10 +1823,10 @@ config ARCH_WANT_GENERAL_HUGETLB
source "mm/Kconfig"
config FORCE_MAX_ZONEORDER
int "Maximum zone order" if ARCH_SHMOBILE
range 11 64 if ARCH_SHMOBILE
int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
range 11 64 if ARCH_SHMOBILE_LEGACY
default "12" if SOC_AM33XX
default "9" if SA1111
default "9" if SA1111 || ARCH_EFM32
default "11"
help
The kernel memory allocator divides physically contiguous memory

19
arch/arm/Kconfig.debug
View File

@ -117,6 +117,14 @@ choice
mobile SoCs in the Kona family of chips (e.g. bcm28155,
bcm11351, etc...)
config DEBUG_BERLIN_UART
bool "Marvell Berlin SoC Debug UART"
depends on ARCH_BERLIN
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on Marvell Berlin SoC based platforms.
config DEBUG_CLPS711X_UART1
bool "Kernel low-level debugging messages via UART1"
depends on ARCH_CLPS711X
@ -278,6 +286,13 @@ choice
Say Y here if you want kernel low-level debugging support
on i.MX35.
config DEBUG_IMX50_UART
bool "i.MX50 Debug UART"
depends on SOC_IMX50
help
Say Y here if you want kernel low-level debugging support
on i.MX50.
config DEBUG_IMX51_UART
bool "i.MX51 Debug UART"
depends on SOC_IMX51
@ -920,6 +935,7 @@ config DEBUG_IMX_UART_PORT
DEBUG_IMX21_IMX27_UART || \
DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
DEBUG_IMX53_UART || \
DEBUG_IMX6Q_UART || \
@ -954,6 +970,7 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX21_IMX27_UART || \
DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
DEBUG_IMX53_UART ||\
DEBUG_IMX6Q_UART || \
@ -1035,6 +1052,7 @@ config DEBUG_UART_PHYS
default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
ARCH_ORION5X
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8b00000 if DEBUG_HI3716_UART
default 0xfcb00000 if DEBUG_HI3620_UART
default 0xfe800000 if ARCH_IOP32X
@ -1060,6 +1078,7 @@ config DEBUG_UART_VIRT
default 0xf2100000 if DEBUG_PXA_UART1
default 0xf4090000 if ARCH_LPC32XX
default 0xf4200000 if ARCH_GEMINI
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT

5
arch/arm/Makefile
View File

@ -144,15 +144,18 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM) += bcm
machine-$(CONFIG_ARCH_BCM2835) += bcm2835
machine-$(CONFIG_ARCH_BERLIN) += berlin
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_DOVE) += dove
machine-$(CONFIG_ARCH_EBSA110) += ebsa110
machine-$(CONFIG_ARCH_EFM32) += efm32
machine-$(CONFIG_ARCH_EP93XX) += ep93xx
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HI3xxx) += hisi
machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
machine-$(CONFIG_ARCH_IOP32X) += iop32x
@ -163,6 +166,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_KS8695) += ks8695
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MOXART) += moxart
machine-$(CONFIG_ARCH_MSM) += msm
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
@ -186,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100) += s5pc100
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
machine-$(CONFIG_ARCH_SA1100) += sa1100
machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile
machine-$(CONFIG_ARCH_SIRF) += prima2
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti

2
arch/arm/boot/compressed/Makefile
View File

@ -64,7 +64,7 @@ else
endif
endif
ifeq ($(CONFIG_ARCH_SHMOBILE),y)
ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y)
OBJS += head-shmobile.o
endif

7
arch/arm/boot/dts/Makefile
View File

@ -46,6 +46,9 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
bcm28155-ap.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
berlin2cd-google-chromecast.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
@ -53,6 +56,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
dove-d2plug.dtb \
dove-d3plug.dtb \
dove-dove-db.dtb
dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
@ -67,6 +71,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
@ -217,7 +222,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \

18
arch/arm/boot/dts/armv7-m.dtsi Normal file
View File

@ -0,0 +1,18 @@
#include "skeleton.dtsi"
/ {
nvic: nv-interrupt-controller {
compatible = "arm,armv7m-nvic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xe000e100 0xc00>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&nvic>;
ranges;
};
};

29
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts Normal file
View File

@ -0,0 +1,29 @@
/*
* Device Tree file for Sony NSZ-GS7
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "berlin2.dtsi"
/ {
model = "Sony NSZ-GS7";
compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
};
&uart0 { status = "okay"; };

227
arch/arm/boot/dts/berlin2.dtsi Normal file
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@ -0,0 +1,227 @@
/*
* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell Armada 1500 (BG2) SoC";
compatible = "marvell,berlin2", "marvell,berlin";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "marvell,pj4b";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
};
cpu@1 {
compatible = "marvell,pj4b";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <1>;
};
};
clocks {
smclk: sysmgr-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cfgclk: cfg-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
sysclk: system-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0 0xf7000000 0x1000000>;
l2: l2-cache-controller@ac0000 {
compatible = "marvell,tauros3-cache", "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "okay";
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "okay";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <8>;
clocks = <&smclk>;
status = "disabled";
};
uart1: serial@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <9>;
clocks = <&smclk>;
status = "disabled";
};
uart2: serial@b000 {
compatible = "snps,dw-apb-uart";
reg = <0xb000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <10>;
clocks = <&smclk>;
status = "disabled";
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};

29
arch/arm/boot/dts/berlin2cd-google-chromecast.dts Normal file
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@ -0,0 +1,29 @@
/*
* Device Tree file for Google Chromecast
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "berlin2cd.dtsi"
/ {
model = "Google Chromecast";
compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
};
&uart0 { status = "okay"; };

210
arch/arm/boot/dts/berlin2cd.dtsi Normal file
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@ -0,0 +1,210 @@
/*
* Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell Armada 1500-mini (BG2CD) SoC";
compatible = "marvell,berlin2cd", "marvell,berlin";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
};
};
clocks {
smclk: sysmgr-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cfgclk: cfg-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <75000000>;
};
sysclk: system-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0 0xf7000000 0x1000000>;
l2: l2-cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "okay";
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "okay";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <8>;
clocks = <&smclk>;
status = "disabled";
};
uart1: serial@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <9>;
clocks = <&smclk>;
status = "disabled";
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};

86
arch/arm/boot/dts/efm32gg-dk3750.dts Normal file
View File

@ -0,0 +1,86 @@
/*
* Device tree for EFM32GG-DK3750 development board.
*
* Documentation available from
* http://www.silabs.com/Support%20Documents/TechnicalDocs/efm32gg-dk3750-ug.pdf
*/
/dts-v1/;
#include "efm32gg.dtsi"
/ {
model = "Energy Micro Giant Gecko Development Kit";
compatible = "efm32,dk3750";
chosen {
bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0";
};
memory {
reg = <0x88000000 0x400000>;
};
soc {
adc@40002000 {
status = "ok";
};
i2c@4000a000 {
location = <3>;
status = "ok";
temp@48 {
compatible = "st,stds75";
reg = <0x48>;
};
eeprom@50 {
compatible = "microchip,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
spi0: spi@4000c000 { /* USART0 */
cs-gpios = <&gpio 68 1>; // E4
location = <1>;
status = "ok";
microsd@0 {
compatible = "mmc-spi-slot";
spi-max-frequency = <100000>;
voltage-ranges = <3200 3400>;
broken-cd;
reg = <0>;
};
};
spi1: spi@4000c400 { /* USART1 */
cs-gpios = <&gpio 51 1>; // D3
location = <1>;
status = "ok";
ks8851@0 {
compatible = "ks8851";
spi-max-frequency = <6000000>;
reg = <0>;
interrupt-parent = <&boardfpga>;
interrupts = <4>;
};
};
uart4: uart@4000e400 { /* UART1 */
location = <2>;
status = "ok";
};
boardfpga: boardfpga {
compatible = "efm32board";
reg = <0x80000000 0x400>;
irq-gpios = <&gpio 64 1>;
interrupt-controller;
#interrupt-cells = <1>;
status = "ok";
};
};
};

172
arch/arm/boot/dts/efm32gg.dtsi Normal file
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@ -0,0 +1,172 @@
/*
* Device tree for Energy Micro EFM32 Giant Gecko SoC.
*
* Documentation available from
* http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf
*/
#include "armv7-m.dtsi"
#include "dt-bindings/clock/efm32-cmu.h"
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
};
soc {
adc: adc@40002000 {
compatible = "efm32,adc";
reg = <0x40002000 0x400>;
interrupts = <7>;
clocks = <&cmu clk_HFPERCLKADC0>;
status = "disabled";
};
gpio: gpio@40006000 {
compatible = "efm32,gpio";
reg = <0x40006000 0x1000>;
interrupts = <1 11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&cmu clk_HFPERCLKGPIO>;
status = "ok";
};
i2c0: i2c@4000a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,i2c";
reg = <0x4000a000 0x400>;
interrupts = <9>;
clocks = <&cmu clk_HFPERCLKI2C0>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@4000a400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,i2c";
reg = <0x4000a400 0x400>;
interrupts = <10>;
clocks = <&cmu clk_HFPERCLKI2C1>;
clock-frequency = <100000>;
status = "disabled";
};
spi0: spi@4000c000 { /* USART0 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,spi";
reg = <0x4000c000 0x400>;
interrupts = <3 4>;
clocks = <&cmu clk_HFPERCLKUSART0>;
status = "disabled";
};
spi1: spi@4000c400 { /* USART1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,spi";
reg = <0x4000c400 0x400>;
interrupts = <15 16>;
clocks = <&cmu clk_HFPERCLKUSART1>;
status = "disabled";
};
spi2: spi@40x4000c800 { /* USART2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,spi";
reg = <0x4000c800 0x400>;
interrupts = <18 19>;
clocks = <&cmu clk_HFPERCLKUSART2>;
status = "disabled";
};
uart0: uart@4000c000 { /* USART0 */
compatible = "efm32,uart";
reg = <0x4000c000 0x400>;
interrupts = <3 4>;
clocks = <&cmu clk_HFPERCLKUSART0>;
status = "disabled";
};
uart1: uart@4000c400 { /* USART1 */
compatible = "efm32,uart";
reg = <0x4000c400 0x400>;
interrupts = <15 16>;
clocks = <&cmu clk_HFPERCLKUSART1>;
status = "disabled";
};
uart2: uart@40x4000c800 { /* USART2 */
compatible = "efm32,uart";
reg = <0x4000c800 0x400>;
interrupts = <18 19>;
clocks = <&cmu clk_HFPERCLKUSART2>;
status = "disabled";
};
uart3: uart@4000e000 { /* UART0 */
compatible = "efm32,uart";
reg = <0x4000e000 0x400>;
interrupts = <20 21>;
clocks = <&cmu clk_HFPERCLKUART0>;
status = "disabled";
};
uart4: uart@4000e400 { /* UART1 */
compatible = "efm32,uart";
reg = <0x4000e400 0x400>;
interrupts = <22 23>;
clocks = <&cmu clk_HFPERCLKUART1>;
status = "disabled";
};
timer0: timer@40010000 {
compatible = "efm32,timer";
reg = <0x40010000 0x400>;
interrupts = <2>;
clocks = <&cmu clk_HFPERCLKTIMER0>;
};
timer1: timer@40010400 {
compatible = "efm32,timer";
reg = <0x40010400 0x400>;
interrupts = <12>;
clocks = <&cmu clk_HFPERCLKTIMER1>;
};
timer2: timer@40010800 {
compatible = "efm32,timer";
reg = <0x40010800 0x400>;
interrupts = <13>;
clocks = <&cmu clk_HFPERCLKTIMER2>;
};
timer3: timer@40010c00 {
compatible = "efm32,timer";
reg = <0x40010c00 0x400>;
interrupts = <14>;
clocks = <&cmu clk_HFPERCLKTIMER3>;
};
cmu: cmu@400c8000 {
compatible = "efm32gg,cmu";
reg = <0x400c8000 0x400>;
interrupts = <32>;
#clock-cells = <1>;
};
};
};

649
arch/arm/boot/dts/hi3620-hi4511.dts Normal file
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@ -0,0 +1,649 @@
/*
* Copyright (C) 2012-2013 Linaro Ltd.
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
#include "hi3620.dtsi"
/ {
model = "Hisilicon Hi4511 Development Board";
compatible = "hisilicon,hi3620-hi4511";
chosen {
bootargs = "console=ttyAMA0,115200 root=/dev/ram0 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
amba {
dual_timer0: dual_timer@800000 {
status = "ok";
};
uart0: uart@b00000 { /* console */
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
status = "ok";
};
uart1: uart@b01000 { /* modem */
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
status = "ok";
};
uart2: uart@b02000 { /* audience */
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
status = "ok";
};
uart3: uart@b03000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
status = "ok";
};
uart4: uart@b04000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
status = "ok";
};
pmx0: pinmux@803000 {
pinctrl-names = "default";
pinctrl-0 = <&board_pmx_pins>;
board_pmx_pins: board_pmx_pins {
pinctrl-single,pins = <
0x008 0x0 /* GPIO -- eFUSE_DOUT */
0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */
>;
};
uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = <
0x0f0 0x0
0x0f4 0x0 /* UART0_RX & UART0_TX */
>;
};
uart0_pmx_idle: uart0_pmx_idle {
pinctrl-single,pins = <
/*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */
0x0f4 0x1 /* UART0_RX & UART0_TX */
>;
};
uart1_pmx_func: uart1_pmx_func {
pinctrl-single,pins = <
0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */
0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */
>;
};
uart1_pmx_idle: uart1_pmx_idle {
pinctrl-single,pins = <
0x0f8 0x1 /* GPIO (IOMG61) */
0x0fc 0x1 /* GPIO (IOMG62) */
>;
};
uart2_pmx_func: uart2_pmx_func {
pinctrl-single,pins = <
0x104 0x2 /* UART2_RXD (IOMG96) */
0x108 0x2 /* UART2_TXD (IOMG64) */
>;
};
uart2_pmx_idle: uart2_pmx_idle {
pinctrl-single,pins = <
0x104 0x1 /* GPIO (IOMG96) */
0x108 0x1 /* GPIO (IOMG64) */
>;
};
uart3_pmx_func: uart3_pmx_func {
pinctrl-single,pins = <
0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */
0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */
>;
};
uart3_pmx_idle: uart3_pmx_idle {
pinctrl-single,pins = <
0x160 0x1 /* GPIO (IOMG85) */
0x164 0x1 /* GPIO (IOMG86) */
>;
};
uart4_pmx_func: uart4_pmx_func {
pinctrl-single,pins = <
0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */
0x16c 0x0 /* UART4_RXD (IOMG88) */
0x170 0x0 /* UART4_TXD (IOMG93) */
>;
};
uart4_pmx_idle: uart4_pmx_idle {
pinctrl-single,pins = <
0x168 0x1 /* GPIO (IOMG87) */
0x16c 0x1 /* GPIO (IOMG88) */
0x170 0x1 /* GPIO (IOMG93) */
>;
};
i2c0_pmx_func: i2c0_pmx_func {
pinctrl-single,pins = <
0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */
>;
};
i2c0_pmx_idle: i2c0_pmx_idle {
pinctrl-single,pins = <
0x0b4 0x1 /* GPIO (IOMG45) */
>;
};
i2c1_pmx_func: i2c1_pmx_func {
pinctrl-single,pins = <
0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */
>;
};
i2c1_pmx_idle: i2c1_pmx_idle {
pinctrl-single,pins = <
0x0b8 0x1 /* GPIO (IOMG46) */
>;
};
i2c2_pmx_func: i2c2_pmx_func {
pinctrl-single,pins = <
0x068 0x0 /* I2C2_SCL (IOMG26) */
0x06c 0x0 /* I2C2_SDA (IOMG27) */
>;
};
i2c2_pmx_idle: i2c2_pmx_idle {
pinctrl-single,pins = <
0x068 0x1 /* GPIO (IOMG26) */
0x06c 0x1 /* GPIO (IOMG27) */
>;
};
i2c3_pmx_func: i2c3_pmx_func {
pinctrl-single,pins = <
0x050 0x2 /* I2C3_SCL (IOMG20) */
0x054 0x2 /* I2C3_SDA (IOMG21) */
>;
};
i2c3_pmx_idle: i2c3_pmx_idle {
pinctrl-single,pins = <
0x050 0x1 /* GPIO (IOMG20) */
0x054 0x1 /* GPIO (IOMG21) */
>;
};
spi0_pmx_func: spi0_pmx_func {
pinctrl-single,pins = <
0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */
0x0d8 0x0 /* SPI0_CS0 (IOMG54) */
0x0dc 0x0 /* SPI0_CS1 (IOMG55) */
0x0e0 0x0 /* SPI0_CS2 (IOMG56) */
0x0e4 0x0 /* SPI0_CS3 (IOMG57) */
>;
};
spi0_pmx_idle: spi0_pmx_idle {
pinctrl-single,pins = <
0x0d4 0x1 /* GPIO (IOMG53) */
0x0d8 0x1 /* GPIO (IOMG54) */
0x0dc 0x1 /* GPIO (IOMG55) */
0x0e0 0x1 /* GPIO (IOMG56) */
0x0e4 0x1 /* GPIO (IOMG57) */
>;
};
spi1_pmx_func: spi1_pmx_func {
pinctrl-single,pins = <
0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */
0x0e8 0x0 /* SPI1_DO (IOMG58) */
0x0ec 0x0 /* SPI1_CS (IOMG95) */
>;
};
spi1_pmx_idle: spi1_pmx_idle {
pinctrl-single,pins = <
0x184 0x1 /* GPIO (IOMG98) */
0x0e8 0x1 /* GPIO (IOMG58) */
0x0ec 0x1 /* GPIO (IOMG95) */
>;
};
kpc_pmx_func: kpc_pmx_func {
pinctrl-single,pins = <
0x12c 0x0 /* KEY_IN0 (IOMG73) */
0x130 0x0 /* KEY_IN1 (IOMG74) */
0x134 0x0 /* KEY_IN2 (IOMG75) */
0x10c 0x0 /* KEY_OUT0 (IOMG65) */
0x110 0x0 /* KEY_OUT1 (IOMG66) */
0x114 0x0 /* KEY_OUT2 (IOMG67) */
>;
};
kpc_pmx_idle: kpc_pmx_idle {
pinctrl-single,pins = <
0x12c 0x1 /* GPIO (IOMG73) */
0x130 0x1 /* GPIO (IOMG74) */
0x134 0x1 /* GPIO (IOMG75) */
0x10c 0x1 /* GPIO (IOMG65) */
0x110 0x1 /* GPIO (IOMG66) */
0x114 0x1 /* GPIO (IOMG67) */
>;
};
gpio_key_func: gpio_key_func {
pinctrl-single,pins = <
0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */
0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */
>;
};
emmc_pmx_func: emmc_pmx_func {
pinctrl-single,pins = <
0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */
0x018 0x0 /* NAND_CS3_N (IOMG6) */
0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */
>;
};
emmc_pmx_idle: emmc_pmx_idle {
pinctrl-single,pins = <
0x030 0x0 /* GPIO (IOMG12) */
0x018 0x1 /* GPIO (IOMG6) */
0x024 0x1 /* GPIO (IOMG8) */
0x028 0x1 /* GPIO (IOMG9) */
0x02c 0x1 /* GPIO (IOMG10) */
>;
};
sd_pmx_func: sd_pmx_func {
pinctrl-single,pins = <
0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */
0x0c0 0x0 /* SD_DATA3 (IOMG48) */
>;
};
sd_pmx_idle: sd_pmx_idle {
pinctrl-single,pins = <
0x0bc 0x1 /* GPIO (IOMG47) */
0x0c0 0x1 /* GPIO (IOMG48) */
>;
};
nand_pmx_func: nand_pmx_func {
pinctrl-single,pins = <
0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */
0x010 0x0 /* NAND_CS1_N (IOMG4) */
0x014 0x0 /* NAND_CS2_N (IOMG5) */
0x018 0x0 /* NAND_CS3_N (IOMG6) */
0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */
0x020 0x0 /* NAND_BUSY1_N (IOMG7) */
0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */
>;
};
nand_pmx_idle: nand_pmx_idle {
pinctrl-single,pins = <
0x00c 0x1 /* GPIO (IOMG3) */
0x010 0x1 /* GPIO (IOMG4) */
0x014 0x1 /* GPIO (IOMG5) */
0x018 0x1 /* GPIO (IOMG6) */
0x01c 0x1 /* GPIO (IOMG94) */
0x020 0x1 /* GPIO (IOMG7) */
0x024 0x1 /* GPIO (IOMG8) */
0x028 0x1 /* GPIO (IOMG9) */
0x02c 0x1 /* GPIO (IOMG10) */
>;
};
sdio_pmx_func: sdio_pmx_func {
pinctrl-single,pins = <
0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */
>;
};
sdio_pmx_idle: sdio_pmx_idle {
pinctrl-single,pins = <
0x0c4 0x1 /* GPIO (IOMG49) */
>;
};
audio_out_pmx_func: audio_out_pmx_func {
pinctrl-single,pins = <
0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */
>;
};
};
pmx1: pinmux@803800 {
pinctrl-names = "default";
pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins
&board_np_pins &board_ps_pins &kpc_cfg_func
&audio_out_cfg_func>;
board_pu_pins: board_pu_pins {
pinctrl-single,pins = <
0x014 0 /* GPIO_158 (IOCFG2) */
0x018 0 /* GPIO_159 (IOCFG3) */
0x01c 0 /* BOOT_MODE0 (IOCFG4) */
0x020 0 /* BOOT_MODE1 (IOCFG5) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
};
board_pd_pins: board_pd_pins {
pinctrl-single,pins = <
0x038 0 /* eFUSE_DOUT (IOCFG11) */
0x150 0 /* ISP_GPIO8 (IOCFG93) */
0x154 0 /* ISP_GPIO9 (IOCFG94) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
board_pd_ps_pins: board_pd_ps_pins {
pinctrl-single,pins = <
0x2d8 0 /* CLK_OUT0 (IOCFG190) */
0x004 0 /* PMU_SPI_DATA (IOCFG192) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
board_np_pins: board_np_pins {
pinctrl-single,pins = <
0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
board_ps_pins: board_ps_pins {
pinctrl-single,pins = <
0x000 0 /* PMU_SPI_CLK (IOCFG191) */
0x008 0 /* PMU_SPI_CS_N (IOCFG193) */
>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
uart0_cfg_func: uart0_cfg_func {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart0_cfg_idle: uart0_cfg_idle {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart1_cfg_func: uart1_cfg_func {
pinctrl-single,pins = <
0x210 0 /* UART1_CTS (IOCFG140) */
0x214 0 /* UART1_RTS (IOCFG141) */
0x218 0 /* UART1_RXD (IOCFG142) */
0x21c 0 /* UART1_TXD (IOCFG143) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart1_cfg_idle: uart1_cfg_idle {
pinctrl-single,pins = <
0x210 0 /* UART1_CTS (IOCFG140) */
0x214 0 /* UART1_RTS (IOCFG141) */
0x218 0 /* UART1_RXD (IOCFG142) */
0x21c 0 /* UART1_TXD (IOCFG143) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart2_cfg_func: uart2_cfg_func {
pinctrl-single,pins = <
0x220 0 /* UART2_CTS (IOCFG144) */
0x224 0 /* UART2_RTS (IOCFG145) */
0x228 0 /* UART2_RXD (IOCFG146) */
0x22c 0 /* UART2_TXD (IOCFG147) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart2_cfg_idle: uart2_cfg_idle {
pinctrl-single,pins = <
0x220 0 /* GPIO (IOCFG144) */
0x224 0 /* GPIO (IOCFG145) */
0x228 0 /* GPIO (IOCFG146) */
0x22c 0 /* GPIO (IOCFG147) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart3_cfg_func: uart3_cfg_func {
pinctrl-single,pins = <
0x294 0 /* UART3_CTS (IOCFG173) */
0x298 0 /* UART3_RTS (IOCFG174) */
0x29c 0 /* UART3_RXD (IOCFG175) */
0x2a0 0 /* UART3_TXD (IOCFG176) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart3_cfg_idle: uart3_cfg_idle {
pinctrl-single,pins = <
0x294 0 /* UART3_CTS (IOCFG173) */
0x298 0 /* UART3_RTS (IOCFG174) */
0x29c 0 /* UART3_RXD (IOCFG175) */
0x2a0 0 /* UART3_TXD (IOCFG176) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart4_cfg_func: uart4_cfg_func {
pinctrl-single,pins = <
0x2a4 0 /* UART4_CTS (IOCFG177) */
0x2a8 0 /* UART4_RTS (IOCFG178) */
0x2ac 0 /* UART4_RXD (IOCFG179) */
0x2b0 0 /* UART4_TXD (IOCFG180) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
i2c0_cfg_func: i2c0_cfg_func {
pinctrl-single,pins = <
0x17c 0 /* I2C0_SCL (IOCFG103) */
0x180 0 /* I2C0_SDA (IOCFG104) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c1_cfg_func: i2c1_cfg_func {
pinctrl-single,pins = <
0x184 0 /* I2C1_SCL (IOCFG105) */
0x188 0 /* I2C1_SDA (IOCFG106) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c2_cfg_func: i2c2_cfg_func {
pinctrl-single,pins = <
0x118 0 /* I2C2_SCL (IOCFG79) */
0x11c 0 /* I2C2_SDA (IOCFG80) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c3_cfg_func: i2c3_cfg_func {
pinctrl-single,pins = <
0x100 0 /* I2C3_SCL (IOCFG73) */
0x104 0 /* I2C3_SDA (IOCFG74) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi0_cfg_func1: spi0_cfg_func1 {
pinctrl-single,pins = <
0x1d4 0 /* SPI0_CLK (IOCFG125) */
0x1d8 0 /* SPI0_DI (IOCFG126) */
0x1dc 0 /* SPI0_DO (IOCFG127) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi0_cfg_func2: spi0_cfg_func2 {
pinctrl-single,pins = <
0x1e0 0 /* SPI0_CS0 (IOCFG128) */
0x1e4 0 /* SPI0_CS1 (IOCFG129) */
0x1e8 0 /* SPI0_CS2 (IOCFG130 */
0x1ec 0 /* SPI0_CS3 (IOCFG131) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi1_cfg_func1: spi1_cfg_func1 {
pinctrl-single,pins = <
0x1f0 0 /* SPI1_CLK (IOCFG132) */
0x1f4 0 /* SPI1_DI (IOCFG133) */
0x1f8 0 /* SPI1_DO (IOCFG134) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi1_cfg_func2: spi1_cfg_func2 {
pinctrl-single,pins = <
0x1fc 0 /* SPI1_CS (IOCFG135) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
kpc_cfg_func: kpc_cfg_func {
pinctrl-single,pins = <
0x250 0 /* KEY_IN0 (IOCFG156) */
0x254 0 /* KEY_IN1 (IOCFG157) */
0x258 0 /* KEY_IN2 (IOCFG158) */
0x230 0 /* KEY_OUT0 (IOCFG148) */
0x234 0 /* KEY_OUT1 (IOCFG149) */
0x238 0 /* KEY_OUT2 (IOCFG150) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
emmc_cfg_func: emmc_cfg_func {
pinctrl-single,pins = <
0x0ac 0 /* eMMC_CMD (IOCFG40) */
0x0b0 0 /* eMMC_CLK (IOCFG41) */
0x058 0 /* NAND_CS3_N (IOCFG19) */
0x064 0 /* NAND_BUSY2_N (IOCFG22) */
0x068 0 /* NAND_BUSY3_N (IOCFG23) */
0x08c 0 /* NAND_DATA8 (IOCFG32) */
0x090 0 /* NAND_DATA9 (IOCFG33) */
0x094 0 /* NAND_DATA10 (IOCFG34) */
0x098 0 /* NAND_DATA11 (IOCFG35) */
0x09c 0 /* NAND_DATA12 (IOCFG36) */
0x0a0 0 /* NAND_DATA13 (IOCFG37) */
0x0a4 0 /* NAND_DATA14 (IOCFG38) */
0x0a8 0 /* NAND_DATA15 (IOCFG39) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sd_cfg_func1: sd_cfg_func1 {
pinctrl-single,pins = <
0x18c 0 /* SD_CLK (IOCFG107) */
0x190 0 /* SD_CMD (IOCFG108) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sd_cfg_func2: sd_cfg_func2 {
pinctrl-single,pins = <
0x194 0 /* SD_DATA0 (IOCFG109) */
0x198 0 /* SD_DATA1 (IOCFG110) */
0x19c 0 /* SD_DATA2 (IOCFG111) */
0x1a0 0 /* SD_DATA3 (IOCFG112) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x70 0xf0>;
};
nand_cfg_func1: nand_cfg_func1 {
pinctrl-single,pins = <
0x03c 0 /* NAND_ALE (IOCFG12) */
0x040 0 /* NAND_CLE (IOCFG13) */
0x06c 0 /* NAND_DATA0 (IOCFG24) */
0x070 0 /* NAND_DATA1 (IOCFG25) */
0x074 0 /* NAND_DATA2 (IOCFG26) */
0x078 0 /* NAND_DATA3 (IOCFG27) */
0x07c 0 /* NAND_DATA4 (IOCFG28) */
0x080 0 /* NAND_DATA5 (IOCFG29) */
0x084 0 /* NAND_DATA6 (IOCFG30) */
0x088 0 /* NAND_DATA7 (IOCFG31) */
0x08c 0 /* NAND_DATA8 (IOCFG32) */
0x090 0 /* NAND_DATA9 (IOCFG33) */
0x094 0 /* NAND_DATA10 (IOCFG34) */
0x098 0 /* NAND_DATA11 (IOCFG35) */
0x09c 0 /* NAND_DATA12 (IOCFG36) */
0x0a0 0 /* NAND_DATA13 (IOCFG37) */
0x0a4 0 /* NAND_DATA14 (IOCFG38) */
0x0a8 0 /* NAND_DATA15 (IOCFG39) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
nand_cfg_func2: nand_cfg_func2 {
pinctrl-single,pins = <
0x044 0 /* NAND_RE_N (IOCFG14) */
0x048 0 /* NAND_WE_N (IOCFG15) */
0x04c 0 /* NAND_CS0_N (IOCFG16) */
0x050 0 /* NAND_CS1_N (IOCFG17) */
0x054 0 /* NAND_CS2_N (IOCFG18) */
0x058 0 /* NAND_CS3_N (IOCFG19) */
0x05c 0 /* NAND_BUSY0_N (IOCFG20) */
0x060 0 /* NAND_BUSY1_N (IOCFG21) */
0x064 0 /* NAND_BUSY2_N (IOCFG22) */
0x068 0 /* NAND_BUSY3_N (IOCFG23) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sdio_cfg_func: sdio_cfg_func {
pinctrl-single,pins = <
0x1a4 0 /* SDIO0_CLK (IOCG113) */
0x1a8 0 /* SDIO0_CMD (IOCG114) */
0x1ac 0 /* SDIO0_DATA0 (IOCG115) */
0x1b0 0 /* SDIO0_DATA1 (IOCG116) */
0x1b4 0 /* SDIO0_DATA2 (IOCG117) */
0x1b8 0 /* SDIO0_DATA3 (IOCG118) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
audio_out_cfg_func: audio_out_cfg_func {
pinctrl-single,pins = <
0x200 0 /* GPIO (IOCFG136) */
0x204 0 /* GPIO (IOCFG137) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
call {
label = "call";
gpios = <&gpio17 2 0>;
linux,code = <169>; /* KEY_PHONE */
};
};
};

565
arch/arm/boot/dts/hi3620.dtsi Normal file
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@ -0,0 +1,565 @@
/*
* Hisilicon Ltd. Hi3620 SoC
*
* Copyright (C) 2012-2013 Hisilicon Ltd.
* Copyright (C) 2012-2013 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/hi3620-clock.h>
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
pclk: clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "apb_pclk";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
};
};
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
interrupt-parent = <&gic>;
ranges = <0 0xfc000000 0x2000000>;
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xfc10000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base */
reg = <0x1000 0x1000>, <0x100 0x100>;
};
sysctrl: system-controller@802000 {
compatible = "hisilicon,sysctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x802000 0x1000>;
reg = <0x802000 0x1000>;
smp-offset = <0x31c>;
resume-offset = <0x308>;
reboot-offset = <0x4>;
clock: clock@0 {
compatible = "hisilicon,hi3620-clock";
reg = <0 0x10000>;
#clock-cells = <1>;
};
};
dual_timer0: dual_timer@800000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x800000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 0 4>, <0 1 4>;
clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@801000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x801000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 2 4>, <0 3 4>;
clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer2: dual_timer@a01000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa01000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 4 4>, <0 5 4>;
clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer3: dual_timer@a02000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa02000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 6 4>, <0 7 4>;
clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer4: dual_timer@a03000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa03000 0x1000>;
/* timer40 & timer41 */
interrupts = <0 96 4>, <0 97 4>;
clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
timer5: timer@600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x600 0x20>;
interrupts = <1 13 0xf01>;
};
uart0: uart@b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb00000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock HI3620_UARTCLK0>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@b01000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb01000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock HI3620_UARTCLK1>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: uart@b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb02000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock HI3620_UARTCLK2>;
clock-names = "apb_pclk";
status = "disabled";
};
uart3: uart@b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb03000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock HI3620_UARTCLK3>;
clock-names = "apb_pclk";
status = "disabled";
};
uart4: uart@b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock HI3620_UARTCLK4>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio0: gpio@806000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x806000 0x1000>;
interrupts = <0 64 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK0>;
clock-names = "apb_pclk";
};
gpio1: gpio@807000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x807000 0x1000>;
interrupts = <0 65 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
&pmx0 6 5 1 &pmx0 7 6 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK1>;
clock-names = "apb_pclk";
};
gpio2: gpio@808000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x808000 0x1000>;
interrupts = <0 66 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
&pmx0 6 3 1 &pmx0 7 3 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK2>;
clock-names = "apb_pclk";
};
gpio3: gpio@809000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x809000 0x1000>;
interrupts = <0 67 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
&pmx0 6 11 1 &pmx0 7 11 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK3>;
clock-names = "apb_pclk";
};
gpio4: gpio@80a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80a000 0x1000>;
interrupts = <0 68 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
&pmx0 6 13 1 &pmx0 7 13 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK4>;
clock-names = "apb_pclk";
};
gpio5: gpio@80b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80b000 0x1000>;
interrupts = <0 69 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
&pmx0 6 16 1 &pmx0 7 16 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK5>;
clock-names = "apb_pclk";
};
gpio6: gpio@80c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80c000 0x1000>;
interrupts = <0 70 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
&pmx0 6 18 1 &pmx0 7 19 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK6>;
clock-names = "apb_pclk";
};
gpio7: gpio@80d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80d000 0x1000>;
interrupts = <0 71 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
&pmx0 6 25 1 &pmx0 7 26 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK7>;
clock-names = "apb_pclk";
};
gpio8: gpio@80e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80e000 0x1000>;
interrupts = <0 72 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
&pmx0 6 33 1 &pmx0 7 34 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK8>;
clock-names = "apb_pclk";
};
gpio9: gpio@80f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80f000 0x1000>;
interrupts = <0 73 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
&pmx0 6 41 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK9>;
clock-names = "apb_pclk";
};
gpio10: gpio@810000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x810000 0x1000>;
interrupts = <0 74 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK10>;
clock-names = "apb_pclk";
};
gpio11: gpio@811000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x811000 0x1000>;
interrupts = <0 75 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
&pmx0 6 49 1 &pmx0 7 49 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK11>;
clock-names = "apb_pclk";
};
gpio12: gpio@812000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x812000 0x1000>;
interrupts = <0 76 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
&pmx0 6 51 1 &pmx0 7 52 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK12>;
clock-names = "apb_pclk";
};
gpio13: gpio@813000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x813000 0x1000>;
interrupts = <0 77 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
&pmx0 6 55 1 &pmx0 7 56 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK13>;
clock-names = "apb_pclk";
};
gpio14: gpio@814000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x814000 0x1000>;
interrupts = <0 78 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
&pmx0 6 60 1 &pmx0 7 61 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK14>;
clock-names = "apb_pclk";
};
gpio15: gpio@815000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x815000 0x1000>;
interrupts = <0 79 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
&pmx0 6 64 1 &pmx0 7 65 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK15>;
clock-names = "apb_pclk";
};
gpio16: gpio@816000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x816000 0x1000>;
interrupts = <0 80 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
&pmx0 6 72 1 &pmx0 7 73 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK16>;
clock-names = "apb_pclk";
};
gpio17: gpio@817000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x817000 0x1000>;
interrupts = <0 81 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
&pmx0 6 80 1 &pmx0 7 81 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK17>;
clock-names = "apb_pclk";
};
gpio18: gpio@818000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x818000 0x1000>;
interrupts = <0 82 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
&pmx0 6 86 1 &pmx0 7 87 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK18>;
clock-names = "apb_pclk";
};
gpio19: gpio@819000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x819000 0x1000>;
interrupts = <0 83 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
&pmx0 3 88 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK19>;
clock-names = "apb_pclk";
};
gpio20: gpio@81a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x81a000 0x1000>;
interrupts = <0 84 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK20>;
clock-names = "apb_pclk";
};
gpio21: gpio@81b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x81b000 0x1000>;
interrupts = <0 85 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK21>;
clock-names = "apb_pclk";
};
pmx0: pinmux@803000 {
compatible = "pinctrl-single";
reg = <0x803000 0x188>;
#address-cells = <1>;
#size-cells = <1>;
#gpio-range-cells = <3>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
&range 12 1 0 &range 13 29 1
&range 43 1 0 &range 44 49 1
&range 94 1 1 &range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pmx1: pinmux@803800 {
compatible = "pinconf-single";
reg = <0x803800 0x2dc>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
};
};
};

33
arch/arm/boot/dts/qcom-msm8974.dtsi Normal file
View File

@ -0,0 +1,33 @@
/dts-v1/;
#include "skeleton.dtsi"
/ {
model = "Qualcomm MSM8974";
compatible = "qcom,msm8974";
interrupt-parent = <&intc>;
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xf9000000 0x1000>,
<0xf9002000 0x1000>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <19200000>;
};
};
};

4
arch/arm/common/timer-sp.c
View File

@ -66,7 +66,7 @@ static long __init sp804_get_clock_rate(struct clk *clk)
static void __iomem *sched_clock_base;
static u32 sp804_read(void)
static u64 notrace sp804_read(void)
{
return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
}
@ -104,7 +104,7 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
if (use_sched_clock) {
sched_clock_base = base;
setup_sched_clock(sp804_read, 32, rate);
sched_clock_register(sp804_read, 32, rate);
}
}

2
arch/arm/configs/ape6evm_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_BLOCK is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A73A4=y
CONFIG_MACH_APE6EVM=y
# CONFIG_ARM_THUMB is not set

2
arch/arm/configs/armadillo800eva_defconfig
View File

@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7740=y
CONFIG_MACH_ARMADILLO800EVA=y
# CONFIG_SH_TIMER_TMU is not set

3
arch/arm/configs/bcm_defconfig
View File

@ -29,11 +29,9 @@ CONFIG_ARCH_BCM_MOBILE=y
CONFIG_ARM_THUMBEE=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
# CONFIG_COMPACTION is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M"
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
@ -120,6 +118,7 @@ CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
# CONFIG_FTRACE is not set
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRC_CCITT=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y

2
arch/arm/configs/bockw_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7778=y
CONFIG_MACH_BOCKW=y
CONFIG_MEMORY_START=0x60000000

102
arch/arm/configs/efm32_defconfig Normal file
View File

@ -0,0 +1,102 @@
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=12
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_UID16 is not set
# CONFIG_BASE_FULL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_MMU is not set
CONFIG_ARCH_EFM32=y
# CONFIG_KUSER_HELPERS is not set
CONFIG_SET_MEM_PARAM=y
CONFIG_DRAM_BASE=0x88000000
CONFIG_DRAM_SIZE=0x00400000
CONFIG_FLASH_MEM_BASE=0x8c000000
CONFIG_FLASH_SIZE=0x01000000
CONFIG_PREEMPT=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_XIP_KERNEL=y
CONFIG_XIP_PHYS_ADDR=0x8c000000
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_SHARED_FLAT=y
# CONFIG_COREDUMP is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK_RO=y
CONFIG_MTD_ROM=y
CONFIG_MTD_UCLINUX=y
CONFIG_PROC_DEVICETREE=y
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_KS8851=y
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_EFM32_UART=y
CONFIG_SERIAL_EFM32_UART_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
CONFIG_SPI_EFM32=y
CONFIG_GPIO_SYSFS=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_SPI=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_FTRACE is not set

56
arch/arm/configs/hi3xxx_defconfig Normal file
View File

@ -0,0 +1,56 @@
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_LZMA=y
CONFIG_ARCH_HI3xxx=y
CONFIG_SMP=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_NETDEVICES=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_REGULATOR_GPIO=y
CONFIG_DRM=y
CONFIG_FB_SIMPLE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_MMC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PL031=y
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_PL330_DMA=y
CONFIG_PWM=y
CONFIG_EXT4_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_LOCKUP_DETECTOR=y

2
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -91,6 +91,7 @@ CONFIG_SMSC911X=y
CONFIG_SMSC_PHY=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_IMX=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
@ -118,6 +119,7 @@ CONFIG_IMX2_WDT=y
CONFIG_MFD_MC13XXX_SPI=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_MEDIA_SUPPORT=y

13
arch/arm/configs/imx_v6_v7_defconfig
View File

@ -28,11 +28,13 @@ CONFIG_MACH_QONG=y
CONFIG_MACH_ARMADILLO5X0=y
CONFIG_MACH_KZM_ARM11_01=y
CONFIG_MACH_IMX31_DT=y
CONFIG_MACH_IMX35_DT=y
CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_VPR200=y
CONFIG_MACH_IMX51_DT=y
CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
@ -41,7 +43,7 @@ CONFIG_SMP=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_VFP=y
CONFIG_NEON=y
@ -89,7 +91,6 @@ CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_SRAM=y
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
# CONFIG_SCSI_PROC_FS is not set
@ -118,6 +119,7 @@ CONFIG_SMC91X=y
CONFIG_SMC911X=y
CONFIG_SMSC911X=y
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_AT803X_PHY=y
CONFIG_BRCMFMAC=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
@ -129,6 +131,8 @@ CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_EGALAX=y
CONFIG_TOUCHSCREEN_MC13783=y
CONFIG_TOUCHSCREEN_TSC2007=y
CONFIG_TOUCHSCREEN_STMPE=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MMA8450=y
CONFIG_SERIO_SERPORT=m
@ -156,14 +160,19 @@ CONFIG_IMX2_WDT=y
CONFIG_MFD_DA9052_I2C=y
CONFIG_MFD_MC13XXX_SPI=y
CONFIG_MFD_MC13XXX_I2C=y
CONFIG_MFD_STMPE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ANATOP=y
CONFIG_REGULATOR_DA9052=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_REGULATOR_PFUZE100=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_RC_SUPPORT=y
CONFIG_RC_DEVICES=y
CONFIG_IR_GPIO_CIR=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_VIDEO_MX3=y

20
arch/arm/configs/keystone_defconfig
View File

@ -115,6 +115,8 @@ CONFIG_MTD_UBI=y
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_EEPROM_AT24=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@ -129,10 +131,24 @@ CONFIG_SPI_DAVINCI=y
CONFIG_SPI_SPIDEV=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
# CONFIG_USB_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_MON=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_DEBUG=y
CONFIG_USB_DWC3_VERBOSE=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_DMADEVICES=y
CONFIG_COMMON_CLK_DEBUG=y
CONFIG_MEMORY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
@ -144,6 +160,8 @@ CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_NFSD_V3=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DEBUG_INFO=y

2
arch/arm/configs/koelsch_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_BLOCK is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7791=y
CONFIG_MACH_KOELSCH=y
# CONFIG_SWP_EMULATE is not set

2
arch/arm/configs/kzm9d_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_EMEV2=y
CONFIG_MACH_KZM9D=y
CONFIG_MEMORY_START=0x40000000

2
arch/arm/configs/kzm9g_defconfig
View File

@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_SH73A0=y
CONFIG_MACH_KZM9G=y
CONFIG_MEMORY_START=0x41000000

2
arch/arm/configs/lager_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7790=y
CONFIG_MACH_LAGER=y
# CONFIG_SH_TIMER_TMU is not set

2
arch/arm/configs/mackerel_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_SH7372=y
CONFIG_MACH_MACKEREL=y
CONFIG_MEMORY_SIZE=0x10000000

2
arch/arm/configs/marzen_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7779=y
CONFIG_MACH_MARZEN=y
CONFIG_MEMORY_START=0x60000000

149
arch/arm/configs/moxart_defconfig Normal file
View File

@ -0,0 +1,149 @@
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_ELF_CORE is not set
# CONFIG_BASE_FULL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_ARCH_MOXART=y
CONFIG_MACH_UC7112LX=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_ATAGS is not set
CONFIG_ARM_APPENDED_DTB=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_PROC_DEVICETREE=y
CONFIG_NETDEVICES=y
CONFIG_NETCONSOLE=y
CONFIG_NETCONSOLE_DYNAMIC=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
CONFIG_ARM_MOXART_ETHER=y
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_REALTEK_PHY=y
CONFIG_MDIO_MOXART=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MOXART=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_MOXART_WDT=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_SDHCI_MOXART=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MOXART=y
CONFIG_DMADEVICES=y
CONFIG_MOXART_DMA=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT3_FS=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_PAGEALLOC=y
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_PROVE_LOCKING=y
CONFIG_DMA_API_DEBUG=y
CONFIG_KGDB=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_UART_8250=y
CONFIG_DEBUG_UART_PHYS=0x98200000
CONFIG_DEBUG_UART_VIRT=0xf9820000
CONFIG_EARLY_PRINTK=y
CONFIG_KEYS=y
CONFIG_CRC32_BIT=y

11
arch/arm/configs/msm_defconfig
View File

@ -17,7 +17,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM_DT=y
CONFIG_ARCH_MSM8X60=y
CONFIG_ARCH_MSM8960=y
CONFIG_SMP=y
@ -29,7 +29,6 @@ CONFIG_CLEANCACHE=y
CONFIG_CC_STACKPROTECTOR=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@ -62,7 +61,6 @@ CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_PHYLIB=y
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_MODE_SLIP6=y
@ -81,10 +79,10 @@ CONFIG_SERIO_LIBPS2=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
CONFIG_SSBI=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY=y
@ -101,7 +99,6 @@ CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_SOC=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_USB=y
CONFIG_USB_PHY=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_MON=y
CONFIG_USB_EHCI_HCD=y
@ -128,10 +125,10 @@ CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_CIFS=y
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_LOCKUP_DETECTOR=y
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_SCHED_DEBUG is not set
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_INFO=y
CONFIG_DYNAMIC_DEBUG=y

4
arch/arm/configs/multi_v7_defconfig
View File

@ -7,8 +7,12 @@ CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_MOBILE=y
CONFIG_ARCH_BERLIN=y
CONFIG_MACH_BERLIN_BG2=y
CONFIG_MACH_BERLIN_BG2CD=y
CONFIG_GPIO_PCA953X=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_HI3xxx=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MXC=y
CONFIG_MACH_IMX51_DT=y

1
arch/arm/configs/u8500_defconfig
View File

@ -119,6 +119,7 @@ CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y

26
arch/arm/configs/versatile_defconfig
View File

@ -1,5 +1,3 @@
CONFIG_ARCH_VERSATILE=y
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
@ -7,15 +5,16 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_VERSATILE=y
CONFIG_MACH_VERSATILE_AB=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=1f03 mem=32M"
CONFIG_FPE_NWFPE=y
CONFIG_VFP=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -26,9 +25,7 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
@ -37,10 +34,10 @@ CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_EEPROM_LEGACY=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_SMC91X=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_AMBAKMI=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_8250=m
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
@ -48,15 +45,14 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=m
CONFIG_GPIOLIB=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_FONT_ACORN_8x8=y
CONFIG_SOUND=y
CONFIG_SND=m
CONFIG_SND_MIXER_OSS=m
@ -64,6 +60,9 @@ CONFIG_SND_PCM_OSS=m
CONFIG_SND_ARMAACI=m
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_EXT2_FS=y
CONFIG_VFAT_FS=m
CONFIG_JFFS2_FS=y
@ -71,15 +70,14 @@ CONFIG_CRAMFS=y
CONFIG_MINIX_FS=y
CONFIG_ROMFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_NFSD_V3=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_ISO8859_1=m
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
CONFIG_FONTS=y
CONFIG_FONT_ACORN_8x8=y

10
arch/arm/include/debug/imx-uart.h
View File

@ -43,6 +43,14 @@
#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
#define IMX50_UART1_BASE_ADDR 0x53fbc000
#define IMX50_UART2_BASE_ADDR 0x53fc0000
#define IMX50_UART3_BASE_ADDR 0x5000c000
#define IMX50_UART4_BASE_ADDR 0x53ff0000
#define IMX50_UART5_BASE_ADDR 0x63f90000
#define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR
#define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n)
#define IMX51_UART1_BASE_ADDR 0x73fbc000
#define IMX51_UART2_BASE_ADDR 0x73fc0000
#define IMX51_UART3_BASE_ADDR 0x7000c000
@ -85,6 +93,8 @@
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
#elif defined(CONFIG_DEBUG_IMX35_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
#elif defined(CONFIG_DEBUG_IMX50_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX50)
#elif defined(CONFIG_DEBUG_IMX51_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
#elif defined(CONFIG_DEBUG_IMX53_UART)

34
arch/arm/include/debug/tegra.S
View File

@ -46,10 +46,10 @@
#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
/*
* Must be 1MB-aligned since a 1MB mapping is used early on.
* Must be section-aligned since a section mapping is used early on.
* Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
*/
#define UART_VIRTUAL_BASE 0xfe100000
#define UART_VIRTUAL_BASE 0xfe800000
#define checkuart(rp, rv, lhu, bit, uart) \
/* Load address of CLK_RST register */ \
@ -156,28 +156,6 @@
92: and \rv, \rp, #0xffffff @ offset within 1MB section
add \rv, \rv, #UART_VIRTUAL_BASE
str \rv, [\tmp, #8] @ Store in tegra_uart_virt
movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
ldr \rv, [\rv, #0] @ Load HIDREV
ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
cmp \rv, #0x20 @ Tegra20?
moveq \rv, #0x75 @ Tegra20 divisor
movne \rv, #0xdd @ Tegra30 divisor
str \rv, [\tmp, #12] @ Save divisor to scratch
/* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
str \rv, [\rp, #UART_LCR << UART_SHIFT]
/* uart[UART_DLL] = div & 0xff; */
ldr \rv, [\tmp, #12]
and \rv, \rv, #0xff
str \rv, [\rp, #UART_DLL << UART_SHIFT]
/* uart[UART_DLM] = div >> 8; */
ldr \rv, [\tmp, #12]
lsr \rv, \rv, #8
str \rv, [\rp, #UART_DLM << UART_SHIFT]
/* uart[UART_LCR] = UART_LCR_WLEN8; */
mov \rv, #UART_LCR_WLEN8
str \rv, [\rp, #UART_LCR << UART_SHIFT]
b 100f
.align
@ -205,8 +183,8 @@
cmp \rx, #0
beq 1002f
1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
and \rd, \rd, #UART_LSR_THRE
teq \rd, #UART_LSR_THRE
bne 1001b
1002:
.endm
@ -225,7 +203,7 @@
/*
* Storage for the state maintained by the macros above.
*
* In the kernel proper, this data is located in arch/arm/mach-tegra/common.c.
* In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
* That's because this header is included from multiple files, and we only
* want a single copy of the data. In particular, the UART probing code above
* assumes it's running using physical addresses. This is true when this file
@ -247,6 +225,4 @@ tegra_uart_config:
.word 0
/* Debug UART virtual address */
.word 0
/* Scratch space for debug macro */
.word 0
#endif

2
arch/arm/mach-at91/Kconfig
View File

@ -90,7 +90,7 @@ config SOC_SAMA5D3
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
endif
if SOC_SAM_V4_V5

3
arch/arm/mach-at91/include/mach/cpu.h
View File

@ -53,6 +53,7 @@
#define ARCH_EXID_SAMA5D33 0x00414300
#define ARCH_EXID_SAMA5D34 0x00414301
#define ARCH_EXID_SAMA5D35 0x00584300
#define ARCH_EXID_SAMA5D36 0x00004301
#define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000
@ -105,7 +106,7 @@ enum at91_soc_subtype {
/* SAMA5D3 */
AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
AT91_SOC_SAMA5D35,
AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
/* No subtype for this SoC */
AT91_SOC_SUBTYPE_NONE,

4
arch/arm/mach-at91/setup.c
View File

@ -233,6 +233,9 @@ static void __init soc_detect(u32 dbgu_base)
case ARCH_EXID_SAMA5D35:
at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
break;
case ARCH_EXID_SAMA5D36:
at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
break;
}
}
}
@ -275,6 +278,7 @@ static const char *soc_subtype_name[] = {
[AT91_SOC_SAMA5D33] = "sama5d33",
[AT91_SOC_SAMA5D34] = "sama5d34",
[AT91_SOC_SAMA5D35] = "sama5d35",
[AT91_SOC_SAMA5D36] = "sama5d36",
[AT91_SOC_SUBTYPE_NONE] = "None",
[AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
};

29
arch/arm/mach-berlin/Kconfig Normal file
View File

@ -0,0 +1,29 @@
config ARCH_BERLIN
bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
select ARM_GIC
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select COMMON_CLK
select DW_APB_ICTL
select DW_APB_TIMER_OF
if ARCH_BERLIN
menu "Marvell Berlin SoC variants"
config MACH_BERLIN_BG2
bool "Marvell Armada 1500 (BG2)"
select CACHE_L2X0
select CPU_PJ4B
select HAVE_ARM_TWD if SMP
select HAVE_SMP
config MACH_BERLIN_BG2CD
bool "Marvell Armada 1500-mini (BG2CD)"
select CACHE_L2X0
select CPU_V7
select HAVE_ARM_TWD if SMP
endmenu
endif

1
arch/arm/mach-berlin/Makefile Normal file
View File

@ -0,0 +1 @@
obj-y += berlin.o

39
arch/arm/mach-berlin/berlin.c Normal file
View File

@ -0,0 +1,39 @@
/*
* Device Tree support for Marvell Berlin SoCs.
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
static void __init berlin_init_machine(void)
{
/*
* with DT probing for L2CCs, berlin_init_machine can be removed.
* Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
*/
l2x0_of_init(0x70c00000, 0xfeffffff);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const berlin_dt_compat[] = {
"marvell,berlin",
NULL,
};
DT_MACHINE_START(BERLIN_DT, "Marvell Berlin")
.dt_compat = berlin_dt_compat,
.init_machine = berlin_init_machine,
MACHINE_END

4
arch/arm/mach-clps711x/common.c
View File

@ -259,7 +259,7 @@ asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
} while (1);
}
static u32 notrace clps711x_sched_clock_read(void)
static u64 notrace clps711x_sched_clock_read(void)
{
return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
}
@ -366,7 +366,7 @@ void __init clps711x_timer_init(void)
tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
clps_writel(tmp, SYSCON1);
setup_sched_clock(clps711x_sched_clock_read, 16, timl);
sched_clock_register(clps711x_sched_clock_read, 16, timl);
clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
"clps711x_clocksource", timl, 300, 16,

2
arch/arm/mach-davinci/clock.c
View File

@ -133,7 +133,7 @@ EXPORT_SYMBOL(clk_get_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
return 0;
if (clk->round_rate)
return clk->round_rate(clk, rate);

4
arch/arm/mach-davinci/time.c
View File

@ -285,7 +285,7 @@ static struct clocksource clocksource_davinci = {
/*
* Overwrite weak default sched_clock with something more precise
*/
static u32 notrace davinci_read_sched_clock(void)
static u64 notrace davinci_read_sched_clock(void)
{
return timer32_read(&timers[TID_CLOCKSOURCE]);
}
@ -391,7 +391,7 @@ void __init davinci_timer_init(void)
davinci_clock_tick_rate))
printk(err, clocksource_davinci.name);
setup_sched_clock(davinci_read_sched_clock, 32,
sched_clock_register(davinci_read_sched_clock, 32,
davinci_clock_tick_rate);
/* setup clockevent */

1
arch/arm/mach-efm32/Makefile Normal file
View File

@ -0,0 +1 @@
obj-y += dtmachine.o

3
arch/arm/mach-efm32/Makefile.boot Normal file
View File

@ -0,0 +1,3 @@
# Empty file waiting for deletion once Makefile.boot isn't needed any more.
# Patch waits for application at
# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .

15
arch/arm/mach-efm32/dtmachine.c Normal file
View File

@ -0,0 +1,15 @@
#include <linux/kernel.h>
#include <asm/v7m.h>
#include <asm/mach/arch.h>
static const char *const efm32gg_compat[] __initconst = {
"efm32,dk3750",
NULL
};
DT_MACHINE_START(EFM32DT, "EFM32 (Device Tree Support)")
.dt_compat = efm32gg_compat,
.restart = armv7m_restart,
MACHINE_END

4
arch/arm/mach-efm32/include/mach/entry-macro.S Normal file
View File

@ -0,0 +1,4 @@
/*
* Empty file waiting for deletion once <mach/entry-macro.S> isn't needed any
* more. Patch "ARM: v7-M: drop using mach/entry-macro.S" sitting in next.
*/

3
arch/arm/mach-efm32/include/mach/timex.h Normal file
View File

@ -0,0 +1,3 @@
/*
* Empty file waiting for deletion once <mach/timex.h> isn't needed any more.
*/

1
arch/arm/mach-ep93xx/Kconfig
View File

@ -5,6 +5,7 @@ menu "Cirrus EP93xx Implementation Options"
config EP93XX_SOC_COMMON
bool
default y
select SOC_BUS
select LEDS_GPIO_REGISTER
config CRUNCH

110
arch/arm/mach-ep93xx/core.c
View File

@ -21,6 +21,7 @@
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/sys_soc.h>
#include <linux/timex.h>
#include <linux/irq.h>
#include <linux/io.h>
@ -44,6 +45,7 @@
#include <linux/platform_data/spi-ep93xx.h>
#include <mach/gpio-ep93xx.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
@ -137,7 +139,7 @@ static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
static struct irqaction ep93xx_timer_irq = {
.name = "ep93xx timer",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = ep93xx_timer_interrupt,
};
@ -925,8 +927,108 @@ void ep93xx_ide_release_gpio(struct platform_device *pdev)
}
EXPORT_SYMBOL(ep93xx_ide_release_gpio);
void __init ep93xx_init_devices(void)
/*************************************************************************
* EP93xx Security peripheral
*************************************************************************/
/*
* The Maverick Key is 256 bits of micro fuses blown at the factory during
* manufacturing to uniquely identify a part.
*
* See: http://arm.cirrus.com/forum/viewtopic.php?t=486&highlight=maverick+key
*/
#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
#define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400)
#define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410)
#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
#define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450)
#define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460)
#define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500)
#define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504)
#define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520)
#define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524)
#define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700)
#define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704)
#define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708)
#define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c)
static char ep93xx_soc_id[33];
static const char __init *ep93xx_get_soc_id(void)
{
unsigned int id, id2, id3, id4, id5;
if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1)
return "bad Hamming code";
id = __raw_readl(EP93XX_SECURITY_UNIQID);
id2 = __raw_readl(EP93XX_SECURITY_UNIQID2);
id3 = __raw_readl(EP93XX_SECURITY_UNIQID3);
id4 = __raw_readl(EP93XX_SECURITY_UNIQID4);
id5 = __raw_readl(EP93XX_SECURITY_UNIQID5);
if (id != id2)
return "invalid";
snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),
"%08x%08x%08x%08x", id2, id3, id4, id5);
return ep93xx_soc_id;
}
static const char __init *ep93xx_get_soc_rev(void)
{
int rev = ep93xx_chip_revision();
switch (rev) {
case EP93XX_CHIP_REV_D0:
return "D0";
case EP93XX_CHIP_REV_D1:
return "D1";
case EP93XX_CHIP_REV_E0:
return "E0";
case EP93XX_CHIP_REV_E1:
return "E1";
case EP93XX_CHIP_REV_E2:
return "E2";
default:
return "unknown";
}
}
static const char __init *ep93xx_get_machine_name(void)
{
return kasprintf(GFP_KERNEL,"%s", machine_desc->name);
}
static struct device __init *ep93xx_init_soc(void)
{
struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return NULL;
soc_dev_attr->machine = ep93xx_get_machine_name();
soc_dev_attr->family = "Cirrus Logic EP93xx";
soc_dev_attr->revision = ep93xx_get_soc_rev();
soc_dev_attr->soc_id = ep93xx_get_soc_id();
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr->machine);
kfree(soc_dev_attr);
return NULL;
}
return soc_device_to_device(soc_dev);
}
struct device __init *ep93xx_init_devices(void)
{
struct device *parent;
/* Disallow access to MaverickCrunch initially */
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
@ -937,6 +1039,8 @@ void __init ep93xx_init_devices(void)
EP93XX_SYSCON_DEVCFG_GONIDE |
EP93XX_SYSCON_DEVCFG_HONIDE);
parent = ep93xx_init_soc();
/* Get the GPIO working early, other devices need it */
platform_device_register(&ep93xx_gpio_device);
@ -949,6 +1053,8 @@ void __init ep93xx_init_devices(void)
platform_device_register(&ep93xx_wdt_device);
gpio_led_register_device(-1, &ep93xx_led_data);
return parent;
}
void ep93xx_restart(enum reboot_mode mode, const char *cmd)

3
arch/arm/mach-ep93xx/include/mach/platform.h
View File

@ -6,6 +6,7 @@
#include <linux/reboot.h>
struct device;
struct i2c_gpio_platform_data;
struct i2c_board_info;
struct spi_board_info;
@ -54,7 +55,7 @@ void ep93xx_register_ide(void);
int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
void ep93xx_ide_release_gpio(struct platform_device *pdev);
void ep93xx_init_devices(void);
struct device *ep93xx_init_devices(void);
extern void ep93xx_timer_init(void);
void ep93xx_restart(enum reboot_mode, const char *);

17
arch/arm/mach-hisi/Kconfig Normal file
View File

@ -0,0 +1,17 @@
config ARCH_HI3xxx
bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
select ARM_AMBA
select ARM_GIC
select ARM_TIMER_SP804
select ARCH_WANT_OPTIONAL_GPIOLIB
select CACHE_L2X0
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU
select HAVE_ARM_TWD
select HAVE_SMP
select PINCTRL
select PINCTRL_SINGLE
select SMP
help
Support for Hisilicon Hi36xx/Hi37xx processor family

7
arch/arm/mach-hisi/Makefile Normal file
View File

@ -0,0 +1,7 @@
#
# Makefile for Hisilicon processors family
#
obj-y += hisilicon.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

15
arch/arm/mach-hisi/core.h Normal file
View File

@ -0,0 +1,15 @@
#ifndef __HISILICON_CORE_H
#define __HISILICON_CORE_H
#include <linux/reboot.h>
extern void hi3xxx_set_cpu_jump(int cpu, void *jump_addr);
extern int hi3xxx_get_cpu_jump(int cpu);
extern void secondary_startup(void);
extern struct smp_operations hi3xxx_smp_ops;
extern void hi3xxx_cpu_die(unsigned int cpu);
extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable);
#endif

90
arch/arm/mach-hisi/hisilicon.c Normal file
View File

@ -0,0 +1,90 @@
/*
* (Hisilicon's SoC based) flattened device tree enabled machine
*
* Copyright (c) 2012-2013 Hisilicon Ltd.
* Copyright (c) 2012-2013 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/proc-fns.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "core.h"
#define HI3620_SYSCTRL_PHYS_BASE 0xfc802000
#define HI3620_SYSCTRL_VIRT_BASE 0xfe802000
/*
* This table is only for optimization. Since ioremap() could always share
* the same mapping if it's defined as static IO mapping.
*
* Without this table, system could also work. The cost is some virtual address
* spaces wasted since ioremap() may be called multi times for the same
* IO space.
*/
static struct map_desc hi3620_io_desc[] __initdata = {
{
/* sysctrl */
.pfn = __phys_to_pfn(HI3620_SYSCTRL_PHYS_BASE),
.virtual = HI3620_SYSCTRL_VIRT_BASE,
.length = 0x1000,
.type = MT_DEVICE,
},
};
static void __init hi3620_map_io(void)
{
debug_ll_io_init();
iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
}
static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
void __iomem *base;
int offset;
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
pr_err("failed to find hisilicon,sysctrl node\n");
return;
}
base = of_iomap(np, 0);
if (!base) {
pr_err("failed to map address in hisilicon,sysctrl node\n");
return;
}
if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
pr_err("failed to find reboot-offset property\n");
return;
}
writel_relaxed(0xdeadbeef, base + offset);
while (1)
cpu_do_idle();
}
static const char *hi3xxx_compat[] __initconst = {
"hisilicon,hi3620-hi4511",
NULL,
};
DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
.map_io = hi3620_map_io,
.dt_compat = hi3xxx_compat,
.smp = smp_ops(hi3xxx_smp_ops),
.restart = hi3xxx_restart,
MACHINE_END

200
arch/arm/mach-hisi/hotplug.c Normal file
View File

@ -0,0 +1,200 @@
/*
* Copyright (c) 2013 Linaro Ltd.
* Copyright (c) 2013 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include "core.h"
/* Sysctrl registers in Hi3620 SoC */
#define SCISOEN 0xc0
#define SCISODIS 0xc4
#define SCPERPWREN 0xd0
#define SCPERPWRDIS 0xd4
#define SCCPUCOREEN 0xf4
#define SCCPUCOREDIS 0xf8
#define SCPERCTRL0 0x200
#define SCCPURSTEN 0x410
#define SCCPURSTDIS 0x414
/*
* bit definition in SCISOEN/SCPERPWREN/...
*
* CPU2_ISO_CTRL (1 << 5)
* CPU3_ISO_CTRL (1 << 6)
* ...
*/
#define CPU2_ISO_CTRL (1 << 5)
/*
* bit definition in SCPERCTRL0
*
* CPU0_WFI_MASK_CFG (1 << 28)
* CPU1_WFI_MASK_CFG (1 << 29)
* ...
*/
#define CPU0_WFI_MASK_CFG (1 << 28)
/*
* bit definition in SCCPURSTEN/...
*
* CPU0_SRST_REQ_EN (1 << 0)
* CPU1_SRST_REQ_EN (1 << 1)
* ...
*/
#define CPU0_HPM_SRST_REQ_EN (1 << 22)
#define CPU0_DBG_SRST_REQ_EN (1 << 12)
#define CPU0_NEON_SRST_REQ_EN (1 << 4)
#define CPU0_SRST_REQ_EN (1 << 0)
enum {
HI3620_CTRL,
ERROR_CTRL,
};
static void __iomem *ctrl_base;
static int id;
static void set_cpu_hi3620(int cpu, bool enable)
{
u32 val = 0;
if (enable) {
/* MTCMOS set */
if ((cpu == 2) || (cpu == 3))
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCPERPWREN);
udelay(100);
/* Enable core */
writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
/* unreset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
/* reset */
val |= CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
/* ISO disable */
if ((cpu == 2) || (cpu == 3))
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCISODIS);
udelay(1);
/* WFI Mask */
val = readl_relaxed(ctrl_base + SCPERCTRL0);
val &= ~(CPU0_WFI_MASK_CFG << cpu);
writel_relaxed(val, ctrl_base + SCPERCTRL0);
/* Unreset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
} else {
/* wfi mask */
val = readl_relaxed(ctrl_base + SCPERCTRL0);
val |= (CPU0_WFI_MASK_CFG << cpu);
writel_relaxed(val, ctrl_base + SCPERCTRL0);
/* disable core*/
writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
if ((cpu == 2) || (cpu == 3)) {
/* iso enable */
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCISOEN);
udelay(1);
}
/* reset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
if ((cpu == 2) || (cpu == 3)) {
/* MTCMOS unset */
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCPERPWRDIS);
udelay(100);
}
}
}
static int hi3xxx_hotplug_init(void)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (node) {
ctrl_base = of_iomap(node, 0);
id = HI3620_CTRL;
return 0;
}
id = ERROR_CTRL;
return -ENOENT;
}
void hi3xxx_set_cpu(int cpu, bool enable)
{
if (!ctrl_base) {
if (hi3xxx_hotplug_init() < 0)
return;
}
if (id == HI3620_CTRL)
set_cpu_hi3620(cpu, enable);
}
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
flush_cache_all();
/*
* Turn off coherency and L1 D-cache
*/
asm volatile(
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, #0x40\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, #0x04\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0)
: "cc");
}
void hi3xxx_cpu_die(unsigned int cpu)
{
cpu_enter_lowpower();
hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
cpu_do_idle();
/* We should have never returned from idle */
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
}
int hi3xxx_cpu_kill(unsigned int cpu)
{
unsigned long timeout = jiffies + msecs_to_jiffies(50);
while (hi3xxx_get_cpu_jump(cpu))
if (time_after(jiffies, timeout))
return 0;
hi3xxx_set_cpu(cpu, false);
return 1;
}

89
arch/arm/mach-hisi/platsmp.c Normal file
View File

@ -0,0 +1,89 @@
/*
* Copyright (c) 2013 Linaro Ltd.
* Copyright (c) 2013 Hisilicon Limited.
* Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include "core.h"
static void __iomem *ctrl_base;
void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
if (!cpu || !ctrl_base)
return;
writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
}
int hi3xxx_get_cpu_jump(int cpu)
{
cpu = cpu_logical_map(cpu);
if (!cpu || !ctrl_base)
return 0;
return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
}
static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np = NULL;
unsigned long base = 0;
u32 offset = 0;
void __iomem *scu_base = NULL;
if (scu_a9_has_base()) {
base = scu_a9_get_base();
scu_base = ioremap(base, SZ_4K);
if (!scu_base) {
pr_err("ioremap(scu_base) failed\n");
return;
}
scu_enable(scu_base);
iounmap(scu_base);
}
if (!ctrl_base) {
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
pr_err("failed to find hisilicon,sysctrl node\n");
return;
}
ctrl_base = of_iomap(np, 0);
if (!ctrl_base) {
pr_err("failed to map address\n");
return;
}
if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
pr_err("failed to find smp-offset property\n");
return;
}
ctrl_base += offset;
}
}
static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
hi3xxx_set_cpu(cpu, true);
hi3xxx_set_cpu_jump(cpu, secondary_startup);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
return 0;
}
struct smp_operations hi3xxx_smp_ops __initdata = {
.smp_prepare_cpus = hi3xxx_smp_prepare_cpus,
.smp_boot_secondary = hi3xxx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = hi3xxx_cpu_die,
.cpu_kill = hi3xxx_cpu_kill,
#endif
};

35
arch/arm/mach-imx/Kconfig
View File

@ -10,6 +10,7 @@ config ARCH_MXC
select GENERIC_IRQ_CHIP
select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
select MULTI_IRQ_HANDLER
select PINCTRL
select SOC_BUS
select SPARSE_IRQ
select USE_OF
@ -19,16 +20,6 @@ config ARCH_MXC
menu "Freescale i.MX support"
depends on ARCH_MXC
config MXC_IRQ_PRIOR
bool "Use IRQ priority"
help
Select this if you want to use prioritized IRQ handling.
This feature prevents higher priority ISR to be interrupted
by lower priority IRQ.
This may be useful in embedded applications, where are strong
requirements for timing.
Say N here, unless you have a specialized requirement.
config MXC_TZIC
bool
@ -108,6 +99,7 @@ config SOC_IMX25
select ARCH_MXC_IOMUX_V3
select CPU_ARM926T
select MXC_AVIC
select PINCTRL_IMX25
config SOC_IMX27
bool
@ -117,6 +109,7 @@ config SOC_IMX27
select IMX_HAVE_IOMUX_V1
select MACH_MX27
select MXC_AVIC
select PINCTRL_IMX27
config SOC_IMX31
bool
@ -132,6 +125,7 @@ config SOC_IMX35
select HAVE_EPIT
select MXC_AVIC
select SMP_ON_UP if SMP
select PINCTRL
config SOC_IMX5
bool
@ -144,7 +138,6 @@ config SOC_IMX5
config SOC_IMX51
bool
select HAVE_IMX_SRC
select PINCTRL
select PINCTRL_IMX51
select SOC_IMX5
@ -618,6 +611,13 @@ config MACH_IMX31_DT
comment "MX35 platforms:"
config MACH_IMX35_DT
bool "Support i.MX35 platforms from device tree"
select SOC_IMX35
help
Include support for Freescale i.MX35 based platforms
using the device tree for discovery.
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select IMX_HAVE_PLATFORM_FLEXCAN
@ -765,11 +765,19 @@ endchoice
comment "Device tree only"
config SOC_IMX50
bool "i.MX50 support"
select HAVE_IMX_SRC
select PINCTRL_IMX50
select SOC_IMX5
help
This enables support for Freescale i.MX50 processor.
config SOC_IMX53
bool "i.MX53 support"
select HAVE_IMX_SRC
select IMX_HAVE_PLATFORM_IMX2_WDT
select PINCTRL
select PINCTRL_IMX53
select SOC_IMX5
@ -795,7 +803,6 @@ config SOC_IMX6Q
select MFD_SYSCON
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
select PINCTRL
select PINCTRL_IMX6Q
select PL310_ERRATA_588369 if CACHE_PL310
select PL310_ERRATA_727915 if CACHE_PL310
@ -816,7 +823,6 @@ config SOC_IMX6SL
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select MFD_SYSCON
select PINCTRL
select PINCTRL_IMX6SL
select PL310_ERRATA_588369 if CACHE_PL310
select PL310_ERRATA_727915 if CACHE_PL310
@ -830,7 +836,6 @@ config SOC_VF610
select CPU_V7
select ARM_GIC
select CLKSRC_OF
select PINCTRL
select PINCTRL_VF610
select VF_PIT_TIMER
select PL310_ERRATA_588369 if CACHE_PL310

2
arch/arm/mach-imx/Makefile
View File

@ -89,6 +89,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
@ -112,6 +113,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o

25
arch/arm/mach-imx/avic.c
View File

@ -54,28 +54,6 @@
static void __iomem *avic_base;
static struct irq_domain *domain;
#ifdef CONFIG_MXC_IRQ_PRIOR
static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
{
struct irq_data *d = irq_get_irq_data(irq);
unsigned int temp;
unsigned int mask = 0x0F << irq % 8 * 4;
irq = d->hwirq;
if (irq >= AVIC_NUM_IRQS)
return -EINVAL;
temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
temp &= ~mask;
temp |= prio & mask;
__raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
return 0;
}
#endif
#ifdef CONFIG_FIQ
static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
{
@ -102,9 +80,6 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
static struct mxc_extra_irq avic_extra_irq = {
#ifdef CONFIG_MXC_IRQ_PRIOR
.set_priority = avic_irq_set_priority,
#endif
#ifdef CONFIG_FIQ
.set_irq_fiq = avic_set_irq_fiq,
#endif

2
arch/arm/mach-imx/clk-gate2.c
View File

@ -72,7 +72,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
reg = readl(gate->reg);
if (((reg >> gate->bit_idx) & 3) == 3)
if (((reg >> gate->bit_idx) & 1) == 1)
return 1;
return 0;

14
arch/arm/mach-imx/clk-imx35.c
View File

@ -45,6 +45,8 @@ static struct arm_ahb_div clk_consumer[] = {
static char hsp_div_532[] = { 4, 8, 3, 0 };
static char hsp_div_400[] = { 3, 6, 3, 0 };
static struct clk_onecell_data clk_data;
static const char *std_sel[] = {"ppll", "arm"};
static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
@ -286,3 +288,15 @@ int __init mx35_clocks_init(void)
return 0;
}
static int __init mx35_clocks_init_dt(struct device_node *ccm_node)
{
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
mx35_clocks_init();
return 0;
}
CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);

788
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -12,11 +12,11 @@
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <dt-bindings/clock/imx5-clock.h>
#include "crm-regs-imx5.h"
#include "clk.h"
@ -83,50 +83,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_
static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
enum imx5_clks {
dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
can_sel, can1_serial_gate, can1_ipg_gate,
owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
cko1_sel, cko1_podf, cko1,
cko2_sel, cko2_podf, cko2,
srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
ocram, clk_max
};
static struct clk *clk[clk_max];
static struct clk *clk[IMX5_CLK_END];
static struct clk_onecell_data clk_data;
static void __init mx5_clocks_common_init(unsigned long rate_ckil,
@ -135,236 +92,296 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
{
int i;
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil);
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc);
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
main_bus_sel, ARRAY_SIZE(main_bus_sel));
clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
per_root_sel, ARRAY_SIZE(per_root_sel));
clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
main_bus_sel, ARRAY_SIZE(main_bus_sel));
clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
per_root_sel, ARRAY_SIZE(per_root_sel));
clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX5 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
clk_register_clkdev(clk[cpu_podf], NULL, "cpu0");
clk_register_clkdev(clk[iim_gate], "iim", NULL);
clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
/* Set SDHC parents to be PLL2 */
clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
/* move usb phy clk to 24MHz */
clk_set_parent(clk[usb_phy_sel], clk[osc]);
clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
clk_prepare_enable(clk[gpc_dvfs]);
clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
clk_prepare_enable(clk[aips_tz1]);
clk_prepare_enable(clk[aips_tz2]); /* fec */
clk_prepare_enable(clk[spba]);
clk_prepare_enable(clk[emi_fast_gate]); /* fec */
clk_prepare_enable(clk[emi_slow_gate]); /* eim */
clk_prepare_enable(clk[mipi_hsc1_gate]);
clk_prepare_enable(clk[mipi_hsc2_gate]);
clk_prepare_enable(clk[mipi_esc_gate]);
clk_prepare_enable(clk[mipi_hsp_gate]);
clk_prepare_enable(clk[tmax1]);
clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
clk_prepare_enable(clk[IMX5_CLK_SPBA]);
clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
}
static void __init mx50_clocks_init(struct device_node *np)
{
void __iomem *base;
unsigned long r;
int i, irq;
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX50 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mx5_clocks_common_init(0, 0, 0, 0);
/* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
irq = irq_of_parse_and_map(np, 0);
mxc_timer_init(base, irq);
}
CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
unsigned long rate_ckih1, unsigned long rate_ckih2)
{
@ -372,38 +389,40 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
u32 val;
struct device_node *np;
clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
spdif_sel, ARRAY_SIZE(spdif_sel));
clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
spdif_sel, ARRAY_SIZE(spdif_sel));
clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
@ -417,37 +436,37 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0");
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
/* set the usboh3 parent to pll2_sw */
clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
/* set SDHC root clock to 166.25MHZ*/
clk_set_rate(clk[esdhc_a_podf], 166250000);
clk_set_rate(clk[esdhc_b_podf], 166250000);
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
/* System timer */
mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
clk_prepare_enable(clk[iim_gate]);
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
imx_print_silicon_rev("i.MX51", mx51_revision());
clk_disable_unprepare(clk[iim_gate]);
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
/*
* Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
@ -479,57 +498,59 @@ static void __init mx53_clocks_init(struct device_node *np)
unsigned long r;
void __iomem *base;
clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
@ -542,33 +563,36 @@ static void __init mx53_clocks_init(struct device_node *np)
mx5_clocks_common_init(0, 0, 0, 0);
clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0");
clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
/* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[esdhc_a_podf], 200000000);
clk_set_rate(clk[esdhc_b_podf], 200000000);
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
clk_prepare_enable(clk[iim_gate]);
/* move can bus clk to 24MHz */
clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
imx_print_silicon_rev("i.MX53", mx53_revision());
clk_disable_unprepare(clk[iim_gate]);
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
r = clk_round_rate(clk[usboh3_per_gate], 54000000);
clk_set_rate(clk[usboh3_per_gate], r);
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
base = of_iomap(np, 0);

5
arch/arm/mach-imx/clk-imx6q.c
View File

@ -114,7 +114,7 @@ static struct clk *clk[clk_max];
static struct clk_onecell_data clk_data;
static enum mx6q_clks const clks_init_on[] __initconst = {
mmdc_ch0_axi, rom, pll1_sys,
mmdc_ch0_axi, rom, arm,
};
static struct clk_div_table clk_enet_ref_table[] = {
@ -475,6 +475,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
if (ret)
pr_warn("failed to set up CLKO: %d\n", ret);
/* Audio-related clocks configuration */
clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
/* All existing boards with PCIe use LVDS1 */
if (IS_ENABLED(CONFIG_PCI_IMX6))
clk_set_parent(clk[lvds1_sel], clk[sata_ref]);

11
arch/arm/mach-imx/clk-imx6sl.c
View File

@ -29,14 +29,14 @@ static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf"
static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
static const char const *perclk_sels[] = { "ipg", "osc", };
static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
static const char const *uart_sels[] = { "pll3_80m", "osc", };
@ -63,7 +63,7 @@ static struct clk_div_table video_div_table[] = {
{ }
};
static struct clk *clks[IMX6SL_CLK_CLK_END];
static struct clk *clks[IMX6SL_CLK_END];
static struct clk_onecell_data clk_data;
static void __init imx6sl_clocks_init(struct device_node *ccm_node)
@ -104,6 +104,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
/* dev name parent_name flags reg shift width div: flags, div_table lock */
clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
@ -232,6 +233,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
@ -261,6 +263,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
}
/* Audio-related clocks configuration */
clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);

11
arch/arm/mach-imx/clk-pfd.c
View File

@ -109,12 +109,23 @@ static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
static int clk_pfd_is_enabled(struct clk_hw *hw)
{
struct clk_pfd *pfd = to_clk_pfd(hw);
if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1)))
return 0;
return 1;
}
static const struct clk_ops clk_pfd_ops = {
.enable = clk_pfd_enable,
.disable = clk_pfd_disable,
.recalc_rate = clk_pfd_recalc_rate,
.round_rate = clk_pfd_round_rate,
.set_rate = clk_pfd_set_rate,
.is_enabled = clk_pfd_is_enabled,
};
struct clk *imx_clk_pfd(const char *name, const char *parent_name,

23
arch/arm/mach-imx/clk-pllv1.c
View File

@ -18,6 +18,11 @@
*
* PLL clock version 1, found on i.MX1/21/25/27/31/35
*/
#define MFN_BITS (10)
#define MFN_SIGN (BIT(MFN_BITS - 1))
#define MFN_MASK (MFN_SIGN - 1)
struct clk_pllv1 {
struct clk_hw hw;
void __iomem *base;
@ -25,6 +30,11 @@ struct clk_pllv1 {
#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
static inline bool mfn_is_negative(unsigned int mfn)
{
return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
}
static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
/*
* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
* 2's complements number
* 2's complements number.
* On i.MX27 the bit 9 is the sign bit.
*/
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
mfn_abs = 0x400 - mfn;
if (mfn_is_negative(mfn)) {
if (cpu_is_mx27())
mfn_abs = mfn & MFN_MASK;
else
mfn_abs = BIT(MFN_BITS) - mfn;
}
rate = parent_rate * 2;
rate /= pd + 1;
@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
do_div(ll, mfd + 1);
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
if (mfn_is_negative(mfn))
ll = -ll;
ll = (rate * mfi) + ll;

5
arch/arm/mach-imx/clk-vf610.c
View File

@ -298,6 +298,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);

1
arch/arm/mach-imx/common.h
View File

@ -108,6 +108,7 @@ void tzic_handle_irq(struct pt_regs *);
#define imx27_handle_irq avic_handle_irq
#define imx31_handle_irq avic_handle_irq
#define imx35_handle_irq avic_handle_irq
#define imx50_handle_irq tzic_handle_irq
#define imx51_handle_irq tzic_handle_irq
#define imx53_handle_irq tzic_handle_irq

2
arch/arm/mach-imx/imx31-dt.c
View File

@ -25,7 +25,7 @@ static void __init imx31_dt_init(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char *imx31_dt_board_compat[] __initdata = {
static const char *imx31_dt_board_compat[] __initconst = {
"fsl,imx31",
NULL
};

50
arch/arm/mach-imx/imx35-dt.c Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright 2012 Steffen Trumtrar, Pengutronix
*
* based on imx27-dt.c
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/hardware/cache-l2x0.h>
#include "common.h"
#include "mx35.h"
static void __init imx35_dt_init(void)
{
mxc_arch_reset_init_dt();
of_platform_populate(NULL, of_default_bus_match_table,
NULL, NULL);
}
static void __init imx35_irq_init(void)
{
imx_init_l2cache();
mx35_init_irq();
}
static const char *imx35_dt_board_compat[] __initconst = {
"fsl,imx35",
NULL
};
DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = imx35_irq_init,
.handle_irq = imx35_handle_irq,
.init_machine = imx35_dt_init,
.dt_compat = imx35_dt_board_compat,
.restart = mxc_restart,
MACHINE_END

2
arch/arm/mach-imx/imx51-dt.c
View File

@ -29,7 +29,7 @@ static void __init imx51_dt_init(void)
platform_device_register_full(&devinfo);
}
static const char *imx51_dt_board_compat[] __initdata = {
static const char *imx51_dt_board_compat[] __initconst = {
"fsl,imx51",
NULL
};

1
arch/arm/mach-imx/irq-common.h
View File

@ -24,7 +24,6 @@
struct mxc_extra_irq
{
int (*set_priority)(unsigned char irq, unsigned char prio);
int (*set_irq_fiq)(unsigned int irq, unsigned int type);
};

38
arch/arm/mach-imx/mach-imx50.c Normal file
View File

@ -0,0 +1,38 @@
/*
* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "common.h"
static void __init imx50_dt_init(void)
{
mxc_arch_reset_init_dt();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char *imx50_dt_board_compat[] __initconst = {
"fsl,imx50",
NULL
};
DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
.map_io = mx53_map_io,
.init_irq = mx53_init_irq,
.handle_irq = imx50_handle_irq,
.init_machine = imx50_dt_init,
.dt_compat = imx50_dt_board_compat,
.restart = mxc_restart,
MACHINE_END

2
arch/arm/mach-imx/mach-imx53.c
View File

@ -31,7 +31,7 @@ static void __init imx53_dt_init(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char *imx53_dt_board_compat[] __initdata = {
static const char *imx53_dt_board_compat[] __initconst = {
"fsl,imx53",
NULL
};

32
arch/arm/mach-imx/mach-imx6q.c
View File

@ -13,6 +13,7 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
@ -23,6 +24,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
#include <linux/pci.h>
#include <linux/phy.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
@ -78,6 +80,34 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev)
return 0;
}
/*
* fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
* as they are used for slots1-7 PERST#
*/
static void ventana_pciesw_early_fixup(struct pci_dev *dev)
{
u32 dw;
if (!of_machine_is_compatible("gw,ventana"))
return;
if (dev->devfn != 0)
return;
pci_read_config_dword(dev, 0x62c, &dw);
dw |= 0xaaa8; // GPIO1-7 outputs
pci_write_config_dword(dev, 0x62c, dw);
pci_read_config_dword(dev, 0x644, &dw);
dw |= 0xfe; // GPIO1-7 output high
pci_write_config_dword(dev, 0x644, dw);
msleep(100);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
static int ar8031_phy_fixup(struct phy_device *dev)
{
u16 val;
@ -243,7 +273,7 @@ static void __init imx6q_init_irq(void)
irqchip_init();
}
static const char *imx6q_dt_compat[] __initdata = {
static const char *imx6q_dt_compat[] __initconst = {
"fsl,imx6dl",
"fsl,imx6q",
NULL,

10
arch/arm/mach-imx/mach-imx6sl.c
View File

@ -34,6 +34,13 @@ static void __init imx6sl_fec_init(void)
}
}
static void __init imx6sl_init_late(void)
{
/* imx6sl reuses imx6q cpufreq driver */
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
}
static void __init imx6sl_init_machine(void)
{
struct device *parent;
@ -61,7 +68,7 @@ static void __init imx6sl_init_irq(void)
irqchip_init();
}
static const char *imx6sl_dt_compat[] __initdata = {
static const char *imx6sl_dt_compat[] __initconst = {
"fsl,imx6sl",
NULL,
};
@ -70,6 +77,7 @@ DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
.map_io = debug_ll_io_init,
.init_irq = imx6sl_init_irq,
.init_machine = imx6sl_init_machine,
.init_late = imx6sl_init_late,
.dt_compat = imx6sl_dt_compat,
.restart = mxc_restart,
MACHINE_END

2
arch/arm/mach-imx/mach-vf610.c
View File

@ -26,7 +26,7 @@ static void __init vf610_init_irq(void)
irqchip_init();
}
static const char *vf610_dt_compat[] __initdata = {
static const char *vf610_dt_compat[] __initconst = {
"fsl,vf610",
NULL,
};

8
arch/arm/mach-imx/mm-imx5.c
View File

@ -89,15 +89,7 @@ void __init imx51_init_early(void)
void __init imx53_init_early(void)
{
struct device_node *np;
void __iomem *base;
mxc_set_cpu_type(MXC_CPU_MX53);
np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc");
base = of_iomap(np, 0);
WARN_ON(!base);
mxc_iomux_v3_init(base);
imx_src_init();
}

16
arch/arm/mach-imx/pm-imx6q.c
View File

@ -156,10 +156,16 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
}
/*
* Unmask the always pending IOMUXC interrupt #32 as wakeup source to
* deassert dsm_request signal, so that we can ensure dsm_request
* is not asserted when we're going to write CLPCR register to set LPM.
* After setting up LPM bits, we need to mask this wakeup source.
* ERR007265: CCM: When improper low-power sequence is used,
* the SoC enters low power mode before the ARM core executes WFI.
*
* Software workaround:
* 1) Software should trigger IRQ #32 (IOMUX) to be always pending
* by setting IOMUX_GPR1_GINT.
* 2) Software should then unmask IRQ #32 in GPC before setting CCM
* Low-Power mode.
* 3) Software should mask IRQ #32 right after CCM Low-Power mode
* is set (set bits 0-1 of CCM_CLPCR).
*/
iomuxc_irq_desc = irq_to_desc(32);
imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
@ -219,6 +225,8 @@ void __init imx6q_pm_init(void)
WARN_ON(!ccm_base);
/*
* This is for SW workaround step #1 of ERR007265, see comments
* in imx6q_set_lpm for details of this errata.
* Force IOMUXC irq pending, so that the interrupt to GPC can be
* used to deassert dsm_request signal when the signal gets
* asserted unexpectedly.

4
arch/arm/mach-imx/time.c
View File

@ -111,7 +111,7 @@ static void gpt_irq_acknowledge(void)
static void __iomem *sched_clock_reg;
static u32 notrace mxc_read_sched_clock(void)
static u64 notrace mxc_read_sched_clock(void)
{
return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
}
@ -123,7 +123,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
sched_clock_reg = reg;
setup_sched_clock(mxc_read_sched_clock, 32, c);
sched_clock_register(mxc_read_sched_clock, 32, c);
return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
clocksource_mmio_readl_up);
}

4
arch/arm/mach-integrator/integrator_ap.c
View File

@ -277,7 +277,7 @@ struct amba_pl010_data ap_uart_data = {
static unsigned long timer_reload;
static u32 notrace integrator_read_sched_clock(void)
static u64 notrace integrator_read_sched_clock(void)
{
return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
}
@ -298,7 +298,7 @@ static void integrator_clocksource_init(unsigned long inrate,
clocksource_mmio_init(base + TIMER_VALUE, "timer2",
rate, 200, 16, clocksource_mmio_readl_down);
setup_sched_clock(integrator_read_sched_clock, 16, rate);
sched_clock_register(integrator_read_sched_clock, 16, rate);
}
static void __iomem * clkevt_base;

4
arch/arm/mach-ixp4xx/common.c
View File

@ -475,7 +475,7 @@ void __init ixp4xx_sys_init(void)
/*
* sched_clock()
*/
static u32 notrace ixp4xx_read_sched_clock(void)
static u64 notrace ixp4xx_read_sched_clock(void)
{
return *IXP4XX_OSTS;
}
@ -493,7 +493,7 @@ unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
EXPORT_SYMBOL(ixp4xx_timer_freq);
static void __init ixp4xx_clocksource_init(void)
{
setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
ixp4xx_clocksource_read);

2
arch/arm/mach-keystone/Kconfig
View File

@ -11,6 +11,8 @@ config ARCH_KEYSTONE
select ARM_ERRATA_798181 if SMP
select COMMON_CLK_KEYSTONE
select TI_EDMA
select ARCH_SUPPORTS_BIG_ENDIAN
select ZONE_DMA if ARM_LPAE
help
Support for boards based on the Texas Instruments Keystone family of
SoCs.

4
arch/arm/mach-keystone/keystone.c
View File

@ -41,6 +41,7 @@ static void __init keystone_init(void)
if (WARN_ON(!keystone_rstctrl))
pr_warn("ti,keystone-reset iomap error\n");
keystone_pm_runtime_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
@ -68,6 +69,9 @@ void keystone_restart(enum reboot_mode mode, const char *cmd)
}
DT_MACHINE_START(KEYSTONE, "Keystone")
#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
.dma_zone_size = SZ_2G,
#endif
.smp = smp_ops(keystone_smp_ops),
.init_machine = keystone_init,
.dt_compat = keystone_match,

1
arch/arm/mach-keystone/keystone.h
View File

@ -18,6 +18,7 @@
extern struct smp_operations keystone_smp_ops;
extern void secondary_startup(void);
extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr);
extern int keystone_pm_runtime_init(void);
#endif /* __ASSEMBLER__ */
#endif /* __KEYSTONE_H__ */

2
arch/arm/mach-keystone/pm_domain.c
View File

@ -74,9 +74,7 @@ int __init keystone_pm_runtime_init(void)
if (!np)
return 0;
of_clk_init(NULL);
pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier);
return 0;
}
subsys_initcall(keystone_pm_runtime_init);

4
arch/arm/mach-mmp/time.c
View File

@ -61,7 +61,7 @@ static inline uint32_t timer_read(void)
return __raw_readl(mmp_timer_base + TMR_CVWR(1));
}
static u32 notrace mmp_read_sched_clock(void)
static u64 notrace mmp_read_sched_clock(void)
{
return timer_read();
}
@ -195,7 +195,7 @@ void __init timer_init(int irq)
{
timer_config();
setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
sched_clock_register(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
ckevt.cpumask = cpumask_of(0);

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