From 317d5330aea392c032a5f8c87df74444fd514910 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Wed, 9 Nov 2011 10:33:23 -0800 Subject: [PATCH 01/35] arm/tegra: fix variable formatting in makefile For some reason it started out using {} instead of (), and it's proliferated from there. Switch back to (). Signed-off-by: Olof Johansson Acked-by: Colin Cross --- arch/arm/mach-tegra/Makefile | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 91a07e187208..5be8e9eefc95 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -18,20 +18,20 @@ obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_USB_SUPPORT) += usb_phy.o -obj-${CONFIG_MACH_HARMONY} += board-harmony.o -obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o -obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o -obj-${CONFIG_MACH_HARMONY} += board-harmony-power.o +obj-$(CONFIG_MACH_HARMONY) += board-harmony.o +obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o +obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o +obj-$(CONFIG_MACH_HARMONY) += board-harmony-power.o -obj-${CONFIG_MACH_PAZ00} += board-paz00.o -obj-${CONFIG_MACH_PAZ00} += board-paz00-pinmux.o +obj-$(CONFIG_MACH_PAZ00) += board-paz00.o +obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o -obj-${CONFIG_MACH_SEABOARD} += board-seaboard.o -obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o +obj-$(CONFIG_MACH_SEABOARD) += board-seaboard.o +obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o -obj-${CONFIG_MACH_TEGRA_DT} += board-dt.o -obj-${CONFIG_MACH_TEGRA_DT} += board-harmony-pinmux.o -obj-${CONFIG_MACH_TEGRA_DT} += board-seaboard-pinmux.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-dt.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o -obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o -obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o +obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o +obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o From c27317c0ed114152d02b2ed40056f232e5732b9d Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Fri, 4 Nov 2011 09:12:39 +0000 Subject: [PATCH 02/35] arm/dt: add basic usb nodes to tegra device trees For now they are a minimal binding. It needs to be amended with vendor-specific settings for phy setup and link tuning, etc. v2: Added bindings specification and phy_type properties Signed-off-by: Olof Johansson Acked-by: Grant Likely Acked-by: Stephen Warren --- .../devicetree/bindings/usb/tegra-usb.txt | 13 ++++++++++++ arch/arm/boot/dts/tegra-seaboard.dts | 4 ++++ arch/arm/boot/dts/tegra20.dtsi | 21 +++++++++++++++++++ 3 files changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/tegra-usb.txt diff --git a/Documentation/devicetree/bindings/usb/tegra-usb.txt b/Documentation/devicetree/bindings/usb/tegra-usb.txt new file mode 100644 index 000000000000..035d63d5646d --- /dev/null +++ b/Documentation/devicetree/bindings/usb/tegra-usb.txt @@ -0,0 +1,13 @@ +Tegra SOC USB controllers + +The device node for a USB controller that is part of a Tegra +SOC is as described in the document "Open Firmware Recommended +Practice : Universal Serial Bus" with the following modifications +and additions : + +Required properties : + - compatible : Should be "nvidia,tegra20-ehci" for USB controllers + used in host mode. + - phy_type : Should be one of "ulpi" or "utmi". + - nvidia,vbus-gpio : If present, specifies a gpio that needs to be + activated for the bus to be powered. diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index a72299b8e668..88c682a26cb2 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -29,4 +29,8 @@ sdhci@c8000600 { support-8bit; }; + + usb@c5000000 { + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + }; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 65d7e6a333eb..795b921d92fc 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -143,5 +143,26 @@ reg = <0xc8000600 0x200>; interrupts = < 63 >; }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 52 >; + phy_type = "utmi"; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 53 >; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 129 >; + phy_type = "utmi"; + }; }; From 4a53f4e692c5df8a4bf9bf059b8007d575b0204a Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Fri, 4 Nov 2011 09:12:40 +0000 Subject: [PATCH 03/35] USB: ehci-tegra: add probing through device tree Rely on platform_data being passed through auxdata for now; more elaborate bindings for phy config and tunings to be added. v2: moved vbus-gpio check to the helper function, added check for !of_node, added usb2 clock to board-dt table. Signed-off-by: Olof Johansson Cc: Greg Kroah-Hartman Acked-by: Grant Likely --- arch/arm/mach-tegra/board-dt.c | 9 +++++ drivers/usb/host/ehci-tegra.c | 71 ++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index 74743ad3d2d3..7f287a86941e 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -61,12 +61,21 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", + &tegra_ehci1_device.dev.platform_data), + OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", + &tegra_ehci2_device.dev.platform_data), + OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", + &tegra_ehci3_device.dev.platform_data), {} }; static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { /* name parent rate enabled */ { "uartd", "pll_p", 216000000, true }, + { "usbd", "clk_m", 12000000, false }, + { "usb2", "clk_m", 12000000, false }, + { "usb3", "clk_m", 12000000, false }, { NULL, NULL, 0, 0}, }; diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index db9d1b4bfbdc..dbc7fe8ca9e7 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -21,7 +21,12 @@ #include #include #include +#include +#include +#include + #include +#include #define TEGRA_USB_DMA_ALIGN 32 @@ -574,6 +579,35 @@ static const struct hc_driver tegra_ehci_hc_driver = { .port_handed_over = ehci_port_handed_over, }; +static int setup_vbus_gpio(struct platform_device *pdev) +{ + int err = 0; + int gpio; + + if (!pdev->dev.of_node) + return 0; + + gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0); + if (!gpio_is_valid(gpio)) + return 0; + + err = gpio_request(gpio, "vbus_gpio"); + if (err) { + dev_err(&pdev->dev, "can't request vbus gpio %d", gpio); + return err; + } + err = gpio_direction_output(gpio, 1); + if (err) { + dev_err(&pdev->dev, "can't enable vbus\n"); + return err; + } + gpio_set_value(gpio, 1); + + return err; +} + +static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32); + static int tegra_ehci_probe(struct platform_device *pdev) { struct resource *res; @@ -590,6 +624,15 @@ static int tegra_ehci_probe(struct platform_device *pdev) return -EINVAL; } + /* Right now device-tree probed devices don't get dma_mask set. + * Since shared usb code relies on it, set it here for now. + * Once we have dma capability bindings this can go away. + */ + if (!pdev->dev.dma_mask) + pdev->dev.dma_mask = &tegra_ehci_dma_mask; + + setup_vbus_gpio(pdev); + tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); if (!tegra) return -ENOMEM; @@ -640,6 +683,28 @@ static int tegra_ehci_probe(struct platform_device *pdev) goto fail_io; } + /* This is pretty ugly and needs to be fixed when we do only + * device-tree probing. Old code relies on the platform_device + * numbering that we lack for device-tree-instantiated devices. + */ + if (instance < 0) { + switch (res->start) { + case TEGRA_USB_BASE: + instance = 0; + break; + case TEGRA_USB2_BASE: + instance = 1; + break; + case TEGRA_USB3_BASE: + instance = 2; + break; + default: + err = -ENODEV; + dev_err(&pdev->dev, "unknown usb instance\n"); + goto fail_phy; + } + } + tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config, TEGRA_USB_PHY_MODE_HOST); if (IS_ERR(tegra->phy)) { @@ -773,6 +838,11 @@ static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) hcd->driver->shutdown(hcd); } +static struct of_device_id tegra_ehci_of_match[] __devinitdata = { + { .compatible = "nvidia,tegra20-ehci", }, + { }, +}; + static struct platform_driver tegra_ehci_driver = { .probe = tegra_ehci_probe, .remove = tegra_ehci_remove, @@ -783,5 +853,6 @@ static struct platform_driver tegra_ehci_driver = { .shutdown = tegra_ehci_hcd_shutdown, .driver = { .name = "tegra-ehci", + .of_match_table = tegra_ehci_of_match, } }; From 64f88ec3957b8e448e377231d177260ebfda71a2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 7 Dec 2011 15:13:48 -0700 Subject: [PATCH 04/35] arm/dt: tegra: Clean up I2S and DAS nodes The I2S and DAS nodes don't have children, and hence don't need to set address/size cells. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra20.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 795b921d92fc..04068dd49286 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -45,8 +45,6 @@ }; i2s@70002800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; interrupts = < 45 >; @@ -54,8 +52,6 @@ }; i2s@70002a00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; interrupts = < 35 >; @@ -63,8 +59,6 @@ }; das@70000c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; }; From a7db2c15938668999d4ceb1caec3723d88e38c80 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 25 Oct 2011 02:01:28 +0000 Subject: [PATCH 05/35] arm/tegra: Add device-tree support for TrimSlice board * Add device-tree file for TrimSlice * Add that to the list of .dts files to build * Update board-dt.c to recognize TrimSlice board name v2: Makefile: Add board-trimslice-pinmux.c to obj-$(CONFIG_MACH_TEGRA_DT). v3: Makefile: Use brackets not braces around var names Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-trimslice.dts | 38 +++++++++++++++++++++++++++ arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/Makefile.boot | 1 + arch/arm/mach-tegra/board-dt.c | 3 +++ 4 files changed, 43 insertions(+) create mode 100644 arch/arm/boot/dts/tegra-trimslice.dts diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts new file mode 100644 index 000000000000..d3d0d205a474 --- /dev/null +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +/memreserve/ 0x1c000000 0x04000000; +/include/ "tegra20.dtsi" + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + chosen { + bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p1 rw rootwait"; + }; + + memory@0 { + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 121 0>; + wp-gpios = <&gpio 122 0>; + }; +}; diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 5be8e9eefc95..565bb2253529 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-dt.o obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-trimslice-pinmux.o obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index bd12c9fb81e8..9f177a466b83 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -4,4 +4,5 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb +dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index 7f287a86941e..e6b3953a62b9 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -47,6 +47,7 @@ void harmony_pinmux_init(void); void seaboard_pinmux_init(void); +void trimslice_pinmux_init(void); void ventana_pinmux_init(void); struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { @@ -93,6 +94,7 @@ static struct { char *machine; void (*init)(void); } pinmux_configs[] = { + { "compulab,trimslice", trimslice_pinmux_init }, { "nvidia,harmony", harmony_pinmux_init }, { "nvidia,seaboard", seaboard_pinmux_init }, { "nvidia,ventana", ventana_pinmux_init }, @@ -129,6 +131,7 @@ static void __init tegra_dt_init(void) } static const char * tegra_dt_board_compat[] = { + "compulab,trimslice", "nvidia,harmony", "nvidia,seaboard", "nvidia,ventana", From cc2afa43d43cd07d5a34516262d7489e183311a1 Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Tue, 1 Nov 2011 10:37:05 +0000 Subject: [PATCH 06/35] arm/dt: tegra: add dts file for paz00 This adds a dts file for paz00. As a side effect, this also enables the embedded controller which controls the keyboard, touchpad, power, leds, and some other functions. Cc: Grant Likely Signed-off-by: Marc Dietrich Acked-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-paz00.dts | 82 +++++++++++++++++++++++++++++++ arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/Makefile.boot | 1 + arch/arm/mach-tegra/board-dt.c | 3 ++ 4 files changed, 87 insertions(+) create mode 100644 arch/arm/boot/dts/tegra-paz00.dts diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts new file mode 100644 index 000000000000..15a949f192ff --- /dev/null +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -0,0 +1,82 @@ +/dts-v1/; + +/memreserve/ 0x1c000000 0x04000000; +/include/ "tegra20.dtsi" + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/mmcblk0p1"; + }; + + memory@0 { + reg = <0x00000000 0x20000000>; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "disable"; + }; + + nvec@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,nvec"; + reg = <0x7000C500 0x100>; + interrupts = <124>; + clock-frequency = <80000>; + request-gpios = <&gpio 170 0>; + slave-addr = <138>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + cd-gpios = <&gpio 173 0>; /* gpio PV5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + support-8bit; + }; +}; diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 565bb2253529..c9ec38e82991 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-dt.o obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-paz00-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-trimslice-pinmux.o obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 9f177a466b83..cf51a000d400 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -3,6 +3,7 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb +dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index e6b3953a62b9..03ccaf1380c1 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -46,6 +46,7 @@ #include "devices.h" void harmony_pinmux_init(void); +void paz00_pinmux_init(void); void seaboard_pinmux_init(void); void trimslice_pinmux_init(void); void ventana_pinmux_init(void); @@ -96,6 +97,7 @@ static struct { } pinmux_configs[] = { { "compulab,trimslice", trimslice_pinmux_init }, { "nvidia,harmony", harmony_pinmux_init }, + { "compal,paz00", paz00_pinmux_init }, { "nvidia,seaboard", seaboard_pinmux_init }, { "nvidia,ventana", ventana_pinmux_init }, }; @@ -133,6 +135,7 @@ static void __init tegra_dt_init(void) static const char * tegra_dt_board_compat[] = { "compulab,trimslice", "nvidia,harmony", + "compal,paz00", "nvidia,seaboard", "nvidia,ventana", NULL From f110164ed68e0a039aff0378d66de157c3816aba Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 7 Dec 2011 15:13:40 -0700 Subject: [PATCH 07/35] arm/tegra: board-dt: Fix AUXDATA typo Fix the address of the I2S2 controller in the AUXDATA table. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/board-dt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index 03ccaf1380c1..574e2e7ac930 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -61,7 +61,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL), OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", &tegra_ehci1_device.dev.platform_data), From 586187e22ddc87e95f8ac93f1a1b2a629c983aaf Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 7 Dec 2011 15:13:42 -0700 Subject: [PATCH 08/35] arm/tegra: board-dt: Enable audio-related clocks Certain clocks are required for core audio functionality. Set up the appropriate parenting relationships, and enable clocks that must be on permanently. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/board-dt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index 574e2e7ac930..ba27c13e44e0 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -78,6 +78,11 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "usbd", "clk_m", 12000000, false }, { "usb2", "clk_m", 12000000, false }, { "usb3", "clk_m", 12000000, false }, + { "pll_a", "pll_p_out1", 56448000, true }, + { "pll_a_out0", "pll_a", 11289600, true }, + { "cdev1", NULL, 0, true }, + { "i2s1", "pll_a_out0", 11289600, false}, + { "i2s2", "pll_a_out0", 11289600, false}, { NULL, NULL, 0, 0}, }; From 5a85426506d7593695380dddd92f01f79b2bca4e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 Nov 2011 14:44:07 -0700 Subject: [PATCH 09/35] arm/dt: tegra: Remove /memreserve/ from device-tree files There are no drivers in the kernel at present which can make use of the memory reserved by /memreserve/, so there is no point reserving it. Remove /memreserve/ to allow the user more memory. It's also unclear whether any future driver would actually require /memreserve/, or allocate memory through some other mechanism. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-harmony.dts | 1 - arch/arm/boot/dts/tegra-paz00.dts | 1 - arch/arm/boot/dts/tegra-seaboard.dts | 1 - arch/arm/boot/dts/tegra-trimslice.dts | 1 - arch/arm/boot/dts/tegra-ventana.dts | 1 - 5 files changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index 0e225b86b652..a80232443b7f 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -1,6 +1,5 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 15a949f192ff..1cd0cfe9e3d0 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -1,6 +1,5 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index 88c682a26cb2..60724e4183b4 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -1,6 +1,5 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index d3d0d205a474..95117d31fee3 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -1,6 +1,5 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 3f9abd6b6964..2af12fa76eef 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -1,6 +1,5 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { From 492f204da87ccfef508d5fff63873bda37d4363b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 Nov 2011 14:44:08 -0700 Subject: [PATCH 10/35] arm/dt: tegra: Remove /chosen node The command-lines present in the existing /chosen node are not necessarily correct for all users. Ideally, we should simply use the command-line supplied by the boot-loader. In fact, using the boot-loader's cmdline is quite easy; either the bootloader fully supports DT, in which case it can modify the DT passed to the kernel to include its command-line, or CONFIG_APPENDED_DTB can be used in conjunction with CONFIG_ARM_ATAG_DTB_COMPAT, and the kernel will substitute the bootloader's command-line into the DT. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-harmony.dts | 4 ---- arch/arm/boot/dts/tegra-paz00.dts | 4 ---- arch/arm/boot/dts/tegra-seaboard.dts | 4 ---- arch/arm/boot/dts/tegra-trimslice.dts | 4 ---- arch/arm/boot/dts/tegra-ventana.dts | 4 ---- 5 files changed, 20 deletions(-) diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index a80232443b7f..ca6fa1084c9d 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -6,10 +6,6 @@ model = "NVIDIA Tegra2 Harmony evaluation board"; compatible = "nvidia,harmony", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait"; - }; - memory@0 { reg = < 0x00000000 0x40000000 >; }; diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 1cd0cfe9e3d0..4f6a8aa0a757 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -6,10 +6,6 @@ model = "Toshiba AC100 / Dynabook AZ"; compatible = "compal,paz00", "nvidia,tegra20"; - chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/mmcblk0p1"; - }; - memory@0 { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index 60724e4183b4..d1ada26b7b90 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -6,10 +6,6 @@ model = "NVIDIA Seaboard"; compatible = "nvidia,seaboard", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; - }; - memory { device_type = "memory"; reg = < 0x00000000 0x40000000 >; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index 95117d31fee3..cf8e5617f3bd 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -6,10 +6,6 @@ model = "Compulab TrimSlice board"; compatible = "compulab,trimslice", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p1 rw rootwait"; - }; - memory@0 { reg = < 0x00000000 0x40000000 >; }; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 2af12fa76eef..1c0948541806 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -6,10 +6,6 @@ model = "NVIDIA Tegra2 Ventana evaluation board"; compatible = "nvidia,ventana", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init"; - }; - memory { reg = < 0x00000000 0x40000000 >; }; From 88950f3b6d0f49b6b5a2f68bd1f67406c2c73922 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 Nov 2011 14:44:09 -0700 Subject: [PATCH 11/35] arm/dt: tegra: Fix I2C nodes to match board files With board files, all I2C busses run at 400KHz. Fix the device-tree to be consistent with this. It's possible this is incorrect, but at least it keeps the board files and device-tree consistent. Also, disable any I2C controllers that the board files don't register, also for consistency. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-seaboard.dts | 16 ++++++++++++++++ arch/arm/boot/dts/tegra-trimslice.dts | 4 ++++ arch/arm/boot/dts/tegra-ventana.dts | 16 ++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index d1ada26b7b90..92da1f1ed3a3 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -11,6 +11,22 @@ reg = < 0x00000000 0x40000000 >; }; + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index cf8e5617f3bd..b1aaa45407d4 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -22,6 +22,10 @@ clock-frequency = <400000>; }; + i2c@7000d000 { + status = "disable"; + }; + serial@70006000 { clock-frequency = < 216000000 >; }; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 1c0948541806..0f14ee373e76 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -10,6 +10,22 @@ reg = < 0x00000000 0x40000000 >; }; + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; From 31c1ec9282d28f4eecb5f2e431f67accdf420ac2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 Nov 2011 14:44:10 -0700 Subject: [PATCH 12/35] arm/dt: tegra: Fix serial nodes to match board files Mark any serial ports that aren't registered by the board files as disabled in the device-tree files. In practice, none of the now-disabled ports ended up succeeding device probing because of the missing clock-frequency property. However, explicitly marking the devices disabled has the advantage of squashing the dev_warn() the failed probe causes, and documenting that we intend the port not to be used, rather than accidentally left out the property. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-harmony.dts | 16 ++++++++++++++++ arch/arm/boot/dts/tegra-seaboard.dts | 16 ++++++++++++++++ arch/arm/boot/dts/tegra-trimslice.dts | 16 ++++++++++++++++ arch/arm/boot/dts/tegra-ventana.dts | 16 ++++++++++++++++ 4 files changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index ca6fa1084c9d..ac179a05cfe3 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -47,10 +47,26 @@ ext-mic-en-gpios = <&gpio 185 0>; }; + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + sdhci@c8000200 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index 92da1f1ed3a3..cbb2f085ac23 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -27,10 +27,26 @@ clock-frequency = <400000>; }; + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + sdhci@c8000400 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index b1aaa45407d4..6060ce0ae77c 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -30,6 +30,22 @@ clock-frequency = < 216000000 >; }; + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + sdhci@c8000600 { cd-gpios = <&gpio 121 0>; wp-gpios = <&gpio 122 0>; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 0f14ee373e76..5ac0aa300fe0 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -26,10 +26,26 @@ clock-frequency = <400000>; }; + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + sdhci@c8000400 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ From 1292c129597ce42a75d9e97cd312c3242e10a6f3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 Nov 2011 14:44:11 -0700 Subject: [PATCH 13/35] arm/dt: tegra: Fix SDHCI nodes to match board files Mark any SDHCI controllers that aren't registered by the board files as disabled in the device-tree files. In practice, these controllers: * Have nothing hooked up to them at all, or * For ports intended for SDIO usage, the drivers for anything that might be attached are not in the device-tree yet. If/when drivers appear, the SD/MMC port can be re-enabled. The only possible exception is TrimSlice's mico SD slot, but that wasn't enabled in the board files before anyway, and doesn't work when all the SDHCI controllers are enabled anyway. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-harmony.dts | 8 ++++++++ arch/arm/boot/dts/tegra-seaboard.dts | 8 ++++++++ arch/arm/boot/dts/tegra-trimslice.dts | 12 ++++++++++++ arch/arm/boot/dts/tegra-ventana.dts | 8 ++++++++ 4 files changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index ac179a05cfe3..80afa1b70b80 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -67,12 +67,20 @@ status = "disable"; }; + sdhci@c8000000 { + status = "disable"; + }; + sdhci@c8000200 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ }; + sdhci@c8000400 { + status = "disable"; + }; + sdhci@c8000600 { cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index cbb2f085ac23..f552bcc04412 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -47,6 +47,14 @@ status = "disable"; }; + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + sdhci@c8000400 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts index 6060ce0ae77c..3b3ee7db99f3 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -46,6 +46,18 @@ status = "disable"; }; + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + sdhci@c8000600 { cd-gpios = <&gpio 121 0>; wp-gpios = <&gpio 122 0>; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 5ac0aa300fe0..c7d3b87f29df 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -46,6 +46,14 @@ status = "disable"; }; + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + sdhci@c8000400 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ From 0d4f74792e2946cb2ef40a1673851eda1041358c Mon Sep 17 00:00:00 2001 From: "pdeschrijver@nvidia.com" Date: Tue, 29 Nov 2011 18:29:19 -0700 Subject: [PATCH 14/35] arm/tegra: convert tegra20 to GIC devicetree binding Convert tegra20 IRQ intialization to the GIC devicetree binding. Modify the interrupt definitions in the dts files according to Documentation/devicetree/bindings/arm/gic.txt v3 (swarren): * Moved of_irq_init() call into board-dt.c to avoid ifdef'ing it. - Even with a dummy replacement if !CONFIG_OF, the reference from tegra_dt_irq_match[] to gic_of_init() would still have to be ifdef'd - It's plausible that tegra_dt_irq_match[] may need to contain more entries in the future, and defining what they are seems more suitable for board-dt.c than irq.c v2 (swarren): * Removed some stale GIC init code from board-dt.c * Undid some accidental 0x -> 0x0 search/replace. Signed-off-by: Peter De Schrijver Acked-by: Rob Herring Signed-off-by: Stephen Warren [olof: added include of for compile to pass] Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-paz00.dts | 2 +- arch/arm/boot/dts/tegra20.dtsi | 48 +++++++++++++++++-------------- arch/arm/mach-tegra/board-dt.c | 25 ++++++++-------- arch/arm/mach-tegra/irq.c | 10 +++++-- 4 files changed, 49 insertions(+), 36 deletions(-) diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index 4f6a8aa0a757..1a1d7023b69b 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -27,7 +27,7 @@ #size-cells = <0>; compatible = "nvidia,nvec"; reg = <0x7000C500 0x100>; - interrupts = <124>; + interrupts = <0 92 0x04>; clock-frequency = <80000>; request-gpios = <&gpio 170 0>; slave-addr = <138>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 04068dd49286..660c8ad537c0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -5,9 +5,9 @@ interrupt-parent = <&intc>; intc: interrupt-controller@50041000 { - compatible = "nvidia,tegra20-gic"; + compatible = "arm,cortex-a9-gic"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <3>; reg = < 0x50041000 0x1000 >, < 0x50040100 0x0100 >; }; @@ -17,7 +17,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C000 0x100>; - interrupts = < 70 >; + interrupts = < 0 38 0x04 >; }; i2c@7000c400 { @@ -25,7 +25,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C400 0x100>; - interrupts = < 116 >; + interrupts = < 0 84 0x04 >; }; i2c@7000c500 { @@ -33,7 +33,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C500 0x100>; - interrupts = < 124 >; + interrupts = < 0 92 0x04 >; }; i2c@7000d000 { @@ -41,20 +41,20 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000D000 0x200>; - interrupts = < 85 >; + interrupts = < 0 53 0x04 >; }; i2s@70002800 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; - interrupts = < 45 >; + interrupts = < 0 13 0x04 >; dma-channel = < 2 >; }; i2s@70002a00 { compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; - interrupts = < 35 >; + interrupts = < 0 3 0x04 >; dma-channel = < 1 >; }; @@ -66,7 +66,13 @@ gpio: gpio@6000d000 { compatible = "nvidia,tegra20-gpio"; reg = < 0x6000d000 0x1000 >; - interrupts = < 64 65 66 67 87 119 121 >; + interrupts = < 0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 >; #gpio-cells = <2>; gpio-controller; }; @@ -83,79 +89,79 @@ compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = < 68 >; + interrupts = < 0 36 0x04 >; }; serial@70006040 { compatible = "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = < 69 >; + interrupts = < 0 37 0x04 >; }; serial@70006200 { compatible = "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = < 78 >; + interrupts = < 0 46 0x04 >; }; serial@70006300 { compatible = "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = < 122 >; + interrupts = < 0 90 0x04 >; }; serial@70006400 { compatible = "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = < 123 >; + interrupts = < 0 91 0x04 >; }; sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; - interrupts = < 46 >; + interrupts = < 0 14 0x04 >; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; - interrupts = < 47 >; + interrupts = < 0 15 0x04 >; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; - interrupts = < 51 >; + interrupts = < 0 19 0x04 >; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; - interrupts = < 63 >; + interrupts = < 0 31 0x04 >; }; usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; - interrupts = < 52 >; + interrupts = < 0 20 0x04 >; phy_type = "utmi"; }; usb@c5004000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5004000 0x4000>; - interrupts = < 53 >; + interrupts = < 0 21 0x04 >; phy_type = "ulpi"; }; usb@c5008000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5008000 0x4000>; - interrupts = < 129 >; + interrupts = < 0 97 0x04 >; phy_type = "utmi"; }; }; diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index ba27c13e44e0..2fa599da7deb 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -51,6 +52,17 @@ void seaboard_pinmux_init(void); void trimslice_pinmux_init(void); void ventana_pinmux_init(void); +static const struct of_device_id tegra_dt_irq_match[] __initconst = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, + { } +}; + +void __init tegra_dt_init_irq(void) +{ + tegra_init_irq(); + of_irq_init(tegra_dt_irq_match); +} + struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), @@ -91,11 +103,6 @@ static struct of_device_id tegra_dt_match_table[] __initdata = { {} }; -static struct of_device_id tegra_dt_gic_match[] __initdata = { - { .compatible = "nvidia,tegra20-gic", }, - {} -}; - static struct { char *machine; void (*init)(void); @@ -109,14 +116,8 @@ static struct { static void __init tegra_dt_init(void) { - struct device_node *node; int i; - node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match, - TEGRA_ARM_INT_DIST_BASE); - if (node) - irq_domain_add_simple(node, INT_GIC_BASE); - tegra_clk_init_from_table(tegra_dt_clk_init_table); /* @@ -149,7 +150,7 @@ static const char * tegra_dt_board_compat[] = { DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)") .map_io = tegra_map_common_io, .init_early = tegra_init_early, - .init_irq = tegra_init_irq, + .init_irq = tegra_dt_init_irq, .timer = &tegra_timer, .init_machine = tegra_dt_init, .dt_compat = tegra_dt_board_compat, diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 4956c3cea731..004b0fdf0d76 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -21,6 +21,7 @@ #include #include #include +#include #include @@ -129,6 +130,11 @@ void __init tegra_init_irq(void) gic_arch_extn.irq_unmask = tegra_unmask; gic_arch_extn.irq_retrigger = tegra_retrigger; - gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), - IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); + /* + * Check if there is a devicetree present, since the GIC will be + * initialized elsewhere under DT. + */ + if (!of_have_populated_dt()) + gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), + IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); } From c3e00a0eff4c05717915ac7a8e4646db3882aebf Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:13 +0200 Subject: [PATCH 15/35] arm/tegra: initial device tree for tegra30 This patch adds the initial device tree for tegra30 Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- .../devicetree/bindings/arm/tegra.txt | 14 ++ arch/arm/boot/dts/tegra30.dtsi | 127 ++++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra.txt create mode 100644 arch/arm/boot/dts/tegra30.dtsi diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt new file mode 100644 index 000000000000..6e69d2e5e766 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -0,0 +1,14 @@ +NVIDIA Tegra device tree bindings +------------------------------------------- + +Boards with the tegra20 SoC shall have the following properties: + +Required root node property: + +compatible = "nvidia,tegra20"; + +Boards with the tegra30 SoC shall have the following properties: + +Required root node property: + +compatible = "nvidia,tegra30"; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi new file mode 100644 index 000000000000..ee7db9892e02 --- /dev/null +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -0,0 +1,127 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra30"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 0 38 0x04 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 0 84 0x04 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 0 92 0x04 >; + }; + + i2c@7000c700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = < 0 120 0x04 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x100>; + interrupts = < 0 53 0x04 >; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >; + #gpio-cells = <2>; + gpio-controller; + }; + + serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 0 36 0x04 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 0 37 0x04 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 0 46 0x04 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 0 90 0x04 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 0 91 0x04 >; + }; + + sdhci@78000000 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000000 0x200>; + interrupts = < 0 14 0x04 >; + }; + + sdhci@78000200 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000200 0x200>; + interrupts = < 0 15 0x04 >; + }; + + sdhci@78000400 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000400 0x200>; + interrupts = < 0 19 0x04 >; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000600 0x200>; + interrupts = < 0 31 0x04 >; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra30-pinmux"; + reg = < 0x70000868 0xd0 /* Pad control registers */ + 0x70003000 0x3e0 >; /* Mux registers */ + }; +}; From 2d85b5d8e1f45bc19ba28d6bce2eaae2ca32f9ac Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 26 Oct 2011 11:41:41 +0300 Subject: [PATCH 16/35] arm/tegra: clk_get should not be fatal The timer and rtc-timer clocks aren't gated by default, so there is no reason to crash the system if the dummy enable call failed. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/timer.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index e2272d263a83..2f1df471c932 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -186,16 +186,20 @@ static void __init tegra_init_timer(void) int ret; clk = clk_get_sys("timer", NULL); - BUG_ON(IS_ERR(clk)); - clk_enable(clk); + if (IS_ERR(clk)) + pr_warn("Unable to get timer clock\n"); + else + clk_enable(clk); /* * rtc registers are used by read_persistent_clock, keep the rtc clock * enabled */ clk = clk_get_sys("rtc-tegra", NULL); - BUG_ON(IS_ERR(clk)); - clk_enable(clk); + if (IS_ERR(clk)) + pr_warn("Unable to get rtc-tegra clock\n"); + else + clk_enable(clk); #ifdef CONFIG_HAVE_ARM_TWD twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); From b2bbbc4d5bfde68d4a2b45ee8592d012826ffa70 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:14 +0200 Subject: [PATCH 17/35] arm/tegra: cleanup tegra20 support * add a dependency to ARCH_TEGRA_2x_SOC in Kconfig to all tegra20 based boards and TEGRA_PCI * make powergating dependent on ARCH_TEGRA_2x_SOC * remove dependency on ARCH_TEGRA_2x_SOC for clock.c Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/Kconfig | 8 ++++++++ arch/arm/mach-tegra/Makefile | 3 +-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 91aff7cb8284..2b1d49b93ef4 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -21,18 +21,21 @@ endchoice config TEGRA_PCI bool "PCI Express support" + depends on ARCH_TEGRA_2x_SOC select PCI comment "Tegra board type" config MACH_HARMONY bool "Harmony board" + depends on ARCH_TEGRA_2x_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Harmony development platform config MACH_KAEN bool "Kaen board" + depends on ARCH_TEGRA_2x_SOC select MACH_SEABOARD select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help @@ -40,11 +43,13 @@ config MACH_KAEN config MACH_PAZ00 bool "Paz00 board" + depends on ARCH_TEGRA_2x_SOC help Support for the Toshiba AC100/Dynabook AZ netbook config MACH_SEABOARD bool "Seaboard board" + depends on ARCH_TEGRA_2x_SOC select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Seaboard development platform. It will @@ -59,18 +64,21 @@ config MACH_TEGRA_DT config MACH_TRIMSLICE bool "TrimSlice board" + depends on ARCH_TEGRA_2x_SOC select TEGRA_PCI help Support for CompuLab TrimSlice platform config MACH_WARIO bool "Wario board" + depends on ARCH_TEGRA_2x_SOC select MACH_SEABOARD help Support for the Wario version of Seaboard config MACH_VENTANA bool "Ventana board" + depends on ARCH_TEGRA_2x_SOC select MACH_TEGRA_DT help Support for the nVidia Ventana development platform diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index c9ec38e82991..26ff456ca0db 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -5,9 +5,8 @@ obj-y += irq.o obj-y += clock.o obj-y += timer.o obj-y += pinmux.o -obj-y += powergate.o obj-y += fuse.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o From 742face03f57727b5a86d0df631e47a1ef0498d2 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:15 +0200 Subject: [PATCH 18/35] arm/tegra: prepare clock code for multiple tegra variants Rework the tegra20 clock code to support multiple tegra variants : * remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This functionality should be in clock.c. * remove tegra_sdmmc_tap_delay and export tegra2_sdmmc_tap_delay directly. This feature is handled inside the sdmmc block from tegra30 onwards. So there is no need for support in the clock code beyond tegra20. There are no in tree users of this function. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/clock.c | 20 ++++---------------- arch/arm/mach-tegra/clock.h | 3 --- arch/arm/mach-tegra/include/mach/clk.h | 2 +- arch/arm/mach-tegra/tegra2_clocks.c | 17 +++++------------ 4 files changed, 10 insertions(+), 32 deletions(-) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index f8d41ffc0ca9..a8f359d8ae17 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -387,13 +387,15 @@ EXPORT_SYMBOL(tegra_clk_init_from_table); void tegra_periph_reset_deassert(struct clk *c) { - tegra2_periph_reset_deassert(c); + BUG_ON(!c->ops->reset); + c->ops->reset(c, false); } EXPORT_SYMBOL(tegra_periph_reset_deassert); void tegra_periph_reset_assert(struct clk *c) { - tegra2_periph_reset_assert(c); + BUG_ON(!c->ops->reset); + c->ops->reset(c, true); } EXPORT_SYMBOL(tegra_periph_reset_assert); @@ -402,20 +404,6 @@ void __init tegra_init_clock(void) tegra2_init_clocks(); } -/* - * The SDMMC controllers have extra bits in the clock source register that - * adjust the delay between the clock and data to compenstate for delays - * on the PCB. - */ -void tegra_sdmmc_tap_delay(struct clk *c, int delay) -{ - unsigned long flags; - - spin_lock_irqsave(&c->spinlock, flags); - tegra2_sdmmc_tap_delay(c, delay); - spin_unlock_irqrestore(&c->spinlock, flags); -} - #ifdef CONFIG_DEBUG_FS static int __clk_lock_all_spinlocks(void) diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 688316abc64e..8c18e81a9f56 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -146,8 +146,6 @@ struct tegra_clk_init_table { }; void tegra2_init_clocks(void); -void tegra2_periph_reset_deassert(struct clk *c); -void tegra2_periph_reset_assert(struct clk *c); void clk_init(struct clk *clk); struct clk *tegra_get_clock_by_name(const char *name); unsigned long clk_measure_input_freq(void); @@ -155,6 +153,5 @@ int clk_reparent(struct clk *c, struct clk *parent); void tegra_clk_init_from_table(struct tegra_clk_init_table *table); unsigned long clk_get_rate_locked(struct clk *c); int clk_set_rate_locked(struct clk *c, unsigned long rate); -void tegra2_sdmmc_tap_delay(struct clk *c, int delay); #endif diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h index c8baf8f80d23..fc3ecb66de08 100644 --- a/arch/arm/mach-tegra/include/mach/clk.h +++ b/arch/arm/mach-tegra/include/mach/clk.h @@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c); void tegra_periph_reset_assert(struct clk *c); unsigned long clk_get_rate_all_locked(struct clk *c); -void tegra_sdmmc_tap_delay(struct clk *c, int delay); +void tegra2_sdmmc_tap_delay(struct clk *c, int delay); #endif diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 371869d8ea01..c78abab86253 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = { .disable = tegra2_clk_m_disable, }; -void tegra2_periph_reset_assert(struct clk *c) -{ - BUG_ON(!c->ops->reset); - c->ops->reset(c, true); -} - -void tegra2_periph_reset_deassert(struct clk *c) -{ - BUG_ON(!c->ops->reset); - c->ops->reset(c, false); -} - /* super clock functions */ /* "super clocks" on tegra have two-stage muxes and a clock skipping * super divider. We will ignore the clock skipping divider, since we @@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = { void tegra2_sdmmc_tap_delay(struct clk *c, int delay) { u32 reg; + unsigned long flags; + + spin_lock_irqsave(&c->spinlock, flags); delay = clamp(delay, 0, 15); reg = clk_readl(c->reg); @@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay) reg |= SDMMC_CLK_INT_FB_SEL; reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT; clk_writel(reg, c->reg); + + spin_unlock_irqrestore(&c->spinlock, flags); } /* External memory controller clock ops */ From 8e4fab2c39b2db774e41553646788599cfdac9df Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:16 +0200 Subject: [PATCH 19/35] arm/tegra: don't export clk_measure_input_freq don't export clk_measure_input_freq as its functionality is also available using clk_get_rate(). Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/clock.h | 1 - arch/arm/mach-tegra/tegra2_clocks.c | 2 +- arch/arm/mach-tegra/timer.c | 12 ++++++++---- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 8c18e81a9f56..5c44106616c5 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -148,7 +148,6 @@ struct tegra_clk_init_table { void tegra2_init_clocks(void); void clk_init(struct clk *clk); struct clk *tegra_get_clock_by_name(const char *name); -unsigned long clk_measure_input_freq(void); int clk_reparent(struct clk *c, struct clk *parent); void tegra_clk_init_from_table(struct tegra_clk_init_table *table); unsigned long clk_get_rate_locked(struct clk *c); diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index c78abab86253..ff9e6b6c0460 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32]; #define pmc_readl(reg) \ __raw_readl(reg_pmc_base + (reg)) -unsigned long clk_measure_input_freq(void) +static unsigned long clk_measure_input_freq(void) { u32 clock_autodetect; clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 2f1df471c932..6366654b54c5 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -182,14 +182,18 @@ static struct irqaction tegra_timer_irq = { static void __init tegra_init_timer(void) { struct clk *clk; - unsigned long rate = clk_measure_input_freq(); + unsigned long rate; int ret; clk = clk_get_sys("timer", NULL); - if (IS_ERR(clk)) - pr_warn("Unable to get timer clock\n"); - else + if (IS_ERR(clk)) { + pr_warn("Unable to get timer clock." + " Assuming 12Mhz input clock.\n"); + rate = 12000000; + } else { clk_enable(clk); + rate = clk_get_rate(clk); + } /* * rtc registers are used by read_persistent_clock, keep the rtc clock From c37c07ddf26910f39cdc55df54640439d3a38083 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:17 +0200 Subject: [PATCH 20/35] arm/tegra: prepare early init for multiple tegra variants This patch splits the early init code in a common and a tegra20 specific part. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/board-dt.c | 19 ++++--------------- arch/arm/mach-tegra/board-harmony.c | 2 +- arch/arm/mach-tegra/board-paz00.c | 2 +- arch/arm/mach-tegra/board-seaboard.c | 6 +++--- arch/arm/mach-tegra/board-trimslice.c | 2 +- arch/arm/mach-tegra/board.h | 3 ++- arch/arm/mach-tegra/common.c | 27 ++++++++++++++++++++++----- 7 files changed, 34 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c index c21863d6425d..ddaa037be028 100644 --- a/arch/arm/mach-tegra/board-dt.c +++ b/arch/arm/mach-tegra/board-dt.c @@ -53,17 +53,6 @@ void seaboard_pinmux_init(void); void trimslice_pinmux_init(void); void ventana_pinmux_init(void); -static const struct of_device_id tegra_dt_irq_match[] __initconst = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, - { } -}; - -void __init tegra_dt_init_irq(void) -{ - tegra_init_irq(); - of_irq_init(tegra_dt_irq_match); -} - struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), @@ -139,7 +128,7 @@ static void __init tegra_dt_init(void) "Unknown platform! Pinmuxing not initialized\n"); } -static const char * tegra_dt_board_compat[] = { +static const char *tegra20_dt_board_compat[] = { "compulab,trimslice", "nvidia,harmony", "compal,paz00", @@ -148,12 +137,12 @@ static const char * tegra_dt_board_compat[] = { NULL }; -DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)") +DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_dt_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_dt_init, - .dt_compat = tegra_dt_board_compat, + .dt_compat = tegra20_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index fd190a8dc665..d60a0d45f2f7 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -186,7 +186,7 @@ MACHINE_START(HARMONY, "harmony") .atag_offset = 0x100, .fixup = tegra_harmony_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 0b7e1cfee70d..e68b40727e6d 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -189,7 +189,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ") .atag_offset = 0x100, .fixup = tegra_paz00_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c index 7328379b1356..b79f9ce9941c 100644 --- a/arch/arm/mach-tegra/board-seaboard.c +++ b/arch/arm/mach-tegra/board-seaboard.c @@ -283,7 +283,7 @@ static void __init tegra_wario_init(void) MACHINE_START(SEABOARD, "seaboard") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, @@ -293,7 +293,7 @@ MACHINE_END MACHINE_START(KAEN, "kaen") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, @@ -303,7 +303,7 @@ MACHINE_END MACHINE_START(WARIO, "wario") .atag_offset = 0x100, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c index 60a36a2e0be1..4a197a20be93 100644 --- a/arch/arm/mach-tegra/board-trimslice.c +++ b/arch/arm/mach-tegra/board-trimslice.c @@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice") .atag_offset = 0x100, .fixup = tegra_trimslice_fixup, .map_io = tegra_map_common_io, - .init_early = tegra_init_early, + .init_early = tegra20_init_early, .init_irq = tegra_init_irq, .handle_irq = gic_handle_irq, .timer = &tegra_timer, diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 1d14df7eb7de..fdec3ffa4455 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -25,9 +25,10 @@ void tegra_assert_system_reset(char mode, const char *cmd); -void __init tegra_init_early(void); +void __init tegra20_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); +void __init tegra_dt_init_irq(void); void __init tegra_init_clock(void); int __init tegra_pcie_init(bool init_port0, bool init_port1); diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 690b888be506..0fafb60497a5 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-harmony.c + * arch/arm/mach-tegra/common.c * * Copyright (C) 2010 Google, Inc. * @@ -21,8 +21,10 @@ #include #include #include +#include #include +#include #include #include @@ -33,6 +35,17 @@ void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; +static const struct of_device_id tegra_dt_irq_match[] __initconst = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, + { } +}; + +void __init tegra_dt_init_irq(void) +{ + tegra_init_irq(); + of_irq_init(tegra_dt_irq_match); +} + void tegra_assert_system_reset(char mode, const char *cmd) { void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); @@ -44,7 +57,8 @@ void tegra_assert_system_reset(char mode, const char *cmd) writel_relaxed(reg, reset); } -static __initdata struct tegra_clk_init_table common_clk_init_table[] = { +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, { "pll_p", "clk_m", 216000000, true }, @@ -60,6 +74,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "cpu", NULL, 0, true }, { NULL, NULL, 0, 0}, }; +#endif static void __init tegra_init_cache(void) { @@ -74,10 +89,12 @@ static void __init tegra_init_cache(void) } -void __init tegra_init_early(void) +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +void __init tegra20_init_early(void) { tegra_init_fuse(); - tegra_init_clock(); - tegra_clk_init_from_table(common_clk_init_table); + tegra2_init_clocks(); + tegra_clk_init_from_table(tegra20_clk_init_table); tegra_init_cache(); } +#endif From a2385dc502a9c7eb3a7d0b8c033c344c459a13aa Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:18 +0200 Subject: [PATCH 21/35] arm/tegra: rename board-dt.c to board-dt-tegra20.c Tegra20 based boards will be handled by the current board-dt.c file. Tegra30 based boards will be handled by a new board-dt-tegra30.c file. Hence rename the existing board-dt.c to board-dt-tegra20.c to reflect its use. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/Kconfig | 4 ++-- arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/{board-dt.c => board-dt-tegra20.c} | 0 3 files changed, 3 insertions(+), 3 deletions(-) rename arch/arm/mach-tegra/{board-dt.c => board-dt-tegra20.c} (100%) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 2b1d49b93ef4..996828d68dc0 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -57,10 +57,10 @@ config MACH_SEABOARD have large similarities with the seaboard design. config MACH_TEGRA_DT - bool "Generic Tegra board (FDT support)" + bool "Generic Tegra20 board (FDT support)" select USE_OF help - Support for generic nVidia Tegra boards using Flattened Device Tree + Support for generic NVIDIA Tegra20 boards using Flattened Device Tree config MACH_TRIMSLICE bool "TrimSlice board" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 26ff456ca0db..813af0db07c3 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -28,7 +28,7 @@ obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o obj-$(CONFIG_MACH_SEABOARD) += board-seaboard.o obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o -obj-$(CONFIG_MACH_TEGRA_DT) += board-dt.o +obj-$(CONFIG_MACH_TEGRA_DT) += board-dt-tegra20.o obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o obj-$(CONFIG_MACH_TEGRA_DT) += board-paz00-pinmux.o diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt-tegra20.c similarity index 100% rename from arch/arm/mach-tegra/board-dt.c rename to arch/arm/mach-tegra/board-dt-tegra20.c From 9bfc3f0d48c0e6aac05b02638dd0b502b522dec7 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:19 +0200 Subject: [PATCH 22/35] arm/tegra: use PMC reset Use PMC reset rather then CAR system reset as recommended by the hardware team. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/common.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 0fafb60497a5..007d34f0966f 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -48,12 +48,11 @@ void __init tegra_dt_init_irq(void) void tegra_assert_system_reset(char mode, const char *cmd) { - void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); + void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); u32 reg; - /* use *_related to avoid spinlock since caches are off */ reg = readl_relaxed(reset); - reg |= 0x04; + reg |= 0x10; writel_relaxed(reg, reset); } From 01548673fa15762137539d565767531eb4fef743 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:20 +0200 Subject: [PATCH 23/35] arm/tegra: generalize L2 cache initialization Generalize L2 cache initialization and discover L2 cache associativity at runtime. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/common.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 007d34f0966f..a5c14dc304d1 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -75,15 +75,20 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { }; #endif -static void __init tegra_init_cache(void) +static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) { #ifdef CONFIG_CACHE_L2X0 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + u32 aux_ctrl, cache_type; - writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); + writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL); - l2x0_init(p, 0x6C080001, 0x8200c3fe); + cache_type = readl(p + L2X0_CACHE_TYPE); + aux_ctrl = (cache_type & 0x700) << (17-8); + aux_ctrl |= 0x6C000001; + + l2x0_init(p, aux_ctrl, 0x8200c3fe); #endif } @@ -94,6 +99,6 @@ void __init tegra20_init_early(void) tegra_init_fuse(); tegra2_init_clocks(); tegra_clk_init_from_table(tegra20_clk_init_table); - tegra_init_cache(); + tegra_init_cache(0x331, 0x441); } #endif From 57be3bdb402afbf71b0490ccf229c3b9cf784ce1 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:21 +0200 Subject: [PATCH 24/35] arm/tegra: rename tegra20 pinmux files Rename pinmux-t2.h and pinmux-t2-tables.c to the new tegra naming. This file will be reworked somewhat in the next patch to support multiple tegra SoC types. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/board-seaboard-pinmux.c | 2 +- .../include/mach/{pinmux-t2.h => pinmux-tegra20.h} | 6 +++--- arch/arm/mach-tegra/include/mach/pinmux.h | 2 +- .../{pinmux-t2-tables.c => pinmux-tegra20-tables.c} | 5 +++-- 5 files changed, 9 insertions(+), 8 deletions(-) rename arch/arm/mach-tegra/include/mach/{pinmux-t2.h => pinmux-tegra20.h} (96%) rename arch/arm/mach-tegra/{pinmux-t2-tables.c => pinmux-tegra20-tables.c} (99%) diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 813af0db07c3..48e0c2b87b2b 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -9,7 +9,7 @@ obj-y += fuse.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c index b1c2972f62fe..f6b9c01ef0db 100644 --- a/arch/arm/mach-tegra/board-seaboard-pinmux.c +++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c @@ -19,7 +19,7 @@ #include #include -#include +#include #include "gpio-names.h" #include "board-seaboard.h" diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h similarity index 96% rename from arch/arm/mach-tegra/include/mach/pinmux-t2.h rename to arch/arm/mach-tegra/include/mach/pinmux-tegra20.h index 4c2626347263..6a40c1dbab17 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h +++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h + * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h * * Copyright (C) 2010 Google, Inc. * @@ -14,8 +14,8 @@ * */ -#ifndef __MACH_TEGRA_PINMUX_T2_H -#define __MACH_TEGRA_PINMUX_T2_H +#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H +#define __MACH_TEGRA_PINMUX_TEGRA20_H enum tegra_pingroup { TEGRA_PINGROUP_ATA = 0, diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index bb7dfdb61205..b93df9e31349 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -18,7 +18,7 @@ #define __MACH_TEGRA_PINMUX_H #if defined(CONFIG_ARCH_TEGRA_2x_SOC) -#include "pinmux-t2.h" +#include "pinmux-tegra20.h" #else #error "Undefined Tegra architecture" #endif diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c similarity index 99% rename from arch/arm/mach-tegra/pinmux-t2-tables.c rename to arch/arm/mach-tegra/pinmux-tegra20-tables.c index a0dc2bc28ed3..88642a54e3aa 100644 --- a/arch/arm/mach-tegra/pinmux-t2-tables.c +++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -1,7 +1,7 @@ /* - * linux/arch/arm/mach-tegra/pinmux-t2-tables.c + * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c * - * Common pinmux configurations for Tegra 2 SoCs + * Common pinmux configurations for Tegra20 SoCs * * Copyright (C) 2010 NVIDIA Corporation * @@ -29,6 +29,7 @@ #include #include +#include #include #define TRISTATE_REG_A 0x14 From 6996e0858cd5e7b57bf7297b641c4b6a5bd59be6 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:22 +0200 Subject: [PATCH 25/35] arm/tegra: prepare pinmux code for multiple tegra variants This patch modifies the pinmux code to be useable for multiple tegra variants. Some tegra20 specific constants will be replaced by variables which will be initialized to the appropriate value at runtime. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/board-harmony-pcie.c | 1 + arch/arm/mach-tegra/board-harmony-pinmux.c | 1 + arch/arm/mach-tegra/board-paz00-pinmux.c | 1 + arch/arm/mach-tegra/board-trimslice-pinmux.c | 1 + arch/arm/mach-tegra/include/mach/pinmux.h | 25 ++--- arch/arm/mach-tegra/pinmux-tegra20-tables.c | 15 ++- arch/arm/mach-tegra/pinmux.c | 105 +++++++++++-------- 7 files changed, 86 insertions(+), 63 deletions(-) diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index 6db7d699ef1c..bd402d0d5d06 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c @@ -23,6 +23,7 @@ #include #include +#include #include "board.h" #include "board-harmony.h" diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c index 7a4a26d5174c..b8a2485e3cb9 100644 --- a/arch/arm/mach-tegra/board-harmony-pinmux.c +++ b/arch/arm/mach-tegra/board-harmony-pinmux.c @@ -19,6 +19,7 @@ #include #include +#include #include "gpio-names.h" #include "board-harmony.h" diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c index be30e215f4b7..bc1fe58c26fb 100644 --- a/arch/arm/mach-tegra/board-paz00-pinmux.c +++ b/arch/arm/mach-tegra/board-paz00-pinmux.c @@ -19,6 +19,7 @@ #include #include +#include #include "gpio-names.h" #include "board-paz00.h" diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c index 7ab719d46da0..7331e15b73cc 100644 --- a/arch/arm/mach-tegra/board-trimslice-pinmux.c +++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c @@ -19,6 +19,7 @@ #include #include +#include #include "gpio-names.h" #include "board-trimslice.h" diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index b93df9e31349..35999ce7c9b2 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -17,12 +17,6 @@ #ifndef __MACH_TEGRA_PINMUX_H #define __MACH_TEGRA_PINMUX_H -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) -#include "pinmux-tegra20.h" -#else -#error "Undefined Tegra architecture" -#endif - enum tegra_mux_func { TEGRA_MUX_RSVD = 0x8000, TEGRA_MUX_RSVD1 = 0x8000, @@ -118,7 +112,7 @@ enum tegra_vddio { }; struct tegra_pingroup_config { - enum tegra_pingroup pingroup; + int pingroup; enum tegra_mux_func func; enum tegra_pullupdown pupd; enum tegra_tristate tristate; @@ -187,7 +181,7 @@ enum tegra_schmitt { }; struct tegra_drive_pingroup_config { - enum tegra_drive_pingroup pingroup; + int pingroup; enum tegra_hsm hsm; enum tegra_schmitt schmitt; enum tegra_drive drive; @@ -219,13 +213,15 @@ struct tegra_pingroup_desc { s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ }; -extern const struct tegra_pingroup_desc tegra_soc_pingroups[]; -extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[]; +typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max); -int tegra_pinmux_set_tristate(enum tegra_pingroup pg, - enum tegra_tristate tristate); -int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, - enum tegra_pullupdown pupd); +void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, + const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); + +int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate); +int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd); void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len); @@ -241,4 +237,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, int len, enum tegra_pullupdown pupd); #endif - diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c index 88642a54e3aa..efe6aeeea474 100644 --- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c +++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -44,7 +44,7 @@ .reg = ((r) - PINGROUP_REG_A) \ } -const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { +static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { DRIVE_PINGROUP(AO1, 0x868), DRIVE_PINGROUP(AO2, 0x86c), DRIVE_PINGROUP(AT1, 0x870), @@ -108,7 +108,7 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE .pupd_bit = pupd_b, \ } -const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { +static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), @@ -227,3 +227,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), }; + +void __init tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max) +{ + *pg = tegra_soc_pingroups; + *pg_max = TEGRA_MAX_PINGROUP; + *pgdrive = tegra_soc_drive_pingroups; + *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP; +} + diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 1d201650d7a4..45ebd8ceccca 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -33,8 +34,10 @@ #define SLWR(reg) (((reg) >> 28) & 0x3) #define SLWF(reg) (((reg) >> 30) & 0x3) -static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups; -static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups; +static const struct tegra_pingroup_desc *pingroups; +static const struct tegra_drive_pingroup_desc *drive_pingroups; +static int pingroup_max; +static int drive_max; static char *tegra_mux_names[TEGRA_MAX_MUX] = { [TEGRA_MUX_AHB_CLK] = "AHB_CLK", @@ -116,9 +119,9 @@ static const char *tegra_slew_names[TEGRA_MAX_SLEW] = { static DEFINE_SPINLOCK(mux_lock); -static const char *pingroup_name(enum tegra_pingroup pg) +static const char *pingroup_name(int pg) { - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return ""; return pingroups[pg].name; @@ -189,10 +192,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) int i; unsigned long reg; unsigned long flags; - enum tegra_pingroup pg = config->pingroup; + int pg = config->pingroup; enum tegra_mux_func func = config->func; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].mux_reg < 0) @@ -230,13 +233,12 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) return 0; } -int tegra_pinmux_set_tristate(enum tegra_pingroup pg, - enum tegra_tristate tristate) +int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate) { unsigned long reg; unsigned long flags; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].tri_reg < 0) @@ -255,13 +257,12 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg, return 0; } -int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, - enum tegra_pullupdown pupd) +int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd) { unsigned long reg; unsigned long flags; - if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + if (pg < 0 || pg >= pingroup_max) return -ERANGE; if (pingroups[pg].pupd_reg < 0) @@ -287,7 +288,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config) { - enum tegra_pingroup pingroup = config->pingroup; + int pingroup = config->pingroup; enum tegra_mux_func func = config->func; enum tegra_pullupdown pupd = config->pupd; enum tegra_tristate tristate = config->tristate; @@ -323,9 +324,9 @@ void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int l tegra_pinmux_config_pingroup(&config[i]); } -static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) +static const char *drive_pinmux_name(int pg) { - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return ""; return drive_pingroups[pg].name; @@ -352,12 +353,11 @@ static const char *slew_name(unsigned long val) return tegra_slew_names[val]; } -static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, - enum tegra_hsm hsm) +static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE) @@ -377,12 +377,11 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, - enum tegra_schmitt schmitt) +static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE) @@ -402,12 +401,11 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, - enum tegra_drive drive) +static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (drive < 0 || drive >= TEGRA_MAX_DRIVE) @@ -425,12 +423,12 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_pull_down(int pg, enum tegra_pull_strength pull_down) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL) @@ -448,12 +446,12 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_pull_up(int pg, enum tegra_pull_strength pull_up) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL) @@ -471,12 +469,12 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_slew_rising(int pg, enum tegra_slew slew_rising) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW) @@ -494,12 +492,12 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, return 0; } -static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, +static int tegra_drive_pinmux_set_slew_falling(int pg, enum tegra_slew slew_falling) { unsigned long flags; u32 reg; - if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + if (pg < 0 || pg >= drive_max) return -ERANGE; if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW) @@ -517,7 +515,7 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, return 0; } -static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup, +static void tegra_drive_pinmux_config_pingroup(int pingroup, enum tegra_hsm hsm, enum tegra_schmitt schmitt, enum tegra_drive drive, @@ -596,7 +594,7 @@ void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *conf for (i = 0; i < len; i++) { int err; c = config[i]; - if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) { + if (c.pingroup < 0 || c.pingroup >= pingroup_max) { WARN_ON(1); continue; } @@ -617,7 +615,7 @@ void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config for (i = 0; i < len; i++) { int err; if (config[i].pingroup < 0 || - config[i].pingroup >= TEGRA_MAX_PINGROUP) { + config[i].pingroup >= pingroup_max) { WARN_ON(1); continue; } @@ -635,7 +633,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf { int i; int err; - enum tegra_pingroup pingroup; + int pingroup; for (i = 0; i < len; i++) { pingroup = config[i].pingroup; @@ -654,7 +652,7 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co { int i; int err; - enum tegra_pingroup pingroup; + int pingroup; for (i = 0; i < len; i++) { pingroup = config[i].pingroup; @@ -668,11 +666,31 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co } } +static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { + { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init }, + { }, +}; + static int __devinit tegra_pinmux_probe(struct platform_device *pdev) { struct resource *res; int i; int config_bad = 0; + const struct of_device_id *match; + + match = of_match_device(tegra_pinmux_of_match, &pdev->dev); + + if (match) + ((pinmux_init)(match->data))(&pingroups, &pingroup_max, + &drive_pingroups, &drive_max); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + else + /* no device tree available, so we must be on tegra20 */ + tegra20_pinmux_init(&pingroups, &pingroup_max, + &drive_pingroups, &drive_max); +#else + pr_warn("non Tegra20 platform requires pinmux devicetree node\n"); +#endif for (i = 0; ; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); @@ -681,7 +699,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) } nbanks = i; - for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { + for (i = 0; i < pingroup_max; i++) { if (pingroups[i].tri_bank >= nbanks) { dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i); config_bad = 1; @@ -698,7 +716,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) } } - for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { + for (i = 0; i < drive_max; i++) { if (drive_pingroups[i].reg_bank >= nbanks) { dev_err(&pdev->dev, "drive pingroup %d: bad reg_bank\n", i); @@ -741,11 +759,6 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev) return 0; } -static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { - { .compatible = "nvidia,tegra20-pinmux", }, - { }, -}; - static struct platform_driver tegra_pinmux_driver = { .driver = { .name = "tegra-pinmux", @@ -779,7 +792,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) int i; int len; - for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { + for (i = 0; i < pingroup_max; i++) { unsigned long reg; unsigned long tri; unsigned long mux; @@ -850,7 +863,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) int i; int len; - for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { + for (i = 0; i < drive_max; i++) { u32 reg; seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s", From 31e37a183e79e4ba6b6640d65279fa1e8394d24a Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:23 +0200 Subject: [PATCH 26/35] arm/tegra: add new fields to struct tegra_pingroup_desc Add new fields to struct tegra_pingroup_desc to support new hardware features introduced in the tegra30 SoC. The pinmux driver won't use those fields yet, but the tegra30 pinmux tables will already provide the necessary data. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/include/mach/pinmux.h | 10 ++++++++++ arch/arm/mach-tegra/pinmux-tegra20-tables.c | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index 35999ce7c9b2..988c6c5ec9ec 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -2,6 +2,7 @@ * linux/arch/arm/mach-tegra/include/mach/pinmux.h * * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010,2011 Nvidia, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -99,6 +100,11 @@ enum tegra_tristate { TEGRA_TRI_TRISTATE = 1, }; +enum tegra_pin_io { + TEGRA_PIN_OUTPUT = 0, + TEGRA_PIN_INPUT = 1, +}; + enum tegra_vddio { TEGRA_VDDIO_BB = 0, TEGRA_VDDIO_LCD, @@ -202,6 +208,7 @@ struct tegra_pingroup_desc { int funcs[4]; int func_safe; int vddio; + enum tegra_pin_io io_default; s16 tri_bank; /* Register bank the tri_reg exists within */ s16 mux_bank; /* Register bank the mux_reg exists within */ s16 pupd_bank; /* Register bank the pupd_reg exists within */ @@ -211,6 +218,9 @@ struct tegra_pingroup_desc { s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ + s8 lock_bit; /* offset of the LOCK bit into mux register bit */ + s8 od_bit; /* offset of the OD bit into mux register bit */ + s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */ }; typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c index efe6aeeea474..0fe533573567 100644 --- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c +++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -106,6 +106,10 @@ static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MA .pupd_bank = 2, \ .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ .pupd_bit = pupd_b, \ + .lock_bit = -1, \ + .od_bit = -1, \ + .ioreset_bit = -1, \ + .io_default = -1, \ } static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { From 241682c8e0df98e710776ea09a7748938ca2578f Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:24 +0200 Subject: [PATCH 27/35] arm/tegra: pinmux tables and definitions for tegra30 Define the pinmuxing and pindrive tables for tegra30. The pinmux table defines the available functions for each pinmux group. The pindrive table defines the default pullup or pulldowns for each group. Derived from code by Scott Williams (scwilliams@nvidia.com) Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/Makefile | 1 + .../mach-tegra/include/mach/pinmux-tegra30.h | 320 +++++++++++++++ arch/arm/mach-tegra/include/mach/pinmux.h | 53 +++ arch/arm/mach-tegra/pinmux-tegra30-tables.c | 376 ++++++++++++++++++ arch/arm/mach-tegra/pinmux.c | 48 +++ 5 files changed, 798 insertions(+) create mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra30.h create mode 100644 arch/arm/mach-tegra/pinmux-tegra30-tables.c diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 48e0c2b87b2b..ced566e5cc14 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h new file mode 100644 index 000000000000..c1aee3eb2df1 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h @@ -0,0 +1,320 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h + * + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2010,2011 Nvidia, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H +#define __MACH_TEGRA_PINMUX_TEGRA30_H + +enum tegra_pingroup { + TEGRA_PINGROUP_ULPI_DATA0 = 0, + TEGRA_PINGROUP_ULPI_DATA1, + TEGRA_PINGROUP_ULPI_DATA2, + TEGRA_PINGROUP_ULPI_DATA3, + TEGRA_PINGROUP_ULPI_DATA4, + TEGRA_PINGROUP_ULPI_DATA5, + TEGRA_PINGROUP_ULPI_DATA6, + TEGRA_PINGROUP_ULPI_DATA7, + TEGRA_PINGROUP_ULPI_CLK, + TEGRA_PINGROUP_ULPI_DIR, + TEGRA_PINGROUP_ULPI_NXT, + TEGRA_PINGROUP_ULPI_STP, + TEGRA_PINGROUP_DAP3_FS, + TEGRA_PINGROUP_DAP3_DIN, + TEGRA_PINGROUP_DAP3_DOUT, + TEGRA_PINGROUP_DAP3_SCLK, + TEGRA_PINGROUP_GPIO_PV0, + TEGRA_PINGROUP_GPIO_PV1, + TEGRA_PINGROUP_SDMMC1_CLK, + TEGRA_PINGROUP_SDMMC1_CMD, + TEGRA_PINGROUP_SDMMC1_DAT3, + TEGRA_PINGROUP_SDMMC1_DAT2, + TEGRA_PINGROUP_SDMMC1_DAT1, + TEGRA_PINGROUP_SDMMC1_DAT0, + TEGRA_PINGROUP_GPIO_PV2, + TEGRA_PINGROUP_GPIO_PV3, + TEGRA_PINGROUP_CLK2_OUT, + TEGRA_PINGROUP_CLK2_REQ, + TEGRA_PINGROUP_LCD_PWR1, + TEGRA_PINGROUP_LCD_PWR2, + TEGRA_PINGROUP_LCD_SDIN, + TEGRA_PINGROUP_LCD_SDOUT, + TEGRA_PINGROUP_LCD_WR_N, + TEGRA_PINGROUP_LCD_CS0_N, + TEGRA_PINGROUP_LCD_DC0, + TEGRA_PINGROUP_LCD_SCK, + TEGRA_PINGROUP_LCD_PWR0, + TEGRA_PINGROUP_LCD_PCLK, + TEGRA_PINGROUP_LCD_DE, + TEGRA_PINGROUP_LCD_HSYNC, + TEGRA_PINGROUP_LCD_VSYNC, + TEGRA_PINGROUP_LCD_D0, + TEGRA_PINGROUP_LCD_D1, + TEGRA_PINGROUP_LCD_D2, + TEGRA_PINGROUP_LCD_D3, + TEGRA_PINGROUP_LCD_D4, + TEGRA_PINGROUP_LCD_D5, + TEGRA_PINGROUP_LCD_D6, + TEGRA_PINGROUP_LCD_D7, + TEGRA_PINGROUP_LCD_D8, + TEGRA_PINGROUP_LCD_D9, + TEGRA_PINGROUP_LCD_D10, + TEGRA_PINGROUP_LCD_D11, + TEGRA_PINGROUP_LCD_D12, + TEGRA_PINGROUP_LCD_D13, + TEGRA_PINGROUP_LCD_D14, + TEGRA_PINGROUP_LCD_D15, + TEGRA_PINGROUP_LCD_D16, + TEGRA_PINGROUP_LCD_D17, + TEGRA_PINGROUP_LCD_D18, + TEGRA_PINGROUP_LCD_D19, + TEGRA_PINGROUP_LCD_D20, + TEGRA_PINGROUP_LCD_D21, + TEGRA_PINGROUP_LCD_D22, + TEGRA_PINGROUP_LCD_D23, + TEGRA_PINGROUP_LCD_CS1_N, + TEGRA_PINGROUP_LCD_M1, + TEGRA_PINGROUP_LCD_DC1, + TEGRA_PINGROUP_HDMI_INT, + TEGRA_PINGROUP_DDC_SCL, + TEGRA_PINGROUP_DDC_SDA, + TEGRA_PINGROUP_CRT_HSYNC, + TEGRA_PINGROUP_CRT_VSYNC, + TEGRA_PINGROUP_VI_D0, + TEGRA_PINGROUP_VI_D1, + TEGRA_PINGROUP_VI_D2, + TEGRA_PINGROUP_VI_D3, + TEGRA_PINGROUP_VI_D4, + TEGRA_PINGROUP_VI_D5, + TEGRA_PINGROUP_VI_D6, + TEGRA_PINGROUP_VI_D7, + TEGRA_PINGROUP_VI_D8, + TEGRA_PINGROUP_VI_D9, + TEGRA_PINGROUP_VI_D10, + TEGRA_PINGROUP_VI_D11, + TEGRA_PINGROUP_VI_PCLK, + TEGRA_PINGROUP_VI_MCLK, + TEGRA_PINGROUP_VI_VSYNC, + TEGRA_PINGROUP_VI_HSYNC, + TEGRA_PINGROUP_UART2_RXD, + TEGRA_PINGROUP_UART2_TXD, + TEGRA_PINGROUP_UART2_RTS_N, + TEGRA_PINGROUP_UART2_CTS_N, + TEGRA_PINGROUP_UART3_TXD, + TEGRA_PINGROUP_UART3_RXD, + TEGRA_PINGROUP_UART3_CTS_N, + TEGRA_PINGROUP_UART3_RTS_N, + TEGRA_PINGROUP_GPIO_PU0, + TEGRA_PINGROUP_GPIO_PU1, + TEGRA_PINGROUP_GPIO_PU2, + TEGRA_PINGROUP_GPIO_PU3, + TEGRA_PINGROUP_GPIO_PU4, + TEGRA_PINGROUP_GPIO_PU5, + TEGRA_PINGROUP_GPIO_PU6, + TEGRA_PINGROUP_GEN1_I2C_SDA, + TEGRA_PINGROUP_GEN1_I2C_SCL, + TEGRA_PINGROUP_DAP4_FS, + TEGRA_PINGROUP_DAP4_DIN, + TEGRA_PINGROUP_DAP4_DOUT, + TEGRA_PINGROUP_DAP4_SCLK, + TEGRA_PINGROUP_CLK3_OUT, + TEGRA_PINGROUP_CLK3_REQ, + TEGRA_PINGROUP_GMI_WP_N, + TEGRA_PINGROUP_GMI_IORDY, + TEGRA_PINGROUP_GMI_WAIT, + TEGRA_PINGROUP_GMI_ADV_N, + TEGRA_PINGROUP_GMI_CLK, + TEGRA_PINGROUP_GMI_CS0_N, + TEGRA_PINGROUP_GMI_CS1_N, + TEGRA_PINGROUP_GMI_CS2_N, + TEGRA_PINGROUP_GMI_CS3_N, + TEGRA_PINGROUP_GMI_CS4_N, + TEGRA_PINGROUP_GMI_CS6_N, + TEGRA_PINGROUP_GMI_CS7_N, + TEGRA_PINGROUP_GMI_AD0, + TEGRA_PINGROUP_GMI_AD1, + TEGRA_PINGROUP_GMI_AD2, + TEGRA_PINGROUP_GMI_AD3, + TEGRA_PINGROUP_GMI_AD4, + TEGRA_PINGROUP_GMI_AD5, + TEGRA_PINGROUP_GMI_AD6, + TEGRA_PINGROUP_GMI_AD7, + TEGRA_PINGROUP_GMI_AD8, + TEGRA_PINGROUP_GMI_AD9, + TEGRA_PINGROUP_GMI_AD10, + TEGRA_PINGROUP_GMI_AD11, + TEGRA_PINGROUP_GMI_AD12, + TEGRA_PINGROUP_GMI_AD13, + TEGRA_PINGROUP_GMI_AD14, + TEGRA_PINGROUP_GMI_AD15, + TEGRA_PINGROUP_GMI_A16, + TEGRA_PINGROUP_GMI_A17, + TEGRA_PINGROUP_GMI_A18, + TEGRA_PINGROUP_GMI_A19, + TEGRA_PINGROUP_GMI_WR_N, + TEGRA_PINGROUP_GMI_OE_N, + TEGRA_PINGROUP_GMI_DQS, + TEGRA_PINGROUP_GMI_RST_N, + TEGRA_PINGROUP_GEN2_I2C_SCL, + TEGRA_PINGROUP_GEN2_I2C_SDA, + TEGRA_PINGROUP_SDMMC4_CLK, + TEGRA_PINGROUP_SDMMC4_CMD, + TEGRA_PINGROUP_SDMMC4_DAT0, + TEGRA_PINGROUP_SDMMC4_DAT1, + TEGRA_PINGROUP_SDMMC4_DAT2, + TEGRA_PINGROUP_SDMMC4_DAT3, + TEGRA_PINGROUP_SDMMC4_DAT4, + TEGRA_PINGROUP_SDMMC4_DAT5, + TEGRA_PINGROUP_SDMMC4_DAT6, + TEGRA_PINGROUP_SDMMC4_DAT7, + TEGRA_PINGROUP_SDMMC4_RST_N, + TEGRA_PINGROUP_CAM_MCLK, + TEGRA_PINGROUP_GPIO_PCC1, + TEGRA_PINGROUP_GPIO_PBB0, + TEGRA_PINGROUP_CAM_I2C_SCL, + TEGRA_PINGROUP_CAM_I2C_SDA, + TEGRA_PINGROUP_GPIO_PBB3, + TEGRA_PINGROUP_GPIO_PBB4, + TEGRA_PINGROUP_GPIO_PBB5, + TEGRA_PINGROUP_GPIO_PBB6, + TEGRA_PINGROUP_GPIO_PBB7, + TEGRA_PINGROUP_GPIO_PCC2, + TEGRA_PINGROUP_JTAG_RTCK, + TEGRA_PINGROUP_PWR_I2C_SCL, + TEGRA_PINGROUP_PWR_I2C_SDA, + TEGRA_PINGROUP_KB_ROW0, + TEGRA_PINGROUP_KB_ROW1, + TEGRA_PINGROUP_KB_ROW2, + TEGRA_PINGROUP_KB_ROW3, + TEGRA_PINGROUP_KB_ROW4, + TEGRA_PINGROUP_KB_ROW5, + TEGRA_PINGROUP_KB_ROW6, + TEGRA_PINGROUP_KB_ROW7, + TEGRA_PINGROUP_KB_ROW8, + TEGRA_PINGROUP_KB_ROW9, + TEGRA_PINGROUP_KB_ROW10, + TEGRA_PINGROUP_KB_ROW11, + TEGRA_PINGROUP_KB_ROW12, + TEGRA_PINGROUP_KB_ROW13, + TEGRA_PINGROUP_KB_ROW14, + TEGRA_PINGROUP_KB_ROW15, + TEGRA_PINGROUP_KB_COL0, + TEGRA_PINGROUP_KB_COL1, + TEGRA_PINGROUP_KB_COL2, + TEGRA_PINGROUP_KB_COL3, + TEGRA_PINGROUP_KB_COL4, + TEGRA_PINGROUP_KB_COL5, + TEGRA_PINGROUP_KB_COL6, + TEGRA_PINGROUP_KB_COL7, + TEGRA_PINGROUP_CLK_32K_OUT, + TEGRA_PINGROUP_SYS_CLK_REQ, + TEGRA_PINGROUP_CORE_PWR_REQ, + TEGRA_PINGROUP_CPU_PWR_REQ, + TEGRA_PINGROUP_PWR_INT_N, + TEGRA_PINGROUP_CLK_32K_IN, + TEGRA_PINGROUP_OWR, + TEGRA_PINGROUP_DAP1_FS, + TEGRA_PINGROUP_DAP1_DIN, + TEGRA_PINGROUP_DAP1_DOUT, + TEGRA_PINGROUP_DAP1_SCLK, + TEGRA_PINGROUP_CLK1_REQ, + TEGRA_PINGROUP_CLK1_OUT, + TEGRA_PINGROUP_SPDIF_IN, + TEGRA_PINGROUP_SPDIF_OUT, + TEGRA_PINGROUP_DAP2_FS, + TEGRA_PINGROUP_DAP2_DIN, + TEGRA_PINGROUP_DAP2_DOUT, + TEGRA_PINGROUP_DAP2_SCLK, + TEGRA_PINGROUP_SPI2_MOSI, + TEGRA_PINGROUP_SPI2_MISO, + TEGRA_PINGROUP_SPI2_CS0_N, + TEGRA_PINGROUP_SPI2_SCK, + TEGRA_PINGROUP_SPI1_MOSI, + TEGRA_PINGROUP_SPI1_SCK, + TEGRA_PINGROUP_SPI1_CS0_N, + TEGRA_PINGROUP_SPI1_MISO, + TEGRA_PINGROUP_SPI2_CS1_N, + TEGRA_PINGROUP_SPI2_CS2_N, + TEGRA_PINGROUP_SDMMC3_CLK, + TEGRA_PINGROUP_SDMMC3_CMD, + TEGRA_PINGROUP_SDMMC3_DAT0, + TEGRA_PINGROUP_SDMMC3_DAT1, + TEGRA_PINGROUP_SDMMC3_DAT2, + TEGRA_PINGROUP_SDMMC3_DAT3, + TEGRA_PINGROUP_SDMMC3_DAT4, + TEGRA_PINGROUP_SDMMC3_DAT5, + TEGRA_PINGROUP_SDMMC3_DAT6, + TEGRA_PINGROUP_SDMMC3_DAT7, + TEGRA_PINGROUP_PEX_L0_PRSNT_N, + TEGRA_PINGROUP_PEX_L0_RST_N, + TEGRA_PINGROUP_PEX_L0_CLKREQ_N, + TEGRA_PINGROUP_PEX_WAKE_N, + TEGRA_PINGROUP_PEX_L1_PRSNT_N, + TEGRA_PINGROUP_PEX_L1_RST_N, + TEGRA_PINGROUP_PEX_L1_CLKREQ_N, + TEGRA_PINGROUP_PEX_L2_PRSNT_N, + TEGRA_PINGROUP_PEX_L2_RST_N, + TEGRA_PINGROUP_PEX_L2_CLKREQ_N, + TEGRA_PINGROUP_HDMI_CEC, + TEGRA_MAX_PINGROUP, +}; + +enum tegra_drive_pingroup { + TEGRA_DRIVE_PINGROUP_AO1 = 0, + TEGRA_DRIVE_PINGROUP_AO2, + TEGRA_DRIVE_PINGROUP_AT1, + TEGRA_DRIVE_PINGROUP_AT2, + TEGRA_DRIVE_PINGROUP_AT3, + TEGRA_DRIVE_PINGROUP_AT4, + TEGRA_DRIVE_PINGROUP_AT5, + TEGRA_DRIVE_PINGROUP_CDEV1, + TEGRA_DRIVE_PINGROUP_CDEV2, + TEGRA_DRIVE_PINGROUP_CSUS, + TEGRA_DRIVE_PINGROUP_DAP1, + TEGRA_DRIVE_PINGROUP_DAP2, + TEGRA_DRIVE_PINGROUP_DAP3, + TEGRA_DRIVE_PINGROUP_DAP4, + TEGRA_DRIVE_PINGROUP_DBG, + TEGRA_DRIVE_PINGROUP_LCD1, + TEGRA_DRIVE_PINGROUP_LCD2, + TEGRA_DRIVE_PINGROUP_SDIO2, + TEGRA_DRIVE_PINGROUP_SDIO3, + TEGRA_DRIVE_PINGROUP_SPI, + TEGRA_DRIVE_PINGROUP_UAA, + TEGRA_DRIVE_PINGROUP_UAB, + TEGRA_DRIVE_PINGROUP_UART2, + TEGRA_DRIVE_PINGROUP_UART3, + TEGRA_DRIVE_PINGROUP_VI1, + TEGRA_DRIVE_PINGROUP_SDIO1, + TEGRA_DRIVE_PINGROUP_CRT, + TEGRA_DRIVE_PINGROUP_DDC, + TEGRA_DRIVE_PINGROUP_GMA, + TEGRA_DRIVE_PINGROUP_GMB, + TEGRA_DRIVE_PINGROUP_GMC, + TEGRA_DRIVE_PINGROUP_GMD, + TEGRA_DRIVE_PINGROUP_GME, + TEGRA_DRIVE_PINGROUP_GMF, + TEGRA_DRIVE_PINGROUP_GMG, + TEGRA_DRIVE_PINGROUP_GMH, + TEGRA_DRIVE_PINGROUP_OWR, + TEGRA_DRIVE_PINGROUP_UAD, + TEGRA_DRIVE_PINGROUP_GPV, + TEGRA_DRIVE_PINGROUP_DEV3, + TEGRA_DRIVE_PINGROUP_CEC, + TEGRA_MAX_DRIVE_PINGROUP, +}; + +#endif + diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index 988c6c5ec9ec..055f1792c8ff 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -24,6 +24,7 @@ enum tegra_mux_func { TEGRA_MUX_RSVD2 = 0x8001, TEGRA_MUX_RSVD3 = 0x8002, TEGRA_MUX_RSVD4 = 0x8003, + TEGRA_MUX_INVALID = 0x4000, TEGRA_MUX_NONE = -1, TEGRA_MUX_AHB_CLK, TEGRA_MUX_APB_CLK, @@ -85,6 +86,49 @@ enum tegra_mux_func { TEGRA_MUX_VI, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_MUX_XIO, + TEGRA_MUX_BLINK, + TEGRA_MUX_CEC, + TEGRA_MUX_CLK12, + TEGRA_MUX_DAP, + TEGRA_MUX_DAPSDMMC2, + TEGRA_MUX_DDR, + TEGRA_MUX_DEV3, + TEGRA_MUX_DTV, + TEGRA_MUX_VI_ALT1, + TEGRA_MUX_VI_ALT2, + TEGRA_MUX_VI_ALT3, + TEGRA_MUX_EMC_DLL, + TEGRA_MUX_EXTPERIPH1, + TEGRA_MUX_EXTPERIPH2, + TEGRA_MUX_EXTPERIPH3, + TEGRA_MUX_GMI_ALT, + TEGRA_MUX_HDA, + TEGRA_MUX_HSI, + TEGRA_MUX_I2C4, + TEGRA_MUX_I2C5, + TEGRA_MUX_I2CPWR, + TEGRA_MUX_I2S0, + TEGRA_MUX_I2S1, + TEGRA_MUX_I2S2, + TEGRA_MUX_I2S3, + TEGRA_MUX_I2S4, + TEGRA_MUX_NAND_ALT, + TEGRA_MUX_POPSDIO4, + TEGRA_MUX_POPSDMMC4, + TEGRA_MUX_PWM0, + TEGRA_MUX_PWM1, + TEGRA_MUX_PWM2, + TEGRA_MUX_PWM3, + TEGRA_MUX_SATA, + TEGRA_MUX_SPI5, + TEGRA_MUX_SPI6, + TEGRA_MUX_SYSCLK, + TEGRA_MUX_VGP1, + TEGRA_MUX_VGP2, + TEGRA_MUX_VGP3, + TEGRA_MUX_VGP4, + TEGRA_MUX_VGP5, + TEGRA_MUX_VGP6, TEGRA_MUX_SAFE, TEGRA_MAX_MUX, }; @@ -115,6 +159,12 @@ enum tegra_vddio { TEGRA_VDDIO_SYS, TEGRA_VDDIO_AUDIO, TEGRA_VDDIO_SD, + TEGRA_VDDIO_CAM, + TEGRA_VDDIO_GMI, + TEGRA_VDDIO_PEXCTL, + TEGRA_VDDIO_SDMMC1, + TEGRA_VDDIO_SDMMC3, + TEGRA_VDDIO_SDMMC4, }; struct tegra_pingroup_config { @@ -230,6 +280,9 @@ typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg, void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); +void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, + const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); + int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate); int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd); diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c new file mode 100644 index 000000000000..8b6db9a9152f --- /dev/null +++ b/arch/arm/mach-tegra/pinmux-tegra30-tables.c @@ -0,0 +1,376 @@ +/* + * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c + * + * Common pinmux configurations for Tegra30 SoCs + * + * Copyright (C) 2010,2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define PINGROUP_REG_A 0x868 +#define MUXCTL_REG_A 0x3000 + +#define DRIVE_PINGROUP(pg_name, r) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg_bank = 0, \ + .reg = ((r) - PINGROUP_REG_A) \ + } + +static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { + DRIVE_PINGROUP(AO1, 0x868), + DRIVE_PINGROUP(AO2, 0x86c), + DRIVE_PINGROUP(AT1, 0x870), + DRIVE_PINGROUP(AT2, 0x874), + DRIVE_PINGROUP(AT3, 0x878), + DRIVE_PINGROUP(AT4, 0x87c), + DRIVE_PINGROUP(AT5, 0x880), + DRIVE_PINGROUP(CDEV1, 0x884), + DRIVE_PINGROUP(CDEV2, 0x888), + DRIVE_PINGROUP(CSUS, 0x88c), + DRIVE_PINGROUP(DAP1, 0x890), + DRIVE_PINGROUP(DAP2, 0x894), + DRIVE_PINGROUP(DAP3, 0x898), + DRIVE_PINGROUP(DAP4, 0x89c), + DRIVE_PINGROUP(DBG, 0x8a0), + DRIVE_PINGROUP(LCD1, 0x8a4), + DRIVE_PINGROUP(LCD2, 0x8a8), + DRIVE_PINGROUP(SDIO2, 0x8ac), + DRIVE_PINGROUP(SDIO3, 0x8b0), + DRIVE_PINGROUP(SPI, 0x8b4), + DRIVE_PINGROUP(UAA, 0x8b8), + DRIVE_PINGROUP(UAB, 0x8bc), + DRIVE_PINGROUP(UART2, 0x8c0), + DRIVE_PINGROUP(UART3, 0x8c4), + DRIVE_PINGROUP(VI1, 0x8c8), + DRIVE_PINGROUP(SDIO1, 0x8ec), + DRIVE_PINGROUP(CRT, 0x8f8), + DRIVE_PINGROUP(DDC, 0x8fc), + DRIVE_PINGROUP(GMA, 0x900), + DRIVE_PINGROUP(GMB, 0x904), + DRIVE_PINGROUP(GMC, 0x908), + DRIVE_PINGROUP(GMD, 0x90c), + DRIVE_PINGROUP(GME, 0x910), + DRIVE_PINGROUP(GMF, 0x914), + DRIVE_PINGROUP(GMG, 0x918), + DRIVE_PINGROUP(GMH, 0x91c), + DRIVE_PINGROUP(OWR, 0x920), + DRIVE_PINGROUP(UAD, 0x924), + DRIVE_PINGROUP(GPV, 0x928), + DRIVE_PINGROUP(DEV3, 0x92c), + DRIVE_PINGROUP(CEC, 0x938), +}; + +#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \ + [TEGRA_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .vddio = TEGRA_VDDIO_ ## vdd, \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_ ## f2, \ + TEGRA_MUX_ ## f3, \ + }, \ + .func_safe = TEGRA_MUX_ ## fs, \ + .tri_bank = 1, \ + .tri_reg = ((reg) - MUXCTL_REG_A), \ + .tri_bit = 4, \ + .mux_bank = 1, \ + .mux_reg = ((reg) - MUXCTL_REG_A), \ + .mux_bit = 0, \ + .pupd_bank = 1, \ + .pupd_reg = ((reg) - MUXCTL_REG_A), \ + .pupd_bit = 2, \ + .io_default = TEGRA_PIN_ ## iod, \ + .od_bit = 6, \ + .lock_bit = 7, \ + .ioreset_bit = 8, \ + } + +static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { + /* NAME VDD f0 f1 f2 f3 fSafe io reg */ + PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000), + PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004), + PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008), + PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c), + PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010), + PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014), + PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018), + PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c), + PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020), + PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024), + PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028), + PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c), + PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030), + PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034), + PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038), + PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c), + PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040), + PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044), + PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048), + PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c), + PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050), + PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054), + PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058), + PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c), + PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060), + PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064), + PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068), + PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c), + PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070), + PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074), + PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078), + PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c), + PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080), + PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084), + PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088), + PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c), + PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090), + PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094), + PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098), + PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c), + PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0), + PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4), + PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8), + PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac), + PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0), + PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4), + PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8), + PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc), + PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0), + PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4), + PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8), + PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc), + PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0), + PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4), + PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8), + PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc), + PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0), + PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4), + PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8), + PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec), + PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0), + PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4), + PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8), + PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc), + PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100), + PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104), + PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108), + PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c), + PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110), + PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114), + PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118), + PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c), + PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120), + PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124), + PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128), + PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c), + PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130), + PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134), + PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138), + PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c), + PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140), + PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144), + PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148), + PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c), + PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150), + PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154), + PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158), + PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c), + PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160), + PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164), + PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168), + PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c), + PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170), + PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174), + PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178), + PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c), + PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180), + PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184), + PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188), + PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c), + PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190), + PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194), + PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198), + PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c), + PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0), + PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4), + PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8), + PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac), + PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0), + PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4), + PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8), + PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc), + PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0), + PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4), + PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8), + PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc), + PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0), + PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4), + PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8), + PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc), + PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0), + PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4), + PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8), + PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec), + PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0), + PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4), + PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8), + PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc), + PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200), + PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204), + PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208), + PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c), + PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210), + PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214), + PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218), + PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c), + PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220), + PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224), + PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228), + PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c), + PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230), + PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234), + PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238), + PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c), + PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240), + PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244), + PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248), + PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c), + PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250), + PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254), + PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258), + PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c), + PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260), + PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264), + PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268), + PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c), + PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270), + PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274), + PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278), + PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c), + PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280), + PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284), + PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288), + PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c), + PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290), + PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294), + PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298), + PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c), + PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0), + PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4), + PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8), + PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac), + PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0), + PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4), + PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8), + PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc), + PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0), + PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4), + PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8), + PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc), + PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0), + PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4), + PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8), + PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc), + PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0), + PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4), + PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8), + PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec), + PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0), + PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4), + PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8), + PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc), + PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300), + PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304), + PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308), + PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c), + PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310), + PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314), + PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318), + PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c), + PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320), + PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324), + PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328), + PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c), + PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330), + PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334), + PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338), + PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c), + PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340), + PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344), + PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348), + PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c), + PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350), + PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354), + PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358), + PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c), + PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360), + PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364), + PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368), + PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c), + PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370), + PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374), + PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378), + PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c), + PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380), + PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384), + PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388), + PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c), + PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390), + PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394), + PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398), + PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c), + PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0), + PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4), + PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8), + PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac), + PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0), + PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4), + PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8), + PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc), + PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0), + PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4), + PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8), + PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc), + PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0), + PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4), + PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8), + PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc), + PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0), +}; + +void __init tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, + int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, + int *pgdrive_max) +{ + *pg = tegra_soc_pingroups; + *pg_max = TEGRA_MAX_PINGROUP; + *pgdrive = tegra_soc_drive_pingroups; + *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP; +} + diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 45ebd8ceccca..ac35d2b76850 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -100,6 +100,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = { [TEGRA_MUX_VI] = "VI", [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", [TEGRA_MUX_XIO] = "XIO", + [TEGRA_MUX_BLINK] = "BLINK", + [TEGRA_MUX_CEC] = "CEC", + [TEGRA_MUX_CLK12] = "CLK12", + [TEGRA_MUX_DAP] = "DAP", + [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2", + [TEGRA_MUX_DDR] = "DDR", + [TEGRA_MUX_DEV3] = "DEV3", + [TEGRA_MUX_DTV] = "DTV", + [TEGRA_MUX_VI_ALT1] = "VI_ALT1", + [TEGRA_MUX_VI_ALT2] = "VI_ALT2", + [TEGRA_MUX_VI_ALT3] = "VI_ALT3", + [TEGRA_MUX_EMC_DLL] = "EMC_DLL", + [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1", + [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2", + [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3", + [TEGRA_MUX_GMI_ALT] = "GMI_ALT", + [TEGRA_MUX_HDA] = "HDA", + [TEGRA_MUX_HSI] = "HSI", + [TEGRA_MUX_I2C4] = "I2C4", + [TEGRA_MUX_I2C5] = "I2C5", + [TEGRA_MUX_I2CPWR] = "I2CPWR", + [TEGRA_MUX_I2S0] = "I2S0", + [TEGRA_MUX_I2S1] = "I2S1", + [TEGRA_MUX_I2S2] = "I2S2", + [TEGRA_MUX_I2S3] = "I2S3", + [TEGRA_MUX_I2S4] = "I2S4", + [TEGRA_MUX_NAND_ALT] = "NAND_ALT", + [TEGRA_MUX_POPSDIO4] = "POPSDIO4", + [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4", + [TEGRA_MUX_PWM0] = "PWM0", + [TEGRA_MUX_PWM1] = "PWM2", + [TEGRA_MUX_PWM2] = "PWM2", + [TEGRA_MUX_PWM3] = "PWM3", + [TEGRA_MUX_SATA] = "SATA", + [TEGRA_MUX_SPI5] = "SPI5", + [TEGRA_MUX_SPI6] = "SPI6", + [TEGRA_MUX_SYSCLK] = "SYSCLK", + [TEGRA_MUX_VGP1] = "VGP1", + [TEGRA_MUX_VGP2] = "VGP2", + [TEGRA_MUX_VGP3] = "VGP3", + [TEGRA_MUX_VGP4] = "VGP4", + [TEGRA_MUX_VGP5] = "VGP5", + [TEGRA_MUX_VGP6] = "VGP6", [TEGRA_MUX_SAFE] = "", }; @@ -667,7 +710,12 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co } static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { +#ifdef CONFIG_ARCH_TEGRA_2x_SOC { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init }, +#endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init }, +#endif { }, }; From 44107d8b7e7ea3e24bebed565f03befd61caf426 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:25 +0200 Subject: [PATCH 28/35] arm/tegra: implement support for tegra30 Add support for tegra30 SoC. This includes a device tree compatible type for this SoC ("nvidia,tegra30") and adds L2 cache initialization for this new SoC. The clock framework is still missing, which prevents most drivers from working. The basic IRQs are the same, so remove the dependency on CONFIG_ARCH_TEGRA_2x_SOC. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/Kconfig | 18 +++++-- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/board-dt-tegra30.c | 62 +++++++++++++++++++++++++ arch/arm/mach-tegra/board.h | 1 + arch/arm/mach-tegra/common.c | 6 +++ arch/arm/mach-tegra/include/mach/irqs.h | 2 - 6 files changed, 83 insertions(+), 7 deletions(-) create mode 100644 arch/arm/mach-tegra/board-dt-tegra30.c diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 996828d68dc0..b3d78fcd4bef 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -2,11 +2,8 @@ if ARCH_TEGRA comment "NVIDIA Tegra options" -choice - prompt "Select Tegra processor family for target system" - config ARCH_TEGRA_2x_SOC - bool "Tegra 2 family" + bool "Enable support for Tegra20 family" select CPU_V7 select ARM_GIC select ARCH_REQUIRE_GPIOLIB @@ -17,7 +14,18 @@ config ARCH_TEGRA_2x_SOC Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller -endchoice +config ARCH_TEGRA_3x_SOC + bool "Enable support for Tegra30 family" + select CPU_V7 + select ARM_GIC + select ARCH_REQUIRE_GPIOLIB + select USB_ARCH_HAS_EHCI if USB_SUPPORT + select USB_ULPI if USB_SUPPORT + select USB_ULPI_VIEWPORT if USB_SUPPORT + select USE_OF + help + Support for NVIDIA Tegra T30 processor family, based on the + ARM CortexA9MP CPU and the ARM PL310 L2 cache controller config TEGRA_PCI bool "PCI Express support" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index ced566e5cc14..d9bf7c19660e 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c new file mode 100644 index 000000000000..f44a29cfbe2b --- /dev/null +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -0,0 +1,62 @@ +/* + * arch/arm/mach-tegra/board-dt-tegra30.c + * + * NVIDIA Tegra30 device tree board support + * + * Copyright (C) 2011 NVIDIA Corporation + * + * Derived from: + * + * arch/arm/mach-tegra/board-dt-tegra20.c + * + * Copyright (C) 2010 Secret Lab Technologies, Ltd. + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "board.h" + +static struct of_device_id tegra_dt_match_table[] __initdata = { + { .compatible = "simple-bus", }, + {} +}; + +static void __init tegra30_dt_init(void) +{ + of_platform_populate(NULL, tegra_dt_match_table, + NULL, NULL); +} + +static const char *tegra30_dt_board_compat[] = { + NULL +}; + +DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)") + .map_io = tegra_map_common_io, + .init_early = tegra30_init_early, + .init_irq = tegra_dt_init_irq, + .handle_irq = gic_handle_irq, + .timer = &tegra_timer, + .init_machine = tegra30_dt_init, + .restart = tegra_assert_system_reset, + .dt_compat = tegra30_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index fdec3ffa4455..628f5a8a0d9a 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -26,6 +26,7 @@ void tegra_assert_system_reset(char mode, const char *cmd); void __init tegra20_init_early(void); +void __init tegra30_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_dt_init_irq(void); diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index a5c14dc304d1..8911e620c092 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -102,3 +102,9 @@ void __init tegra20_init_early(void) tegra_init_cache(0x331, 0x441); } #endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +void __init tegra30_init_early(void) +{ + tegra_init_cache(0x441, 0x551); +} +#endif diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h index 73265af4dda3..a2146cd6867d 100644 --- a/arch/arm/mach-tegra/include/mach/irqs.h +++ b/arch/arm/mach-tegra/include/mach/irqs.h @@ -25,7 +25,6 @@ #define IRQ_LOCALTIMER 29 -#ifdef CONFIG_ARCH_TEGRA_2x_SOC /* Primary Interrupt Controller */ #define INT_PRI_BASE (INT_GIC_BASE + 32) #define INT_TMR1 (INT_PRI_BASE + 0) @@ -178,6 +177,5 @@ #define NR_BOARD_IRQS 32 #define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) -#endif #endif From 64c4e9f8988e6974ee7cae569fa500e7e673837b Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 14 Dec 2011 17:03:26 +0200 Subject: [PATCH 29/35] arm/tegra: add support for tegra30 based board cardhu Add support for the tegra30 based cardhu development board. Cardhu is a tablet formfactor reference design for tegra30. The patch provides a device tree for the board, updates Makefile.boot to build the dtb, includes the platform in Kconfig and updates board-dt.c. Signed-off-by: Peter De Schrijver Acked-by: Stephen Warren Acked-by: Colin Cross Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra-cardhu.dts | 36 ++++++++++++++++++++++++++ arch/arm/mach-tegra/Makefile.boot | 1 + arch/arm/mach-tegra/board-dt-tegra30.c | 1 + 3 files changed, 38 insertions(+) create mode 100644 arch/arm/boot/dts/tegra-cardhu.dts diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts new file mode 100644 index 000000000000..70c41fc897d7 --- /dev/null +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = < 0x80000000 0x40000000 >; + }; + + serial@70006000 { + clock-frequency = < 408000000 >; + }; + + i2c@7000c000 { + clock-frequency = <100000>; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + }; + + i2c@7000c700 { + clock-frequency = <100000>; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + }; +}; diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index cf51a000d400..9a82094092d7 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -7,3 +7,4 @@ dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index f44a29cfbe2b..3c197e2440b7 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -47,6 +47,7 @@ static void __init tegra30_dt_init(void) } static const char *tegra30_dt_board_compat[] = { + "nvidia,cardhu", NULL }; From 256a32eacf74681631ee7d17c5863f023e3ba402 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Sat, 17 Dec 2011 20:45:27 -0800 Subject: [PATCH 30/35] arm/tegra: refresh defconfig for tegra30 Update the defconfig for tegra due to the addition of tegra30 and rename of t20/t30 options. Signed-off-by: Olof Johansson Acked-by: Stephen Warren --- arch/arm/configs/tegra_defconfig | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 195729760aeb..fd5d3041d717 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -9,9 +9,8 @@ CONFIG_RESOURCE_COUNTERS=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set # CONFIG_ELF_CORE is not set +CONFIG_EMBEDDED=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -20,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_TEGRA_2x_SOC=y +CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_MACH_HARMONY=y CONFIG_MACH_KAEN=y CONFIG_MACH_PAZ00=y @@ -78,14 +79,12 @@ CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=y -CONFIG_NET_ETHERNET=y CONFIG_R8169=y -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set CONFIG_USB_PEGASUS=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y +# CONFIG_WLAN is not set # CONFIG_INPUT is not set # CONFIG_SERIO is not set # CONFIG_VT is not set From ba4ba3b02de3b4397e3eaf7926f82ff7229bcfca Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 19 Dec 2011 11:01:57 -0700 Subject: [PATCH 31/35] arm/tegra: Fix section mismatch errors in tegra20 pinmux tegra20_pinmux_init() is called from the pinmux's probe() function, and hence should be __devinit not __init. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/pinmux-tegra20-tables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c index 0fe533573567..734add1280b7 100644 --- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c +++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c @@ -232,7 +232,7 @@ static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), }; -void __init tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, +void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max) { From ac8a494894e0e7add2fd0919d1929c21d8cf03e1 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 19 Dec 2011 11:01:58 -0700 Subject: [PATCH 32/35] arm/tegra: Fix section mismatch errors in tegra30 pinmux tegra30_pinmux_init() is called from the pinmux's probe() function, and hence should be __devinit not __init. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/pinmux-tegra30-tables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c index 8b6db9a9152f..14fc0e4c1c44 100644 --- a/arch/arm/mach-tegra/pinmux-tegra30-tables.c +++ b/arch/arm/mach-tegra/pinmux-tegra30-tables.c @@ -364,7 +364,7 @@ static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0), }; -void __init tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, +void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max) { From 229f05fdb025ff82f47221c11ee5dfa73f7e4cb2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 19 Dec 2011 12:24:03 -0700 Subject: [PATCH 33/35] arm/tegra: Delete tegra_init_clock() tegra_init_clock() is written to call tegra2_init_clocks(), which only exists if Tegra20 support is enabled. This breaks the build of a Tegra30-only kernel. tegra_init_clock() isn't actually used any more; tegra20_init_early() calls tegra2_init_clocks() directly. So, just delete this function. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/board.h | 1 - arch/arm/mach-tegra/clock.c | 5 ----- 2 files changed, 6 deletions(-) diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 628f5a8a0d9a..75d1543d77c0 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -30,7 +30,6 @@ void __init tegra30_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_dt_init_irq(void); -void __init tegra_init_clock(void); int __init tegra_pcie_init(bool init_port0, bool init_port1); extern struct sys_timer tegra_timer; diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index a8f359d8ae17..8337068a4abe 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -399,11 +399,6 @@ void tegra_periph_reset_assert(struct clk *c) } EXPORT_SYMBOL(tegra_periph_reset_assert); -void __init tegra_init_clock(void) -{ - tegra2_init_clocks(); -} - #ifdef CONFIG_DEBUG_FS static int __clk_lock_all_spinlocks(void) From 24692c0fc6ee62b1b98dfab962694ca40a3e404a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 19 Dec 2011 12:24:04 -0700 Subject: [PATCH 34/35] arm/tegra: Make MACH_TEGRA_DT depend on ARCH_TEGRA_2x_SOC Now that Tegra20 and Tegra30 device tree board files are separate, MACH_TEGRA_DT (which enables the Tegra20 device tree board file) should depend on Tegra20 support being enabled. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index b3d78fcd4bef..373652d76b90 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -66,6 +66,7 @@ config MACH_SEABOARD config MACH_TEGRA_DT bool "Generic Tegra20 board (FDT support)" + depends on ARCH_TEGRA_2x_SOC select USE_OF help Support for generic NVIDIA Tegra20 boards using Flattened Device Tree From 6cc04a4420391c3f034afe8ea6e28d75912a70a3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 19 Dec 2011 12:24:05 -0700 Subject: [PATCH 35/35] arm/tegra: Compile tegra_dt_init_irq only when CONFIG_OF This fixes a build break attempting to build a Tegra20-only kernel without device tree enabled. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 8911e620c092..72b666bd3043 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -35,6 +35,7 @@ void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; +#ifdef CONFIG_OF static const struct of_device_id tegra_dt_irq_match[] __initconst = { { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, { } @@ -45,6 +46,7 @@ void __init tegra_dt_init_irq(void) tegra_init_irq(); of_irq_init(tegra_dt_irq_match); } +#endif void tegra_assert_system_reset(char mode, const char *cmd) {