clk: mvebu: support for 98DX3236 SoC

The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.

The clock gating options are a subset of those on the Armada XP.

The core clock divider is different to the Armada XP also.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Chris Packham 2017-01-27 16:25:42 +13:00 committed by Stephen Boyd
parent 2e6f38cef8
commit e120c17a70
5 changed files with 72 additions and 0 deletions

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@ -7,6 +7,7 @@ Required properties:
- compatible : must be "marvell,armada-370-corediv-clock",
"marvell,armada-375-corediv-clock",
"marvell,armada-380-corediv-clock",
"marvell,mv98dx3236-corediv-clock",
- reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1

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@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.

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@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar)
return 250000000;
}
/* MV98DX3236 TCLK frequency is fixed to 200MHz */
static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
{
return 200000000;
}
static const u32 axp_cpu_freqs[] __initconst = {
1000000000,
1066000000,
@ -89,6 +95,12 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar)
return cpu_freq;
}
/* MV98DX3236 CLK frequency is fixed to 800MHz */
static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
{
return 800000000;
}
static const int axp_nbclk_ratios[32][2] __initconst = {
{0, 1}, {1, 2}, {2, 2}, {2, 2},
{1, 2}, {1, 2}, {1, 1}, {2, 3},
@ -158,6 +170,11 @@ static const struct coreclk_soc_desc axp_coreclks = {
.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
};
static const struct coreclk_soc_desc mv98dx3236_coreclks = {
.get_tclk_freq = mv98dx3236_get_tclk_freq,
.get_cpu_freq = mv98dx3236_get_cpu_freq,
};
/*
* Clock Gating Control
*/
@ -195,6 +212,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
{ }
};
static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
{ "ge1", NULL, 3, 0 },
{ "ge0", NULL, 4, 0 },
{ "pex00", NULL, 5, 0 },
{ "sdio", NULL, 17, 0 },
{ "xor0", NULL, 22, 0 },
{ }
};
static void __init axp_clk_init(struct device_node *np)
{
struct device_node *cgnp =
@ -206,3 +232,16 @@ static void __init axp_clk_init(struct device_node *np)
mvebu_clk_gating_setup(cgnp, axp_gating_desc);
}
CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
static void __init mv98dx3236_clk_init(struct device_node *np)
{
struct device_node *cgnp =
of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
mvebu_coreclk_setup(np, &mv98dx3236_coreclks);
if (cgnp)
mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
}
CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock",
mv98dx3236_clk_init);

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@ -71,6 +71,10 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
{ .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
};
static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
{ .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
};
#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
static int clk_corediv_is_enabled(struct clk_hw *hwclk)
@ -232,6 +236,18 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
.ratio_offset = 0x4,
};
static const struct clk_corediv_soc_desc mv98dx3236_corediv_soc = {
.descs = mv98dx3236_corediv_desc,
.ndescs = ARRAY_SIZE(mv98dx3236_corediv_desc),
.ops = {
.recalc_rate = clk_corediv_recalc_rate,
.round_rate = clk_corediv_round_rate,
.set_rate = clk_corediv_set_rate,
},
.ratio_reload = BIT(10),
.ratio_offset = 0x8,
};
static void __init
mvebu_corediv_clk_init(struct device_node *node,
const struct clk_corediv_soc_desc *soc_desc)
@ -313,3 +329,10 @@ static void __init armada380_corediv_clk_init(struct device_node *node)
}
CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
armada380_corediv_clk_init);
static void __init mv98dx3236_corediv_clk_init(struct device_node *node)
{
return mvebu_corediv_clk_init(node, &mv98dx3236_corediv_soc);
}
CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
mv98dx3236_corediv_clk_init);

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@ -245,3 +245,11 @@ cpuclk_out:
CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
of_cpu_clk_setup);
static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
{
of_clk_add_provider(node, of_clk_src_simple_get, NULL);
}
CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
of_mv98dx3236_cpu_clk_setup);