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x86, microcode: Share native MSR accessing variants 

We want to use those in AMD's early loading path too. Also, add a
native_wrmsrl variant.

Signed-off-by: Borislav Petkov <bp@suse.de>
Tested-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
This commit is contained in:
Borislav Petkov 2013-12-04 12:31:31 +01:00
parent 5aa3d718f2
commit e1b43e3f13
2 changed files with 15 additions and 10 deletions
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15
arch/x86/include/asm/microcode.h
View File

@ -1,6 +1,21 @@
#ifndef _ASM_X86_MICROCODE_H
#define _ASM_X86_MICROCODE_H
#define native_rdmsr(msr, val1, val2) \
do { \
u64 __val = native_read_msr((msr)); \
(void)((val1) = (u32)__val); \
(void)((val2) = (u32)(__val >> 32)); \
} while (0)
#define native_wrmsr(msr, low, high) \
native_write_msr(msr, low, high)
#define native_wrmsrl(msr, val) \
native_write_msr((msr), \
(u32)((u64)(val)), \
(u32)((u64)(val) >> 32))
struct cpu_signature {
unsigned int sig;
unsigned int pf;

10
arch/x86/kernel/microcode_intel_early.c
View File

@ -365,16 +365,6 @@ out:
return state;
}
#define native_rdmsr(msr, val1, val2) \
do { \
u64 __val = native_read_msr((msr)); \
(void)((val1) = (u32)__val); \
(void)((val2) = (u32)(__val >> 32)); \
} while (0)
#define native_wrmsr(msr, low, high) \
native_write_msr(msr, low, high);
static int collect_cpu_info_early(struct ucode_cpu_info *uci)
{
unsigned int val[2];