From e208f83a7aa4ebf6c0a68e814903e8aa33f9439a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 25 Jul 2007 10:11:42 +0800 Subject: [PATCH] Blackfin arch: use HI/LO macros rather than masking the bit ranges ourselves Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/head.S | 12 +++---- arch/blackfin/mach-bf537/head.S | 12 +++---- arch/blackfin/mach-bf548/head.S | 12 +++---- arch/blackfin/mach-bf561/head.S | 12 +++---- arch/blackfin/mach-common/cache.S | 8 ++--- arch/blackfin/mach-common/cacheinit.S | 4 +-- arch/blackfin/mach-common/cplbmgr.S | 52 +++++++++++++-------------- arch/blackfin/mach-common/dpmc.S | 52 +++++++++++++-------------- arch/blackfin/mach-common/lock.S | 20 +++++------ 9 files changed, 92 insertions(+), 92 deletions(-) diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 5aeffd06fe71..69da0e8b7732 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -144,8 +144,8 @@ ENTRY(__start) ssync; /* Turn off the icache */ - p0.l = (IMEM_CONTROL & 0xFFFF); - p0.h = (IMEM_CONTROL >> 16); + p0.l = LO(IMEM_CONTROL); + p0.h = HI(IMEM_CONTROL); R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; @@ -162,8 +162,8 @@ ENTRY(__start) #endif /* Turn off the dcache */ - p0.l = (DMEM_CONTROL & 0xFFFF); - p0.h = (DMEM_CONTROL >> 16); + p0.l = LO(DMEM_CONTROL); + p0.h = HI(DMEM_CONTROL); R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; @@ -417,8 +417,8 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ + p0.l = LO(EBIU_SDBCTL); + p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ r0 = mem_SDBCTL; w[p0] = r0.l; ssync; diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index d9b411adf6a7..b1d4b91b7aed 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -100,8 +100,8 @@ ENTRY(__start) R0 = R1; /* Turn off the icache */ - p0.l = (IMEM_CONTROL & 0xFFFF); - p0.h = (IMEM_CONTROL >> 16); + p0.l = LO(IMEM_CONTROL); + p0.h = HI(IMEM_CONTROL); R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; @@ -118,8 +118,8 @@ ENTRY(__start) #endif /* Turn off the dcache */ - p0.l = (DMEM_CONTROL & 0xFFFF); - p0.h = (DMEM_CONTROL >> 16); + p0.l = LO(DMEM_CONTROL); + p0.h = HI(DMEM_CONTROL); R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; @@ -436,8 +436,8 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ + p0.l = LO(EBIU_SDBCTL); + p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ r0 = mem_SDBCTL; w[p0] = r0.l; ssync; diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index e5e56df3bf46..47cd91777a3b 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S @@ -97,8 +97,8 @@ ENTRY(__stext) R0 = R1; /* Turn off the icache */ - p0.l = (IMEM_CONTROL & 0xFFFF); - p0.h = (IMEM_CONTROL >> 16); + p0.l = LO(IMEM_CONTROL); + p0.h = HI(IMEM_CONTROL); R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; @@ -106,8 +106,8 @@ ENTRY(__stext) SSYNC; /* Turn off the dcache */ - p0.l = (DMEM_CONTROL & 0xFFFF); - p0.h = (DMEM_CONTROL >> 16); + p0.l = LO(DMEM_CONTROL); + p0.h = HI(DMEM_CONTROL); R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; @@ -335,8 +335,8 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ + p0.l = LO(EBIU_SDBCTL); + p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ r0 = mem_SDBCTL; w[p0] = r0.l; ssync; diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index b1d0e54a97a9..173893429b04 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S @@ -100,8 +100,8 @@ ENTRY(__start) R0 = R1; /* Turn off the icache */ - p0.l = (IMEM_CONTROL & 0xFFFF); - p0.h = (IMEM_CONTROL >> 16); + p0.l = LO(IMEM_CONTROL); + p0.h = HI(IMEM_CONTROL); R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; @@ -117,8 +117,8 @@ ENTRY(__start) #endif /* Turn off the dcache */ - p0.l = (DMEM_CONTROL & 0xFFFF); - p0.h = (DMEM_CONTROL >> 16); + p0.l = LO(DMEM_CONTROL); + p0.h = HI(DMEM_CONTROL); R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; @@ -371,8 +371,8 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ + p0.l = LO(EBIU_SDBCTL); + p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ r0 = mem_SDBCTL; w[p0] = r0.l; ssync; diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index 7063795eb7c0..0521b1588204 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S @@ -79,8 +79,8 @@ ENTRY(_icache_invalidate) ENTRY(_invalidate_entire_icache) [--SP] = ( R7:5); - P0.L = (IMEM_CONTROL & 0xFFFF); - P0.H = (IMEM_CONTROL >> 16); + P0.L = LO(IMEM_CONTROL); + P0.H = HI(IMEM_CONTROL); R7 = [P0]; /* Clear the IMC bit , All valid bits in the instruction @@ -197,8 +197,8 @@ ENTRY(_invalidate_entire_dcache) ENTRY(_dcache_invalidate) [--SP] = ( R7:6); - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); + P0.L = LO(DMEM_CONTROL); + P0.H = HI(DMEM_CONTROL); R7 = [P0]; /* Clear the DMC[1:0] bits, All valid bits in the data diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S index 05c0c77510b2..afa0adfac6c3 100644 --- a/arch/blackfin/mach-common/cacheinit.S +++ b/arch/blackfin/mach-common/cacheinit.S @@ -43,8 +43,8 @@ ENTRY(_bfin_write_IMEM_CONTROL) /* Enable Instruction Cache */ - P0.l = (IMEM_CONTROL & 0xFFFF); - P0.h = (IMEM_CONTROL >> 16); + P0.l = LO(IMEM_CONTROL); + P0.h = HI(IMEM_CONTROL); /* Anomaly 05000125 */ CLI R1; diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S index 6c256baf087d..cef94c13f956 100644 --- a/arch/blackfin/mach-common/cplbmgr.S +++ b/arch/blackfin/mach-common/cplbmgr.S @@ -75,15 +75,15 @@ ENTRY(_cplb_mgr) * from the configuration table. */ - P4.L = (ICPLB_FAULT_ADDR & 0xFFFF); - P4.H = (ICPLB_FAULT_ADDR >> 16); + P4.L = LO(ICPLB_FAULT_ADDR); + P4.H = HI(ICPLB_FAULT_ADDR); P1 = 16; P5.L = _page_size_table; P5.H = _page_size_table; - P0.L = (ICPLB_DATA0 & 0xFFFF); - P0.H = (ICPLB_DATA0 >> 16); + P0.L = LO(ICPLB_DATA0); + P0.H = HI(ICPLB_DATA0); R4 = [P4]; /* Get faulting address*/ R6 = 64; /* Advance past the fault address, which*/ R6 = R6 + R4; /* we'll use if we find a match*/ @@ -117,13 +117,13 @@ ENTRY(_cplb_mgr) I0 = R4; /* Fault address we'll search for*/ /* set up pointers */ - P0.L = (ICPLB_DATA0 & 0xFFFF); - P0.H = (ICPLB_DATA0 >> 16); + P0.L = LO(ICPLB_DATA0); + P0.H = HI(ICPLB_DATA0); /* The replacement procedure for ICPLBs */ - P4.L = (IMEM_CONTROL & 0xFFFF); - P4.H = (IMEM_CONTROL >> 16); + P4.L = LO(IMEM_CONTROL); + P4.H = HI(IMEM_CONTROL); /* disable cplbs */ R5 = [P4]; /* Control Register*/ @@ -243,8 +243,8 @@ ENTRY(_cplb_mgr) * last entry of the table. */ - P1.L = (ICPLB_DATA15 & 0xFFFF); /* ICPLB_DATA15 */ - P1.H = (ICPLB_DATA15 >> 16); + P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */ + P1.H = HI(ICPLB_DATA15); [P1] = R2; [P1-0x100] = R4; #ifdef CONFIG_CPLB_INFO @@ -292,10 +292,10 @@ ENTRY(_cplb_mgr) * pending writes associated with the CPLB. */ - P4.L = (DCPLB_STATUS & 0xFFFF); - P4.H = (DCPLB_STATUS >> 16); - P3.L = (DCPLB_DATA0 & 0xFFFF); - P3.H = (DCPLB_DATA0 >> 16); + P4.L = LO(DCPLB_STATUS); + P4.H = HI(DCPLB_STATUS); + P3.L = LO(DCPLB_DATA0); + P3.H = HI(DCPLB_DATA0); R5 = [P4]; /* A protection violation can be caused by more than just writes @@ -355,11 +355,11 @@ ENTRY(_cplb_mgr) * config table, that covers the faulting address. */ - P1.L = (DCPLB_DATA15 & 0xFFFF); - P1.H = (DCPLB_DATA15 >> 16); + P1.L = LO(DCPLB_DATA15); + P1.H = HI(DCPLB_DATA15); - P4.L = (DCPLB_FAULT_ADDR & 0xFFFF); - P4.H = (DCPLB_FAULT_ADDR >> 16); + P4.L = LO(DCPLB_FAULT_ADDR); + P4.H = HI(DCPLB_FAULT_ADDR); R4 = [P4]; I0 = R4; @@ -368,8 +368,8 @@ ENTRY(_cplb_mgr) R6 = R1; /* Save for later*/ /* Turn off CPLBs while we work.*/ - P4.L = (DMEM_CONTROL & 0xFFFF); - P4.H = (DMEM_CONTROL >> 16); + P4.L = LO(DMEM_CONTROL); + P4.H = HI(DMEM_CONTROL); R5 = [P4]; BITCLR(R5,ENDCPLB_P); CLI R0; @@ -384,8 +384,8 @@ ENTRY(_cplb_mgr) * are no good. */ - I1.L = (DCPLB_DATA0 & 0xFFFF); - I1.H = (DCPLB_DATA0 >> 16); + I1.L = LO(DCPLB_DATA0); + I1.H = HI(DCPLB_DATA0); P1 = 2; P2 = 16; I2.L = _dcplb_preference; @@ -475,8 +475,8 @@ ENTRY(_cplb_mgr) * one space closer to the start. */ - R1.L = (DCPLB_DATA16 & 0xFFFF); /* DCPLB_DATA15 + 4 */ - R1.H = (DCPLB_DATA16 >> 16); + R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */ + R1.H = HI(DCPLB_DATA16); R0 = P0; /* If the victim happens to be in DCPLB15, @@ -549,8 +549,8 @@ ENTRY(_cplb_mgr) * if necessary. */ - P1.L = (DCPLB_DATA15 & 0xFFFF); - P1.H = (DCPLB_DATA15 >> 16); + P1.L = LO(DCPLB_DATA15); + P1.H = HI(DCPLB_DATA15); /* If the DCPLB has cache bits set, but caching hasn't * been enabled, then we want to mask off the cache-in-L1 diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S index 97cdcd6a00d4..04194dca0151 100644 --- a/arch/blackfin/mach-common/dpmc.S +++ b/arch/blackfin/mach-common/dpmc.S @@ -39,8 +39,8 @@ ENTRY(_unmask_wdog_wakeup_evt) P0.H = hi(SICA_IWR1); P0.L = lo(SICA_IWR1); #else - P0.h = (SIC_IWR >> 16); - P0.l = (SIC_IWR & 0xFFFF); + P0.h = HI(SIC_IWR); + P0.l = LO(SIC_IWR); #endif R7 = [P0]; #if defined(CONFIG_BF561) @@ -60,11 +60,11 @@ ENTRY(_unmask_wdog_wakeup_evt) */ R7 = 0x0000(z); #if defined(CONFIG_BF561) - P0.h = (WDOGA_STAT >> 16); - P0.l = (WDOGA_STAT & 0xFFFF); + P0.h = HI(WDOGA_STAT); + P0.l = LO(WDOGA_STAT); #else - P0.h = (WDOG_STAT >> 16); - P0.l = (WDOG_STAT & 0xFFFF); + P0.h = HI(WDOG_STAT); + P0.l = LO(WDOG_STAT); #endif [P0] = R7; SSYNC; @@ -73,21 +73,21 @@ ENTRY(_unmask_wdog_wakeup_evt) ENTRY(_program_wdog_timer) [--SP] = ( R7:0, P5:0 ); #if defined(CONFIG_BF561) - P0.h = (WDOGA_CNT >> 16); - P0.l = (WDOGA_CNT & 0xFFFF); + P0.h = HI(WDOGA_CNT); + P0.l = LO(WDOGA_CNT); #else - P0.h = (WDOG_CNT >> 16); - P0.l = (WDOG_CNT & 0xFFFF); + P0.h = HI(WDOG_CNT); + P0.l = LO(WDOG_CNT); #endif [P0] = R0; SSYNC; #if defined(CONFIG_BF561) - P0.h = (WDOGA_CTL >> 16); - P0.l = (WDOGA_CTL & 0xFFFF); + P0.h = HI(WDOGA_CTL); + P0.l = LO(WDOGA_CTL); #else - P0.h = (WDOG_CTL >> 16); - P0.l = (WDOG_CTL & 0xFFFF); + P0.h = HI(WDOG_CTL); + P0.l = LO(WDOG_CTL); #endif R7 = W[P0](Z); CC = BITTST(R7,1); @@ -97,11 +97,11 @@ ENTRY(_program_wdog_timer) .LSKIP_WRITE_TO_STAT: #if defined(CONFIG_BF561) - P0.h = (WDOGA_CTL >> 16); - P0.l = (WDOGA_CTL & 0xFFFF); + P0.h = HI(WDOGA_CTL); + P0.l = LO(WDOGA_CTL); #else - P0.h = (WDOG_CTL >> 16); - P0.l = (WDOG_CTL & 0xFFFF); + P0.h = HI(WDOG_CTL); + P0.l = LO(WDOG_CTL); #endif R7 = W[P0](Z); BITCLR(R7,1); /* Enable GP event */ @@ -122,11 +122,11 @@ ENTRY(_clear_wdog_wakeup_evt) [--SP] = ( R7:0, P5:0 ); #if defined(CONFIG_BF561) - P0.h = (WDOGA_CTL >> 16); - P0.l = (WDOGA_CTL & 0xFFFF); + P0.h = HI(WDOGA_CTL); + P0.l = LO(WDOGA_CTL); #else - P0.h = (WDOG_CTL >> 16); - P0.l = (WDOG_CTL & 0xFFFF); + P0.h = HI(WDOG_CTL); + P0.l = LO(WDOG_CTL); #endif R7 = 0x0AD6(Z); W[P0] = R7.L; @@ -149,11 +149,11 @@ ENTRY(_clear_wdog_wakeup_evt) ENTRY(_disable_wdog_timer) [--SP] = ( R7:0, P5:0 ); #if defined(CONFIG_BF561) - P0.h = (WDOGA_CTL >> 16); - P0.l = (WDOGA_CTL & 0xFFFF); + P0.h = HI(WDOGA_CTL); + P0.l = LO(WDOGA_CTL); #else - P0.h = (WDOG_CTL >> 16); - P0.l = (WDOG_CTL & 0xFFFF); + P0.h = HI(WDOG_CTL); + P0.l = LO(WDOG_CTL); #endif R7 = 0xAD6(Z); W[P0] = R7.L; diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S index 386ac8dda076..190edb3cdc84 100644 --- a/arch/blackfin/mach-common/lock.S +++ b/arch/blackfin/mach-common/lock.S @@ -43,12 +43,12 @@ ENTRY(_cache_grab_lock) [--SP]=( R7:0,P5:0 ); - P1.H = (IMEM_CONTROL >> 16); - P1.L = (IMEM_CONTROL & 0xFFFF); - P5.H = (ICPLB_ADDR0 >> 16); - P5.L = (ICPLB_ADDR0 & 0xFFFF); - P4.H = (ICPLB_DATA0 >> 16); - P4.L = (ICPLB_DATA0 & 0xFFFF); + P1.H = HI(IMEM_CONTROL); + P1.L = LO(IMEM_CONTROL); + P5.H = HI(ICPLB_ADDR0); + P5.L = LO(ICPLB_ADDR0); + P4.H = HI(ICPLB_DATA0); + P4.L = LO(ICPLB_DATA0); R7 = R0; /* If the code of interest already resides in the cache @@ -167,8 +167,8 @@ ENTRY(_cache_lock) [--SP]=( R7:0,P5:0 ); - P1.H = (IMEM_CONTROL >> 16); - P1.L = (IMEM_CONTROL & 0xFFFF); + P1.H = HI(IMEM_CONTROL); + P1.L = LO(IMEM_CONTROL); /* Disable the Interrupts*/ CLI R3; @@ -195,8 +195,8 @@ ENDPROC(_cache_lock) */ ENTRY(_read_iloc) - P1.H = (IMEM_CONTROL >> 16); - P1.L = (IMEM_CONTROL & 0xFFFF); + P1.H = HI(IMEM_CONTROL); + P1.L = LO(IMEM_CONTROL); R1 = 0xF; R0 = [P1]; R0 = R0 >> 3;