spi: controller driver for Designware SPI core
Driver for the Designware SPI core, it supports multipul interfaces like PCI/APB etc. User can use "dw_apb_ssi_db.pdf" from Synopsys as HW datasheet. [randy.dunlap@oracle.com: fix build] [akpm@linux-foundation.org: build fix] Signed-off-by: Feng Tang <feng.tang@intel.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Feng Tang
Grant Likely
parent
db389b6143
commit
e24c745272
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@ -292,6 +292,16 @@ config SPI_NUC900
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# Add new SPI master controllers in alphabetical order above this line
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#
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config SPI_DESIGNWARE
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bool "DesignWare SPI controller core support"
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depends on SPI_MASTER
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help
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general driver for SPI controller core from DesignWare
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config SPI_DW_PCI
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tristate "PCI interface driver for DW SPI core"
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depends on SPI_DESIGNWARE && PCI
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#
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# There are lots of SPI device types, with sensors and memory
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# being probably the most widely used ones.
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@ -16,6 +16,8 @@ obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
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obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
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obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
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obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
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obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o
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obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
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@ -0,0 +1,944 @@
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/*
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* dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
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*
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* Copyright (c) 2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/highmem.h>
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#include <linux/delay.h>
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#include <linux/spi/dw_spi.h>
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#include <linux/spi/spi.h>
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#endif
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#define START_STATE ((void *)0)
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#define RUNNING_STATE ((void *)1)
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#define DONE_STATE ((void *)2)
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#define ERROR_STATE ((void *)-1)
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#define QUEUE_RUNNING 0
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#define QUEUE_STOPPED 1
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#define MRST_SPI_DEASSERT 0
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#define MRST_SPI_ASSERT 1
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/* Slave spi_dev related */
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struct chip_data {
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u16 cr0;
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u8 cs; /* chip select pin */
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u8 n_bytes; /* current is a 1/2/4 byte op */
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u8 tmode; /* TR/TO/RO/EEPROM */
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u8 type; /* SPI/SSP/MicroWire */
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u8 poll_mode; /* 1 means use poll mode */
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u32 dma_width;
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u32 rx_threshold;
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u32 tx_threshold;
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u8 enable_dma;
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u8 bits_per_word;
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u16 clk_div; /* baud rate divider */
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u32 speed_hz; /* baud rate */
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int (*write)(struct dw_spi *dws);
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int (*read)(struct dw_spi *dws);
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void (*cs_control)(u32 command);
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};
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#ifdef CONFIG_DEBUG_FS
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static int spi_show_regs_open(struct inode *inode, struct file *file)
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{
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file->private_data = inode->i_private;
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return 0;
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}
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#define SPI_REGS_BUFSIZE 1024
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static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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struct dw_spi *dws;
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char *buf;
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u32 len = 0;
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ssize_t ret;
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dws = file->private_data;
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buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
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if (!buf)
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return 0;
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"MRST SPI0 registers:\n");
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SER: \t\t0x%08x\n", dw_readl(dws, ser));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SR: \t\t0x%08x\n", dw_readl(dws, sr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"IMR: \t\t0x%08x\n", dw_readl(dws, imr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"ISR: \t\t0x%08x\n", dw_readl(dws, isr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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kfree(buf);
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return ret;
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}
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static const struct file_operations mrst_spi_regs_ops = {
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.owner = THIS_MODULE,
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.open = spi_show_regs_open,
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.read = spi_show_regs,
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};
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static int mrst_spi_debugfs_init(struct dw_spi *dws)
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{
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dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
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if (!dws->debugfs)
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return -ENOMEM;
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debugfs_create_file("registers", S_IFREG | S_IRUGO,
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dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
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return 0;
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}
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static void mrst_spi_debugfs_remove(struct dw_spi *dws)
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{
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if (dws->debugfs)
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debugfs_remove_recursive(dws->debugfs);
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}
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#else
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static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
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{
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}
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static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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static void wait_till_not_busy(struct dw_spi *dws)
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{
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unsigned long end = jiffies + usecs_to_jiffies(1000);
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while (time_before(jiffies, end)) {
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if (!(dw_readw(dws, sr) & SR_BUSY))
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return;
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}
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dev_err(&dws->master->dev,
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"DW SPI: Stutus keeps busy for 1000us after a read/write!\n");
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}
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static void flush(struct dw_spi *dws)
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{
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while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
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dw_readw(dws, dr);
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wait_till_not_busy(dws);
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}
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static void null_cs_control(u32 command)
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{
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}
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static int null_writer(struct dw_spi *dws)
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{
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u8 n_bytes = dws->n_bytes;
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if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
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|| (dws->tx == dws->tx_end))
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return 0;
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dw_writew(dws, dr, 0);
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dws->tx += n_bytes;
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wait_till_not_busy(dws);
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return 1;
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}
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static int null_reader(struct dw_spi *dws)
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{
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u8 n_bytes = dws->n_bytes;
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while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
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&& (dws->rx < dws->rx_end)) {
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dw_readw(dws, dr);
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dws->rx += n_bytes;
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}
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wait_till_not_busy(dws);
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return dws->rx == dws->rx_end;
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}
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static int u8_writer(struct dw_spi *dws)
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{
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if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
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|| (dws->tx == dws->tx_end))
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return 0;
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dw_writew(dws, dr, *(u8 *)(dws->tx));
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++dws->tx;
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wait_till_not_busy(dws);
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return 1;
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}
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static int u8_reader(struct dw_spi *dws)
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{
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while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
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&& (dws->rx < dws->rx_end)) {
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*(u8 *)(dws->rx) = dw_readw(dws, dr);
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++dws->rx;
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}
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wait_till_not_busy(dws);
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return dws->rx == dws->rx_end;
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}
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static int u16_writer(struct dw_spi *dws)
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{
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if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
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|| (dws->tx == dws->tx_end))
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return 0;
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dw_writew(dws, dr, *(u16 *)(dws->tx));
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dws->tx += 2;
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wait_till_not_busy(dws);
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return 1;
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}
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static int u16_reader(struct dw_spi *dws)
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{
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u16 temp;
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while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
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&& (dws->rx < dws->rx_end)) {
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temp = dw_readw(dws, dr);
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*(u16 *)(dws->rx) = temp;
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dws->rx += 2;
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}
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wait_till_not_busy(dws);
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return dws->rx == dws->rx_end;
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}
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static void *next_transfer(struct dw_spi *dws)
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{
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struct spi_message *msg = dws->cur_msg;
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struct spi_transfer *trans = dws->cur_transfer;
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/* Move to next transfer */
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if (trans->transfer_list.next != &msg->transfers) {
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dws->cur_transfer =
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list_entry(trans->transfer_list.next,
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struct spi_transfer,
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transfer_list);
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return RUNNING_STATE;
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} else
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return DONE_STATE;
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}
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/*
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* Note: first step is the protocol driver prepares
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* a dma-capable memory, and this func just need translate
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* the virt addr to physical
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*/
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static int map_dma_buffers(struct dw_spi *dws)
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{
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if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
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|| !dws->cur_chip->enable_dma)
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return 0;
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if (dws->cur_transfer->tx_dma)
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dws->tx_dma = dws->cur_transfer->tx_dma;
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if (dws->cur_transfer->rx_dma)
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dws->rx_dma = dws->cur_transfer->rx_dma;
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return 1;
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}
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/* Caller already set message->status; dma and pio irqs are blocked */
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static void giveback(struct dw_spi *dws)
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{
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struct spi_transfer *last_transfer;
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unsigned long flags;
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struct spi_message *msg;
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spin_lock_irqsave(&dws->lock, flags);
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msg = dws->cur_msg;
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dws->cur_msg = NULL;
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dws->cur_transfer = NULL;
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dws->prev_chip = dws->cur_chip;
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dws->cur_chip = NULL;
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dws->dma_mapped = 0;
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queue_work(dws->workqueue, &dws->pump_messages);
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spin_unlock_irqrestore(&dws->lock, flags);
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last_transfer = list_entry(msg->transfers.prev,
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struct spi_transfer,
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transfer_list);
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if (!last_transfer->cs_change)
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dws->cs_control(MRST_SPI_DEASSERT);
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msg->state = NULL;
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if (msg->complete)
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msg->complete(msg->context);
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}
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static void int_error_stop(struct dw_spi *dws, const char *msg)
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{
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/* Stop and reset hw */
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flush(dws);
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spi_enable_chip(dws, 0);
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dev_err(&dws->master->dev, "%s\n", msg);
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dws->cur_msg->state = ERROR_STATE;
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tasklet_schedule(&dws->pump_transfers);
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}
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static void transfer_complete(struct dw_spi *dws)
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{
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/* Update total byte transfered return count actual bytes read */
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dws->cur_msg->actual_length += dws->len;
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/* Move to next transfer */
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dws->cur_msg->state = next_transfer(dws);
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/* Handle end of message */
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if (dws->cur_msg->state == DONE_STATE) {
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dws->cur_msg->status = 0;
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giveback(dws);
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} else
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tasklet_schedule(&dws->pump_transfers);
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}
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static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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{
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u16 irq_status, irq_mask = 0x3f;
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irq_status = dw_readw(dws, isr) & irq_mask;
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/* Error handling */
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if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
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dw_readw(dws, txoicr);
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dw_readw(dws, rxoicr);
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dw_readw(dws, rxuicr);
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int_error_stop(dws, "interrupt_transfer: fifo overrun");
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return IRQ_HANDLED;
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}
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/* INT comes from tx */
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if (dws->tx && (irq_status & SPI_INT_TXEI)) {
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while (dws->tx < dws->tx_end)
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dws->write(dws);
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if (dws->tx == dws->tx_end) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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transfer_complete(dws);
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}
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}
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/* INT comes from rx */
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if (dws->rx && (irq_status & SPI_INT_RXFI)) {
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if (dws->read(dws))
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transfer_complete(dws);
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t dw_spi_irq(int irq, void *dev_id)
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{
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struct dw_spi *dws = dev_id;
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if (!dws->cur_msg) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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/* Never fail */
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return IRQ_HANDLED;
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}
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return dws->transfer_handler(dws);
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}
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/* Must be called inside pump_transfers() */
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static void poll_transfer(struct dw_spi *dws)
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{
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if (dws->tx) {
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while (dws->write(dws))
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dws->read(dws);
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}
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dws->read(dws);
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transfer_complete(dws);
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}
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static void dma_transfer(struct dw_spi *dws, int cs_change)
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{
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}
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static void pump_transfers(unsigned long data)
|
||||
{
|
||||
struct dw_spi *dws = (struct dw_spi *)data;
|
||||
struct spi_message *message = NULL;
|
||||
struct spi_transfer *transfer = NULL;
|
||||
struct spi_transfer *previous = NULL;
|
||||
struct spi_device *spi = NULL;
|
||||
struct chip_data *chip = NULL;
|
||||
u8 bits = 0;
|
||||
u8 imask = 0;
|
||||
u8 cs_change = 0;
|
||||
u16 clk_div = 0;
|
||||
u32 speed = 0;
|
||||
u32 cr0 = 0;
|
||||
|
||||
/* Get current state information */
|
||||
message = dws->cur_msg;
|
||||
transfer = dws->cur_transfer;
|
||||
chip = dws->cur_chip;
|
||||
spi = message->spi;
|
||||
|
||||
if (message->state == ERROR_STATE) {
|
||||
message->status = -EIO;
|
||||
goto early_exit;
|
||||
}
|
||||
|
||||
/* Handle end of message */
|
||||
if (message->state == DONE_STATE) {
|
||||
message->status = 0;
|
||||
goto early_exit;
|
||||
}
|
||||
|
||||
/* Delay if requested at end of transfer*/
|
||||
if (message->state == RUNNING_STATE) {
|
||||
previous = list_entry(transfer->transfer_list.prev,
|
||||
struct spi_transfer,
|
||||
transfer_list);
|
||||
if (previous->delay_usecs)
|
||||
udelay(previous->delay_usecs);
|
||||
}
|
||||
|
||||
dws->n_bytes = chip->n_bytes;
|
||||
dws->dma_width = chip->dma_width;
|
||||
dws->cs_control = chip->cs_control;
|
||||
|
||||
dws->rx_dma = transfer->rx_dma;
|
||||
dws->tx_dma = transfer->tx_dma;
|
||||
dws->tx = (void *)transfer->tx_buf;
|
||||
dws->tx_end = dws->tx + transfer->len;
|
||||
dws->rx = transfer->rx_buf;
|
||||
dws->rx_end = dws->rx + transfer->len;
|
||||
dws->write = dws->tx ? chip->write : null_writer;
|
||||
dws->read = dws->rx ? chip->read : null_reader;
|
||||
dws->cs_change = transfer->cs_change;
|
||||
dws->len = dws->cur_transfer->len;
|
||||
if (chip != dws->prev_chip)
|
||||
cs_change = 1;
|
||||
|
||||
cr0 = chip->cr0;
|
||||
|
||||
/* Handle per transfer options for bpw and speed */
|
||||
if (transfer->speed_hz) {
|
||||
speed = chip->speed_hz;
|
||||
|
||||
if (transfer->speed_hz != speed) {
|
||||
speed = transfer->speed_hz;
|
||||
if (speed > dws->max_freq) {
|
||||
printk(KERN_ERR "MRST SPI0: unsupported"
|
||||
"freq: %dHz\n", speed);
|
||||
message->status = -EIO;
|
||||
goto early_exit;
|
||||
}
|
||||
|
||||
/* clk_div doesn't support odd number */
|
||||
clk_div = dws->max_freq / speed;
|
||||
clk_div = (clk_div >> 1) << 1;
|
||||
|
||||
chip->speed_hz = speed;
|
||||
chip->clk_div = clk_div;
|
||||
}
|
||||
}
|
||||
if (transfer->bits_per_word) {
|
||||
bits = transfer->bits_per_word;
|
||||
|
||||
switch (bits) {
|
||||
case 8:
|
||||
dws->n_bytes = 1;
|
||||
dws->dma_width = 1;
|
||||
dws->read = (dws->read != null_reader) ?
|
||||
u8_reader : null_reader;
|
||||
dws->write = (dws->write != null_writer) ?
|
||||
u8_writer : null_writer;
|
||||
break;
|
||||
case 16:
|
||||
dws->n_bytes = 2;
|
||||
dws->dma_width = 2;
|
||||
dws->read = (dws->read != null_reader) ?
|
||||
u16_reader : null_reader;
|
||||
dws->write = (dws->write != null_writer) ?
|
||||
u16_writer : null_writer;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "MRST SPI0: unsupported bits:"
|
||||
"%db\n", bits);
|
||||
message->status = -EIO;
|
||||
goto early_exit;
|
||||
}
|
||||
|
||||
cr0 = (bits - 1)
|
||||
| (chip->type << SPI_FRF_OFFSET)
|
||||
| (spi->mode << SPI_MODE_OFFSET)
|
||||
| (chip->tmode << SPI_TMOD_OFFSET);
|
||||
}
|
||||
message->state = RUNNING_STATE;
|
||||
|
||||
/* Check if current transfer is a DMA transaction */
|
||||
dws->dma_mapped = map_dma_buffers(dws);
|
||||
|
||||
if (!dws->dma_mapped && !chip->poll_mode) {
|
||||
if (dws->rx)
|
||||
imask |= SPI_INT_RXFI;
|
||||
if (dws->tx)
|
||||
imask |= SPI_INT_TXEI;
|
||||
dws->transfer_handler = interrupt_transfer;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reprogram registers only if
|
||||
* 1. chip select changes
|
||||
* 2. clk_div is changed
|
||||
* 3. control value changes
|
||||
*/
|
||||
if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div) {
|
||||
spi_enable_chip(dws, 0);
|
||||
|
||||
if (dw_readw(dws, ctrl0) != cr0)
|
||||
dw_writew(dws, ctrl0, cr0);
|
||||
|
||||
/* Set the interrupt mask, for poll mode just diable all int */
|
||||
spi_mask_intr(dws, 0xff);
|
||||
if (!chip->poll_mode)
|
||||
spi_umask_intr(dws, imask);
|
||||
|
||||
spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
|
||||
spi_chip_sel(dws, spi->chip_select);
|
||||
spi_enable_chip(dws, 1);
|
||||
|
||||
if (cs_change)
|
||||
dws->prev_chip = chip;
|
||||
}
|
||||
|
||||
if (dws->dma_mapped)
|
||||
dma_transfer(dws, cs_change);
|
||||
|
||||
if (chip->poll_mode)
|
||||
poll_transfer(dws);
|
||||
|
||||
return;
|
||||
|
||||
early_exit:
|
||||
giveback(dws);
|
||||
return;
|
||||
}
|
||||
|
||||
static void pump_messages(struct work_struct *work)
|
||||
{
|
||||
struct dw_spi *dws =
|
||||
container_of(work, struct dw_spi, pump_messages);
|
||||
unsigned long flags;
|
||||
|
||||
/* Lock queue and check for queue work */
|
||||
spin_lock_irqsave(&dws->lock, flags);
|
||||
if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
|
||||
dws->busy = 0;
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Make sure we are not already running a message */
|
||||
if (dws->cur_msg) {
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Extract head of queue */
|
||||
dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
|
||||
list_del_init(&dws->cur_msg->queue);
|
||||
|
||||
/* Initial message state*/
|
||||
dws->cur_msg->state = START_STATE;
|
||||
dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
|
||||
struct spi_transfer,
|
||||
transfer_list);
|
||||
dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
|
||||
|
||||
/* Mark as busy and launch transfers */
|
||||
tasklet_schedule(&dws->pump_transfers);
|
||||
|
||||
dws->busy = 1;
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
}
|
||||
|
||||
/* spi_device use this to queue in their spi_msg */
|
||||
static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
|
||||
{
|
||||
struct dw_spi *dws = spi_master_get_devdata(spi->master);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&dws->lock, flags);
|
||||
|
||||
if (dws->run == QUEUE_STOPPED) {
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
return -ESHUTDOWN;
|
||||
}
|
||||
|
||||
msg->actual_length = 0;
|
||||
msg->status = -EINPROGRESS;
|
||||
msg->state = START_STATE;
|
||||
|
||||
list_add_tail(&msg->queue, &dws->queue);
|
||||
|
||||
if (dws->run == QUEUE_RUNNING && !dws->busy) {
|
||||
|
||||
if (dws->cur_transfer || dws->cur_msg)
|
||||
queue_work(dws->workqueue,
|
||||
&dws->pump_messages);
|
||||
else {
|
||||
/* If no other data transaction in air, just go */
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
pump_messages(&dws->pump_messages);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This may be called twice for each spi dev */
|
||||
static int dw_spi_setup(struct spi_device *spi)
|
||||
{
|
||||
struct dw_spi_chip *chip_info = NULL;
|
||||
struct chip_data *chip;
|
||||
|
||||
if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
|
||||
return -EINVAL;
|
||||
|
||||
/* Only alloc on first setup */
|
||||
chip = spi_get_ctldata(spi);
|
||||
if (!chip) {
|
||||
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->cs_control = null_cs_control;
|
||||
chip->enable_dma = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Protocol drivers may change the chip settings, so...
|
||||
* if chip_info exists, use it
|
||||
*/
|
||||
chip_info = spi->controller_data;
|
||||
|
||||
/* chip_info doesn't always exist */
|
||||
if (chip_info) {
|
||||
if (chip_info->cs_control)
|
||||
chip->cs_control = chip_info->cs_control;
|
||||
|
||||
chip->poll_mode = chip_info->poll_mode;
|
||||
chip->type = chip_info->type;
|
||||
|
||||
chip->rx_threshold = 0;
|
||||
chip->tx_threshold = 0;
|
||||
|
||||
chip->enable_dma = chip_info->enable_dma;
|
||||
}
|
||||
|
||||
if (spi->bits_per_word <= 8) {
|
||||
chip->n_bytes = 1;
|
||||
chip->dma_width = 1;
|
||||
chip->read = u8_reader;
|
||||
chip->write = u8_writer;
|
||||
} else if (spi->bits_per_word <= 16) {
|
||||
chip->n_bytes = 2;
|
||||
chip->dma_width = 2;
|
||||
chip->read = u16_reader;
|
||||
chip->write = u16_writer;
|
||||
} else {
|
||||
/* Never take >16b case for MRST SPIC */
|
||||
dev_err(&spi->dev, "invalid wordsize\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
chip->bits_per_word = spi->bits_per_word;
|
||||
|
||||
chip->speed_hz = spi->max_speed_hz;
|
||||
if (chip->speed_hz)
|
||||
chip->clk_div = 25000000 / chip->speed_hz;
|
||||
else
|
||||
chip->clk_div = 8; /* default value */
|
||||
|
||||
chip->tmode = 0; /* Tx & Rx */
|
||||
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
|
||||
chip->cr0 = (chip->bits_per_word - 1)
|
||||
| (chip->type << SPI_FRF_OFFSET)
|
||||
| (spi->mode << SPI_MODE_OFFSET)
|
||||
| (chip->tmode << SPI_TMOD_OFFSET);
|
||||
|
||||
spi_set_ctldata(spi, chip);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dw_spi_cleanup(struct spi_device *spi)
|
||||
{
|
||||
struct chip_data *chip = spi_get_ctldata(spi);
|
||||
kfree(chip);
|
||||
}
|
||||
|
||||
static int __init init_queue(struct dw_spi *dws)
|
||||
{
|
||||
INIT_LIST_HEAD(&dws->queue);
|
||||
spin_lock_init(&dws->lock);
|
||||
|
||||
dws->run = QUEUE_STOPPED;
|
||||
dws->busy = 0;
|
||||
|
||||
tasklet_init(&dws->pump_transfers,
|
||||
pump_transfers, (unsigned long)dws);
|
||||
|
||||
INIT_WORK(&dws->pump_messages, pump_messages);
|
||||
dws->workqueue = create_singlethread_workqueue(
|
||||
dev_name(dws->master->dev.parent));
|
||||
if (dws->workqueue == NULL)
|
||||
return -EBUSY;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int start_queue(struct dw_spi *dws)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&dws->lock, flags);
|
||||
|
||||
if (dws->run == QUEUE_RUNNING || dws->busy) {
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
dws->run = QUEUE_RUNNING;
|
||||
dws->cur_msg = NULL;
|
||||
dws->cur_transfer = NULL;
|
||||
dws->cur_chip = NULL;
|
||||
dws->prev_chip = NULL;
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
|
||||
queue_work(dws->workqueue, &dws->pump_messages);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stop_queue(struct dw_spi *dws)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned limit = 50;
|
||||
int status = 0;
|
||||
|
||||
spin_lock_irqsave(&dws->lock, flags);
|
||||
dws->run = QUEUE_STOPPED;
|
||||
while (!list_empty(&dws->queue) && dws->busy && limit--) {
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
msleep(10);
|
||||
spin_lock_irqsave(&dws->lock, flags);
|
||||
}
|
||||
|
||||
if (!list_empty(&dws->queue) || dws->busy)
|
||||
status = -EBUSY;
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int destroy_queue(struct dw_spi *dws)
|
||||
{
|
||||
int status;
|
||||
|
||||
status = stop_queue(dws);
|
||||
if (status != 0)
|
||||
return status;
|
||||
destroy_workqueue(dws->workqueue);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Restart the controller, disable all interrupts, clean rx fifo */
|
||||
static void spi_hw_init(struct dw_spi *dws)
|
||||
{
|
||||
spi_enable_chip(dws, 0);
|
||||
spi_mask_intr(dws, 0xff);
|
||||
spi_enable_chip(dws, 1);
|
||||
flush(dws);
|
||||
}
|
||||
|
||||
int __devinit dw_spi_add_host(struct dw_spi *dws)
|
||||
{
|
||||
struct spi_master *master;
|
||||
int ret;
|
||||
|
||||
BUG_ON(dws == NULL);
|
||||
|
||||
master = spi_alloc_master(dws->parent_dev, 0);
|
||||
if (!master) {
|
||||
ret = -ENOMEM;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
dws->master = master;
|
||||
dws->type = SSI_MOTO_SPI;
|
||||
dws->prev_chip = NULL;
|
||||
dws->dma_inited = 0;
|
||||
dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
|
||||
|
||||
ret = request_irq(dws->irq, dw_spi_irq, 0,
|
||||
"dw_spi", dws);
|
||||
if (ret < 0) {
|
||||
dev_err(&master->dev, "can not get IRQ\n");
|
||||
goto err_free_master;
|
||||
}
|
||||
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
||||
master->bus_num = dws->bus_num;
|
||||
master->num_chipselect = dws->num_cs;
|
||||
master->cleanup = dw_spi_cleanup;
|
||||
master->setup = dw_spi_setup;
|
||||
master->transfer = dw_spi_transfer;
|
||||
|
||||
dws->dma_inited = 0;
|
||||
|
||||
/* Basic HW init */
|
||||
spi_hw_init(dws);
|
||||
|
||||
/* Initial and start queue */
|
||||
ret = init_queue(dws);
|
||||
if (ret) {
|
||||
dev_err(&master->dev, "problem initializing queue\n");
|
||||
goto err_diable_hw;
|
||||
}
|
||||
ret = start_queue(dws);
|
||||
if (ret) {
|
||||
dev_err(&master->dev, "problem starting queue\n");
|
||||
goto err_diable_hw;
|
||||
}
|
||||
|
||||
spi_master_set_devdata(master, dws);
|
||||
ret = spi_register_master(master);
|
||||
if (ret) {
|
||||
dev_err(&master->dev, "problem registering spi master\n");
|
||||
goto err_queue_alloc;
|
||||
}
|
||||
|
||||
mrst_spi_debugfs_init(dws);
|
||||
return 0;
|
||||
|
||||
err_queue_alloc:
|
||||
destroy_queue(dws);
|
||||
err_diable_hw:
|
||||
spi_enable_chip(dws, 0);
|
||||
free_irq(dws->irq, dws);
|
||||
err_free_master:
|
||||
spi_master_put(master);
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(dw_spi_add_host);
|
||||
|
||||
void __devexit dw_spi_remove_host(struct dw_spi *dws)
|
||||
{
|
||||
int status = 0;
|
||||
|
||||
if (!dws)
|
||||
return;
|
||||
mrst_spi_debugfs_remove(dws);
|
||||
|
||||
/* Remove the queue */
|
||||
status = destroy_queue(dws);
|
||||
if (status != 0)
|
||||
dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
|
||||
"complete, message memory not freed\n");
|
||||
|
||||
spi_enable_chip(dws, 0);
|
||||
/* Disable clk */
|
||||
spi_set_clk(dws, 0);
|
||||
free_irq(dws->irq, dws);
|
||||
|
||||
/* Disconnect from the SPI framework */
|
||||
spi_unregister_master(dws->master);
|
||||
}
|
||||
|
||||
int dw_spi_suspend_host(struct dw_spi *dws)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = stop_queue(dws);
|
||||
if (ret)
|
||||
return ret;
|
||||
spi_enable_chip(dws, 0);
|
||||
spi_set_clk(dws, 0);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(dw_spi_suspend_host);
|
||||
|
||||
int dw_spi_resume_host(struct dw_spi *dws)
|
||||
{
|
||||
int ret;
|
||||
|
||||
spi_hw_init(dws);
|
||||
ret = start_queue(dws);
|
||||
if (ret)
|
||||
dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(dw_spi_resume_host);
|
||||
|
||||
MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
|
||||
MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* mrst_spi_pci.c - PCI interface driver for DW SPI Core
|
||||
*
|
||||
* Copyright (c) 2009, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation,
|
||||
* Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/spi/dw_spi.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#define DRIVER_NAME "dw_spi_pci"
|
||||
|
||||
struct dw_spi_pci {
|
||||
struct pci_dev *pdev;
|
||||
struct dw_spi dws;
|
||||
};
|
||||
|
||||
static int __devinit spi_pci_probe(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
struct dw_spi_pci *dwpci;
|
||||
struct dw_spi *dws;
|
||||
int pci_bar = 0;
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO "DW: found PCI SPI controller(ID: %04x:%04x)\n",
|
||||
pdev->vendor, pdev->device);
|
||||
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dwpci = kzalloc(sizeof(struct dw_spi_pci), GFP_KERNEL);
|
||||
if (!dwpci) {
|
||||
ret = -ENOMEM;
|
||||
goto err_disable;
|
||||
}
|
||||
|
||||
dwpci->pdev = pdev;
|
||||
dws = &dwpci->dws;
|
||||
|
||||
/* Get basic io resource and map it */
|
||||
dws->paddr = pci_resource_start(pdev, pci_bar);
|
||||
dws->iolen = pci_resource_len(pdev, pci_bar);
|
||||
|
||||
ret = pci_request_region(pdev, pci_bar, dev_name(&pdev->dev));
|
||||
if (ret)
|
||||
goto err_kfree;
|
||||
|
||||
dws->regs = ioremap_nocache((unsigned long)dws->paddr,
|
||||
pci_resource_len(pdev, pci_bar));
|
||||
if (!dws->regs) {
|
||||
ret = -ENOMEM;
|
||||
goto err_release_reg;
|
||||
}
|
||||
|
||||
dws->parent_dev = &pdev->dev;
|
||||
dws->bus_num = 0;
|
||||
dws->num_cs = 4;
|
||||
dws->max_freq = 25000000; /* for Moorestwon */
|
||||
dws->irq = pdev->irq;
|
||||
|
||||
ret = dw_spi_add_host(dws);
|
||||
if (ret)
|
||||
goto err_unmap;
|
||||
|
||||
/* PCI hook and SPI hook use the same drv data */
|
||||
pci_set_drvdata(pdev, dwpci);
|
||||
return 0;
|
||||
|
||||
err_unmap:
|
||||
iounmap(dws->regs);
|
||||
err_release_reg:
|
||||
pci_release_region(pdev, pci_bar);
|
||||
err_kfree:
|
||||
kfree(dwpci);
|
||||
err_disable:
|
||||
pci_disable_device(pdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __devexit spi_pci_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
|
||||
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
iounmap(dwpci->dws.regs);
|
||||
pci_release_region(pdev, 0);
|
||||
kfree(dwpci);
|
||||
pci_disable_device(pdev);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int spi_suspend(struct pci_dev *pdev, pm_message_t state)
|
||||
{
|
||||
struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = dw_spi_suspend_host(&dwpci->dws);
|
||||
if (ret)
|
||||
return ret;
|
||||
pci_save_state(pdev);
|
||||
pci_disable_device(pdev);
|
||||
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spi_resume(struct pci_dev *pdev)
|
||||
{
|
||||
struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
pci_set_power_state(pdev, PCI_D0);
|
||||
pci_restore_state(pdev);
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
return dw_spi_resume_host(&dwpci->dws);
|
||||
}
|
||||
#else
|
||||
#define spi_suspend NULL
|
||||
#define spi_resume NULL
|
||||
#endif
|
||||
|
||||
static const struct pci_device_id pci_ids[] __devinitdata = {
|
||||
/* Intel Moorestown platform SPI controller 0 */
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct pci_driver dw_spi_driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.id_table = pci_ids,
|
||||
.probe = spi_pci_probe,
|
||||
.remove = __devexit_p(spi_pci_remove),
|
||||
.suspend = spi_suspend,
|
||||
.resume = spi_resume,
|
||||
};
|
||||
|
||||
static int __init mrst_spi_init(void)
|
||||
{
|
||||
return pci_register_driver(&dw_spi_driver);
|
||||
}
|
||||
|
||||
static void __exit mrst_spi_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&dw_spi_driver);
|
||||
}
|
||||
|
||||
module_init(mrst_spi_init);
|
||||
module_exit(mrst_spi_exit);
|
||||
|
||||
MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
|
||||
MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,212 @@
|
|||
#ifndef DW_SPI_HEADER_H
|
||||
#define DW_SPI_HEADER_H
|
||||
#include <linux/io.h>
|
||||
|
||||
/* Bit fields in CTRLR0 */
|
||||
#define SPI_DFS_OFFSET 0
|
||||
|
||||
#define SPI_FRF_OFFSET 4
|
||||
#define SPI_FRF_SPI 0x0
|
||||
#define SPI_FRF_SSP 0x1
|
||||
#define SPI_FRF_MICROWIRE 0x2
|
||||
#define SPI_FRF_RESV 0x3
|
||||
|
||||
#define SPI_MODE_OFFSET 6
|
||||
#define SPI_SCPH_OFFSET 6
|
||||
#define SPI_SCOL_OFFSET 7
|
||||
#define SPI_TMOD_OFFSET 8
|
||||
#define SPI_TMOD_TR 0x0 /* xmit & recv */
|
||||
#define SPI_TMOD_TO 0x1 /* xmit only */
|
||||
#define SPI_TMOD_RO 0x2 /* recv only */
|
||||
#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
|
||||
|
||||
#define SPI_SLVOE_OFFSET 10
|
||||
#define SPI_SRL_OFFSET 11
|
||||
#define SPI_CFS_OFFSET 12
|
||||
|
||||
/* Bit fields in SR, 7 bits */
|
||||
#define SR_MASK 0x7f /* cover 7 bits */
|
||||
#define SR_BUSY (1 << 0)
|
||||
#define SR_TF_NOT_FULL (1 << 1)
|
||||
#define SR_TF_EMPT (1 << 2)
|
||||
#define SR_RF_NOT_EMPT (1 << 3)
|
||||
#define SR_RF_FULL (1 << 4)
|
||||
#define SR_TX_ERR (1 << 5)
|
||||
#define SR_DCOL (1 << 6)
|
||||
|
||||
/* Bit fields in ISR, IMR, RISR, 7 bits */
|
||||
#define SPI_INT_TXEI (1 << 0)
|
||||
#define SPI_INT_TXOI (1 << 1)
|
||||
#define SPI_INT_RXUI (1 << 2)
|
||||
#define SPI_INT_RXOI (1 << 3)
|
||||
#define SPI_INT_RXFI (1 << 4)
|
||||
#define SPI_INT_MSTI (1 << 5)
|
||||
|
||||
/* TX RX interrupt level threshhold, max can be 256 */
|
||||
#define SPI_INT_THRESHOLD 32
|
||||
|
||||
enum dw_ssi_type {
|
||||
SSI_MOTO_SPI = 0,
|
||||
SSI_TI_SSP,
|
||||
SSI_NS_MICROWIRE,
|
||||
};
|
||||
|
||||
struct dw_spi_reg {
|
||||
u32 ctrl0;
|
||||
u32 ctrl1;
|
||||
u32 ssienr;
|
||||
u32 mwcr;
|
||||
u32 ser;
|
||||
u32 baudr;
|
||||
u32 txfltr;
|
||||
u32 rxfltr;
|
||||
u32 txflr;
|
||||
u32 rxflr;
|
||||
u32 sr;
|
||||
u32 imr;
|
||||
u32 isr;
|
||||
u32 risr;
|
||||
u32 txoicr;
|
||||
u32 rxoicr;
|
||||
u32 rxuicr;
|
||||
u32 msticr;
|
||||
u32 icr;
|
||||
u32 dmacr;
|
||||
u32 dmatdlr;
|
||||
u32 dmardlr;
|
||||
u32 idr;
|
||||
u32 version;
|
||||
u32 dr; /* Currently oper as 32 bits,
|
||||
though only low 16 bits matters */
|
||||
} __packed;
|
||||
|
||||
struct dw_spi {
|
||||
struct spi_master *master;
|
||||
struct spi_device *cur_dev;
|
||||
struct device *parent_dev;
|
||||
enum dw_ssi_type type;
|
||||
|
||||
void __iomem *regs;
|
||||
unsigned long paddr;
|
||||
u32 iolen;
|
||||
int irq;
|
||||
u32 max_freq; /* max bus freq supported */
|
||||
|
||||
u16 bus_num;
|
||||
u16 num_cs; /* supported slave numbers */
|
||||
|
||||
/* Driver message queue */
|
||||
struct workqueue_struct *workqueue;
|
||||
struct work_struct pump_messages;
|
||||
spinlock_t lock;
|
||||
struct list_head queue;
|
||||
int busy;
|
||||
int run;
|
||||
|
||||
/* Message Transfer pump */
|
||||
struct tasklet_struct pump_transfers;
|
||||
|
||||
/* Current message transfer state info */
|
||||
struct spi_message *cur_msg;
|
||||
struct spi_transfer *cur_transfer;
|
||||
struct chip_data *cur_chip;
|
||||
struct chip_data *prev_chip;
|
||||
size_t len;
|
||||
void *tx;
|
||||
void *tx_end;
|
||||
void *rx;
|
||||
void *rx_end;
|
||||
int dma_mapped;
|
||||
dma_addr_t rx_dma;
|
||||
dma_addr_t tx_dma;
|
||||
size_t rx_map_len;
|
||||
size_t tx_map_len;
|
||||
u8 n_bytes; /* current is a 1/2 bytes op */
|
||||
u8 max_bits_per_word; /* maxim is 16b */
|
||||
u32 dma_width;
|
||||
int cs_change;
|
||||
int (*write)(struct dw_spi *dws);
|
||||
int (*read)(struct dw_spi *dws);
|
||||
irqreturn_t (*transfer_handler)(struct dw_spi *dws);
|
||||
void (*cs_control)(u32 command);
|
||||
|
||||
/* Dma info */
|
||||
int dma_inited;
|
||||
struct dma_chan *txchan;
|
||||
struct dma_chan *rxchan;
|
||||
int txdma_done;
|
||||
int rxdma_done;
|
||||
u64 tx_param;
|
||||
u64 rx_param;
|
||||
struct device *dma_dev;
|
||||
dma_addr_t dma_addr;
|
||||
|
||||
/* Bus interface info */
|
||||
void *priv;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *debugfs;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define dw_readl(dw, name) \
|
||||
__raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
|
||||
#define dw_writel(dw, name, val) \
|
||||
__raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
|
||||
#define dw_readw(dw, name) \
|
||||
__raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
|
||||
#define dw_writew(dw, name, val) \
|
||||
__raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
|
||||
|
||||
static inline void spi_enable_chip(struct dw_spi *dws, int enable)
|
||||
{
|
||||
dw_writel(dws, ssienr, (enable ? 1 : 0));
|
||||
}
|
||||
|
||||
static inline void spi_set_clk(struct dw_spi *dws, u16 div)
|
||||
{
|
||||
dw_writel(dws, baudr, div);
|
||||
}
|
||||
|
||||
static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
|
||||
{
|
||||
if (cs > dws->num_cs)
|
||||
return;
|
||||
dw_writel(dws, ser, 1 << cs);
|
||||
}
|
||||
|
||||
/* Disable IRQ bits */
|
||||
static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
|
||||
{
|
||||
u32 new_mask;
|
||||
|
||||
new_mask = dw_readl(dws, imr) & ~mask;
|
||||
dw_writel(dws, imr, new_mask);
|
||||
}
|
||||
|
||||
/* Enable IRQ bits */
|
||||
static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
|
||||
{
|
||||
u32 new_mask;
|
||||
|
||||
new_mask = dw_readl(dws, imr) | mask;
|
||||
dw_writel(dws, imr, new_mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* Each SPI slave device to work with dw_api controller should
|
||||
* has such a structure claiming its working mode (PIO/DMA etc),
|
||||
* which can be save in the "controller_data" member of the
|
||||
* struct spi_device
|
||||
*/
|
||||
struct dw_spi_chip {
|
||||
u8 poll_mode; /* 0 for contoller polling mode */
|
||||
u8 type; /* SPI/SSP/Micrwire */
|
||||
u8 enable_dma;
|
||||
void (*cs_control)(u32 command);
|
||||
};
|
||||
|
||||
extern int dw_spi_add_host(struct dw_spi *dws);
|
||||
extern void dw_spi_remove_host(struct dw_spi *dws);
|
||||
extern int dw_spi_suspend_host(struct dw_spi *dws);
|
||||
extern int dw_spi_resume_host(struct dw_spi *dws);
|
||||
#endif /* DW_SPI_HEADER_H */
|
||||
Loading…
Reference in New Issue