Merge branch 'mb862xxfb-for-next' of git://git.denx.de/linux-2.6-agust
This commit is contained in:
Paul Mundt
commit
e2968f7018
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@ -2294,6 +2294,15 @@ config FB_MB862XX_LIME
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endchoice
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config FB_MB862XX_I2C
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bool "Support I2C bus on MB862XX GDC"
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depends on FB_MB862XX && I2C
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default y
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help
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Selecting this option adds Coral-P(A)/Lime GDC I2C bus adapter
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driver to support accessing I2C devices on controller's I2C bus.
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These are usually some video decoder chips.
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config FB_EP93XX
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tristate "EP93XX frame buffer support"
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depends on FB && ARCH_EP93XX
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@ -2,4 +2,7 @@
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# Makefile for the MB862xx framebuffer driver
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#
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obj-$(CONFIG_FB_MB862XX) := mb862xxfb.o mb862xxfb_accel.o
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obj-$(CONFIG_FB_MB862XX) += mb862xxfb.o
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mb862xxfb-y := mb862xxfbdrv.o mb862xxfb_accel.o
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mb862xxfb-$(CONFIG_FB_MB862XX_I2C) += mb862xx-i2c.o
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@ -0,0 +1,177 @@
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/*
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* Coral-P(A)/Lime I2C adapter driver
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*
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* (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/fb.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include "mb862xxfb.h"
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#include "mb862xx_reg.h"
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static int mb862xx_i2c_wait_event(struct i2c_adapter *adap)
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{
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struct mb862xxfb_par *par = adap->algo_data;
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u32 reg;
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do {
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udelay(1);
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reg = inreg(i2c, GC_I2C_BCR);
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if (reg & (I2C_INT | I2C_BER))
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break;
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} while (1);
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return (reg & I2C_BER) ? 0 : 1;
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}
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static int mb862xx_i2c_do_address(struct i2c_adapter *adap, int addr)
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{
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struct mb862xxfb_par *par = adap->algo_data;
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outreg(i2c, GC_I2C_DAR, addr);
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outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE);
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outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START);
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if (!mb862xx_i2c_wait_event(adap))
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return -EIO;
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par->i2c_rs = !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
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return par->i2c_rs;
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}
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static int mb862xx_i2c_write_byte(struct i2c_adapter *adap, u8 byte)
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{
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struct mb862xxfb_par *par = adap->algo_data;
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outreg(i2c, GC_I2C_DAR, byte);
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outreg(i2c, GC_I2C_BCR, I2C_START);
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if (!mb862xx_i2c_wait_event(adap))
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return -EIO;
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return !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
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}
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static int mb862xx_i2c_read_byte(struct i2c_adapter *adap, u8 *byte, int last)
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{
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struct mb862xxfb_par *par = adap->algo_data;
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outreg(i2c, GC_I2C_BCR, I2C_START | (last ? 0 : I2C_ACK));
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if (!mb862xx_i2c_wait_event(adap))
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return 0;
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*byte = inreg(i2c, GC_I2C_DAR);
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return 1;
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}
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void mb862xx_i2c_stop(struct i2c_adapter *adap)
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{
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struct mb862xxfb_par *par = adap->algo_data;
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outreg(i2c, GC_I2C_BCR, I2C_STOP);
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outreg(i2c, GC_I2C_CCR, I2C_DISABLE);
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par->i2c_rs = 0;
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}
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static int mb862xx_i2c_read(struct i2c_adapter *adap, struct i2c_msg *m)
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{
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int i, ret = 0;
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int last = m->len - 1;
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for (i = 0; i < m->len; i++) {
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if (!mb862xx_i2c_read_byte(adap, &m->buf[i], i == last)) {
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ret = -EIO;
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break;
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}
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}
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return ret;
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}
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static int mb862xx_i2c_write(struct i2c_adapter *adap, struct i2c_msg *m)
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{
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int i, ret = 0;
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for (i = 0; i < m->len; i++) {
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if (!mb862xx_i2c_write_byte(adap, m->buf[i])) {
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ret = -EIO;
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break;
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}
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}
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return ret;
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}
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static int mb862xx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num)
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{
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struct mb862xxfb_par *par = adap->algo_data;
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struct i2c_msg *m;
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int addr;
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int i = 0, err = 0;
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dev_dbg(par->dev, "%s: %d msgs\n", __func__, num);
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for (i = 0; i < num; i++) {
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m = &msgs[i];
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if (!m->len) {
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dev_dbg(par->dev, "%s: null msgs\n", __func__);
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continue;
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}
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addr = m->addr;
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if (m->flags & I2C_M_RD)
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addr |= 1;
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err = mb862xx_i2c_do_address(adap, addr);
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if (err < 0)
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break;
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if (m->flags & I2C_M_RD)
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err = mb862xx_i2c_read(adap, m);
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else
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err = mb862xx_i2c_write(adap, m);
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}
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if (i)
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mb862xx_i2c_stop(adap);
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return (err < 0) ? err : i;
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}
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static u32 mb862xx_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_SMBUS_BYTE_DATA;
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}
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static const struct i2c_algorithm mb862xx_algo = {
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.master_xfer = mb862xx_xfer,
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.functionality = mb862xx_func,
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};
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static struct i2c_adapter mb862xx_i2c_adapter = {
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.name = "MB862xx I2C adapter",
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.algo = &mb862xx_algo,
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.owner = THIS_MODULE,
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};
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int mb862xx_i2c_init(struct mb862xxfb_par *par)
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{
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int ret;
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mb862xx_i2c_adapter.algo_data = par;
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par->adap = &mb862xx_i2c_adapter;
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ret = i2c_add_adapter(par->adap);
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if (ret < 0) {
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dev_err(par->dev, "failed to add %s\n",
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mb862xx_i2c_adapter.name);
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}
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return ret;
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}
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void mb862xx_i2c_exit(struct mb862xxfb_par *par)
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{
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if (par->adap) {
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i2c_del_adapter(par->adap);
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par->adap = NULL;
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}
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}
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@ -5,11 +5,8 @@
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#ifndef _MB862XX_REG_H
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#define _MB862XX_REG_H
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#ifdef MB862XX_MMIO_BOTTOM
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#define MB862XX_MMIO_BASE 0x03fc0000
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#else
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#define MB862XX_MMIO_BASE 0x01fc0000
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#endif
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#define MB862XX_MMIO_HIGH_BASE 0x03fc0000
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#define MB862XX_I2C_BASE 0x0000c000
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#define MB862XX_DISP_BASE 0x00010000
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#define MB862XX_CAP_BASE 0x00018000
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@ -23,6 +20,7 @@
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#define GC_IMASK 0x00000024
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#define GC_SRST 0x0000002c
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#define GC_CCF 0x00000038
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#define GC_RSW 0x0000005c
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#define GC_CID 0x000000f0
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#define GC_REVISION 0x00000084
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@ -53,10 +51,16 @@
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#define GC_L0OA0 0x00000024
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#define GC_L0DA0 0x00000028
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#define GC_L0DY_L0DX 0x0000002c
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#define GC_L1M 0x00000030
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#define GC_L1DA 0x00000034
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#define GC_DCM1 0x00000100
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#define GC_L0EM 0x00000110
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#define GC_L0WY_L0WX 0x00000114
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#define GC_L0WH_L0WW 0x00000118
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#define GC_L1EM 0x00000120
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#define GC_L1WY_L1WX 0x00000124
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#define GC_L1WH_L1WW 0x00000128
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#define GC_DLS 0x00000180
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#define GC_DCM2 0x00000104
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#define GC_DCM3 0x00000108
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#define GC_CPM_CUTC 0x000000a0
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@ -68,6 +72,11 @@
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#define GC_CPM_CEN0 0x00100000
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#define GC_CPM_CEN1 0x00200000
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#define GC_DCM1_DEN 0x80000000
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#define GC_DCM1_L1E 0x00020000
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#define GC_L1M_16 0x80000000
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#define GC_L1M_YC 0x40000000
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#define GC_L1M_CS 0x20000000
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#define GC_DCM01_ESY 0x00000004
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#define GC_DCM01_SC 0x00003f00
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@ -79,9 +88,50 @@
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#define GC_L0M_L0C_16 0x80000000
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#define GC_L0EM_L0EC_24 0x40000000
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#define GC_L0M_L0W_UNIT 64
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#define GC_L1EM_DM 0x02000000
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#define GC_DISP_REFCLK_400 400
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/* I2C */
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#define GC_I2C_BSR 0x00000000 /* BSR */
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#define GC_I2C_BCR 0x00000004 /* BCR */
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#define GC_I2C_CCR 0x00000008 /* CCR */
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#define GC_I2C_ADR 0x0000000C /* ADR */
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#define GC_I2C_DAR 0x00000010 /* DAR */
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#define I2C_DISABLE 0x00000000
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#define I2C_STOP 0x00000000
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#define I2C_START 0x00000010
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#define I2C_REPEATED_START 0x00000030
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#define I2C_CLOCK_AND_ENABLE 0x0000003f
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#define I2C_READY 0x01
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#define I2C_INT 0x01
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#define I2C_INTE 0x02
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#define I2C_ACK 0x08
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#define I2C_BER 0x80
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#define I2C_BEIE 0x40
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#define I2C_TRX 0x80
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#define I2C_LRB 0x10
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/* Capture registers and bits */
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#define GC_CAP_VCM 0x00000000
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#define GC_CAP_CSC 0x00000004
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#define GC_CAP_VCS 0x00000008
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#define GC_CAP_CBM 0x00000010
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#define GC_CAP_CBOA 0x00000014
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#define GC_CAP_CBLA 0x00000018
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#define GC_CAP_IMG_START 0x0000001C
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#define GC_CAP_IMG_END 0x00000020
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#define GC_CAP_CMSS 0x00000048
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#define GC_CAP_CMDS 0x0000004C
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#define GC_VCM_VIE 0x80000000
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#define GC_VCM_CM 0x03000000
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#define GC_VCM_VS_PAL 0x00000002
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#define GC_CBM_OO 0x80000000
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#define GC_CBM_HRV 0x00000010
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#define GC_CBM_CBST 0x00000001
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|
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/* Carmine specific */
|
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#define MB86297_DRAW_BASE 0x00020000
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#define MB86297_DISP0_BASE 0x00100000
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|
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@ -1,6 +1,26 @@
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#ifndef __MB862XX_H__
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#define __MB862XX_H__
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struct mb862xx_l1_cfg {
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unsigned short sx;
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unsigned short sy;
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unsigned short sw;
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unsigned short sh;
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unsigned short dx;
|
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unsigned short dy;
|
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unsigned short dw;
|
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unsigned short dh;
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int mirror;
|
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};
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|
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#define MB862XX_BASE 'M'
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#define MB862XX_L1_GET_CFG _IOR(MB862XX_BASE, 0, struct mb862xx_l1_cfg*)
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#define MB862XX_L1_SET_CFG _IOW(MB862XX_BASE, 1, struct mb862xx_l1_cfg*)
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#define MB862XX_L1_ENABLE _IOW(MB862XX_BASE, 2, int)
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#define MB862XX_L1_CAP_CTL _IOW(MB862XX_BASE, 3, int)
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|
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#ifdef __KERNEL__
|
||||
|
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#define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
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#define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
|
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#define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
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|
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@ -38,6 +58,8 @@ struct mb862xxfb_par {
|
|||
void __iomem *mmio_base; /* remapped registers */
|
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size_t mapped_vram; /* length of remapped vram */
|
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size_t mmio_len; /* length of register region */
|
||||
unsigned long cap_buf; /* capture buffers offset */
|
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size_t cap_len; /* length of capture buffers */
|
||||
|
||||
void __iomem *host; /* relocatable reg. bases */
|
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void __iomem *i2c;
|
||||
|
|
@ -57,11 +79,23 @@ struct mb862xxfb_par {
|
|||
unsigned int refclk; /* disp. reference clock */
|
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struct mb862xx_gc_mode *gc_mode; /* GDC mode init data */
|
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int pre_init; /* don't init display if 1 */
|
||||
struct i2c_adapter *adap; /* GDC I2C bus adapter */
|
||||
int i2c_rs;
|
||||
|
||||
struct mb862xx_l1_cfg l1_cfg;
|
||||
int l1_stride;
|
||||
|
||||
u32 pseudo_palette[16];
|
||||
};
|
||||
|
||||
extern void mb862xxfb_init_accel(struct fb_info *info, int xres);
|
||||
#ifdef CONFIG_FB_MB862XX_I2C
|
||||
extern int mb862xx_i2c_init(struct mb862xxfb_par *par);
|
||||
extern void mb862xx_i2c_exit(struct mb862xxfb_par *par);
|
||||
#else
|
||||
static inline int mb862xx_i2c_init(struct mb862xxfb_par *par) { return 0; }
|
||||
static inline void mb862xx_i2c_exit(struct mb862xxfb_par *par) { }
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
|
||||
#error "Select Lime GDC or CoralP/Carmine support, but not both together"
|
||||
|
|
@ -82,4 +116,6 @@ extern void mb862xxfb_init_accel(struct fb_info *info, int xres);
|
|||
|
||||
#define pack(a, b) (((a) << 16) | (b))
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
|
||||
#define NR_PALETTE 256
|
||||
#define MB862XX_MEM_SIZE 0x1000000
|
||||
#define CORALP_MEM_SIZE 0x4000000
|
||||
#define CORALP_MEM_SIZE 0x2000000
|
||||
#define CARMINE_MEM_SIZE 0x8000000
|
||||
#define DRV_NAME "mb862xxfb"
|
||||
|
||||
|
|
@ -309,6 +309,97 @@ static int mb862xxfb_blank(int mode, struct fb_info *fbi)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
struct mb862xxfb_par *par = fbi->par;
|
||||
struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
|
||||
void __user *argp = (void __user *)arg;
|
||||
int *enable;
|
||||
u32 l1em = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case MB862XX_L1_GET_CFG:
|
||||
if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
|
||||
return -EFAULT;
|
||||
break;
|
||||
case MB862XX_L1_SET_CFG:
|
||||
if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
|
||||
return -EFAULT;
|
||||
if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
|
||||
/* downscaling */
|
||||
outreg(cap, GC_CAP_CSC,
|
||||
pack((l1_cfg->sh << 11) / l1_cfg->dh,
|
||||
(l1_cfg->sw << 11) / l1_cfg->dw));
|
||||
l1em = inreg(disp, GC_L1EM);
|
||||
l1em &= ~GC_L1EM_DM;
|
||||
} else if ((l1_cfg->sw <= l1_cfg->dw) &&
|
||||
(l1_cfg->sh <= l1_cfg->dh)) {
|
||||
/* upscaling */
|
||||
outreg(cap, GC_CAP_CSC,
|
||||
pack((l1_cfg->sh << 11) / l1_cfg->dh,
|
||||
(l1_cfg->sw << 11) / l1_cfg->dw));
|
||||
outreg(cap, GC_CAP_CMSS,
|
||||
pack(l1_cfg->sw >> 1, l1_cfg->sh));
|
||||
outreg(cap, GC_CAP_CMDS,
|
||||
pack(l1_cfg->dw >> 1, l1_cfg->dh));
|
||||
l1em = inreg(disp, GC_L1EM);
|
||||
l1em |= GC_L1EM_DM;
|
||||
}
|
||||
|
||||
if (l1_cfg->mirror) {
|
||||
outreg(cap, GC_CAP_CBM,
|
||||
inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
|
||||
l1em |= l1_cfg->dw * 2 - 8;
|
||||
} else {
|
||||
outreg(cap, GC_CAP_CBM,
|
||||
inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
|
||||
l1em &= 0xffff0000;
|
||||
}
|
||||
outreg(disp, GC_L1EM, l1em);
|
||||
break;
|
||||
case MB862XX_L1_ENABLE:
|
||||
enable = (int *)arg;
|
||||
if (*enable) {
|
||||
outreg(disp, GC_L1DA, par->cap_buf);
|
||||
outreg(cap, GC_CAP_IMG_START,
|
||||
pack(l1_cfg->sy >> 1, l1_cfg->sx));
|
||||
outreg(cap, GC_CAP_IMG_END,
|
||||
pack(l1_cfg->sh, l1_cfg->sw));
|
||||
outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
|
||||
(par->l1_stride << 16));
|
||||
outreg(disp, GC_L1WY_L1WX,
|
||||
pack(l1_cfg->dy, l1_cfg->dx));
|
||||
outreg(disp, GC_L1WH_L1WW,
|
||||
pack(l1_cfg->dh - 1, l1_cfg->dw));
|
||||
outreg(disp, GC_DLS, 1);
|
||||
outreg(cap, GC_CAP_VCM,
|
||||
GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
|
||||
outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
|
||||
GC_DCM1_DEN | GC_DCM1_L1E);
|
||||
} else {
|
||||
outreg(cap, GC_CAP_VCM,
|
||||
inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
|
||||
outreg(disp, GC_DCM1,
|
||||
inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
|
||||
}
|
||||
break;
|
||||
case MB862XX_L1_CAP_CTL:
|
||||
enable = (int *)arg;
|
||||
if (*enable) {
|
||||
outreg(cap, GC_CAP_VCM,
|
||||
inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
|
||||
} else {
|
||||
outreg(cap, GC_CAP_VCM,
|
||||
inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* framebuffer ops */
|
||||
static struct fb_ops mb862xxfb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
|
|
@ -320,6 +411,7 @@ static struct fb_ops mb862xxfb_ops = {
|
|||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_ioctl = mb862xxfb_ioctl,
|
||||
};
|
||||
|
||||
/* initialize fb_info data */
|
||||
|
|
@ -328,6 +420,7 @@ static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
|
|||
struct mb862xxfb_par *par = fbi->par;
|
||||
struct mb862xx_gc_mode *mode = par->gc_mode;
|
||||
unsigned long reg;
|
||||
int stride;
|
||||
|
||||
fbi->fbops = &mb862xxfb_ops;
|
||||
fbi->pseudo_palette = par->pseudo_palette;
|
||||
|
|
@ -336,7 +429,6 @@ static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
|
|||
|
||||
strcpy(fbi->fix.id, DRV_NAME);
|
||||
fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
|
||||
fbi->fix.smem_len = par->mapped_vram;
|
||||
fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
|
||||
fbi->fix.mmio_len = par->mmio_len;
|
||||
fbi->fix.accel = FB_ACCEL_NONE;
|
||||
|
|
@ -420,6 +512,28 @@ static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
|
|||
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
|
||||
fbi->fix.line_length = (fbi->var.xres_virtual *
|
||||
fbi->var.bits_per_pixel) / 8;
|
||||
fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
|
||||
|
||||
/*
|
||||
* reserve space for capture buffers and two cursors
|
||||
* at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
|
||||
*/
|
||||
par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
|
||||
par->cap_len = 0x1bd800;
|
||||
par->l1_cfg.sx = 0;
|
||||
par->l1_cfg.sy = 0;
|
||||
par->l1_cfg.sw = 720;
|
||||
par->l1_cfg.sh = 576;
|
||||
par->l1_cfg.dx = 0;
|
||||
par->l1_cfg.dy = 0;
|
||||
par->l1_cfg.dw = 720;
|
||||
par->l1_cfg.dh = 576;
|
||||
stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
|
||||
par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
|
||||
outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
|
||||
(par->l1_stride << 16));
|
||||
outreg(cap, GC_CAP_CBOA, par->cap_buf);
|
||||
outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -742,22 +856,38 @@ static int coralp_init(struct mb862xxfb_par *par)
|
|||
|
||||
par->refclk = GC_DISP_REFCLK_400;
|
||||
|
||||
if (par->mapped_vram >= 0x2000000) {
|
||||
/* relocate gdc registers space */
|
||||
writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
|
||||
udelay(1); /* wait at least 20 bus cycles */
|
||||
}
|
||||
|
||||
ver = inreg(host, GC_CID);
|
||||
cn = (ver & GC_CID_CNAME_MSK) >> 8;
|
||||
ver = ver & GC_CID_VERSION_MSK;
|
||||
if (cn == 3) {
|
||||
unsigned long reg;
|
||||
|
||||
dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
|
||||
(ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
|
||||
par->pdev->revision);
|
||||
outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
|
||||
udelay(200);
|
||||
outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
|
||||
udelay(10);
|
||||
reg = inreg(disp, GC_DCM1);
|
||||
if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
|
||||
par->pre_init = 1;
|
||||
|
||||
if (!par->pre_init) {
|
||||
outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
|
||||
udelay(200);
|
||||
outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
|
||||
udelay(10);
|
||||
}
|
||||
/* Clear interrupt status */
|
||||
outreg(host, GC_IST, 0);
|
||||
} else {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mb862xx_i2c_init(par);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -899,7 +1029,13 @@ static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
|
|||
case PCI_DEVICE_ID_FUJITSU_CORALPA:
|
||||
par->fb_base_phys = pci_resource_start(par->pdev, 0);
|
||||
par->mapped_vram = CORALP_MEM_SIZE;
|
||||
par->mmio_base_phys = par->fb_base_phys + MB862XX_MMIO_BASE;
|
||||
if (par->mapped_vram >= 0x2000000) {
|
||||
par->mmio_base_phys = par->fb_base_phys +
|
||||
MB862XX_MMIO_HIGH_BASE;
|
||||
} else {
|
||||
par->mmio_base_phys = par->fb_base_phys +
|
||||
MB862XX_MMIO_BASE;
|
||||
}
|
||||
par->mmio_len = MB862XX_MMIO_SIZE;
|
||||
par->type = BT_CORALP;
|
||||
break;
|
||||
|
|
@ -1009,6 +1145,8 @@ static void __devexit mb862xx_pci_remove(struct pci_dev *pdev)
|
|||
outreg(host, GC_IMASK, 0);
|
||||
}
|
||||
|
||||
mb862xx_i2c_exit(par);
|
||||
|
||||
device_remove_file(&pdev->dev, &dev_attr_dispregs);
|
||||
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
Loading…
Reference in New Issue