[PATCH] bnx2: update firmware handshake for 5708
Dynamically determine the shared memory location where eeprom parameters are stored instead of using a fixed location. Add speed reporting to management firmware. This allows management firmware to know the current speed without contending for MII registers. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
371377091d
commit
e3648b3d8d
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@ -436,6 +436,62 @@ alloc_mem_err:
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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static void
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bnx2_report_fw_link(struct bnx2 *bp)
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{
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u32 fw_link_status = 0;
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if (bp->link_up) {
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u32 bmsr;
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switch (bp->line_speed) {
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case SPEED_10:
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if (bp->duplex == DUPLEX_HALF)
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fw_link_status = BNX2_LINK_STATUS_10HALF;
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else
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fw_link_status = BNX2_LINK_STATUS_10FULL;
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break;
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case SPEED_100:
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if (bp->duplex == DUPLEX_HALF)
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fw_link_status = BNX2_LINK_STATUS_100HALF;
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else
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fw_link_status = BNX2_LINK_STATUS_100FULL;
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break;
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case SPEED_1000:
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if (bp->duplex == DUPLEX_HALF)
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fw_link_status = BNX2_LINK_STATUS_1000HALF;
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else
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fw_link_status = BNX2_LINK_STATUS_1000FULL;
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break;
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case SPEED_2500:
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if (bp->duplex == DUPLEX_HALF)
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fw_link_status = BNX2_LINK_STATUS_2500HALF;
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else
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fw_link_status = BNX2_LINK_STATUS_2500FULL;
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break;
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}
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fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
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if (bp->autoneg) {
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fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
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bnx2_read_phy(bp, MII_BMSR, &bmsr);
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bnx2_read_phy(bp, MII_BMSR, &bmsr);
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if (!(bmsr & BMSR_ANEGCOMPLETE) ||
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bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
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fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
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else
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fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
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}
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}
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else
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fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
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REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
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}
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static void
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static void
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bnx2_report_link(struct bnx2 *bp)
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bnx2_report_link(struct bnx2 *bp)
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{
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{
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@ -467,6 +523,8 @@ bnx2_report_link(struct bnx2 *bp)
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netif_carrier_off(bp->dev);
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netif_carrier_off(bp->dev);
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printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
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printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
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}
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}
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bnx2_report_fw_link(bp);
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}
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}
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static void
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static void
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@ -1123,13 +1181,13 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
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}
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}
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val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_CONFIG) &
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val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
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BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
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BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
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if (val) {
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if (val) {
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u32 is_backplane;
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u32 is_backplane;
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is_backplane = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
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is_backplane = REG_RD_IND(bp, bp->shmem_base +
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BNX2_SHARED_HW_CFG_CONFIG);
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BNX2_SHARED_HW_CFG_CONFIG);
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if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
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if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
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@ -1280,13 +1338,13 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
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bp->fw_wr_seq++;
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bp->fw_wr_seq++;
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msg_data |= bp->fw_wr_seq;
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msg_data |= bp->fw_wr_seq;
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REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
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REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
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/* wait for an acknowledgement. */
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/* wait for an acknowledgement. */
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for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
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for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
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udelay(5);
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udelay(5);
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val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
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val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
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if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
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if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
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break;
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break;
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@ -1299,7 +1357,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
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msg_data &= ~BNX2_DRV_MSG_CODE;
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msg_data &= ~BNX2_DRV_MSG_CODE;
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msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
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msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
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REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
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REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
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bp->fw_timed_out = 1;
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bp->fw_timed_out = 1;
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@ -2935,7 +2993,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
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/* Deposit a driver reset signature so the firmware knows that
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/* Deposit a driver reset signature so the firmware knows that
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* this is a soft reset. */
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* this is a soft reset. */
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REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
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REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
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BNX2_DRV_RESET_SIGNATURE_MAGIC);
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BNX2_DRV_RESET_SIGNATURE_MAGIC);
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bp->fw_timed_out = 0;
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bp->fw_timed_out = 0;
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@ -4012,7 +4070,7 @@ bnx2_timer(unsigned long data)
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goto bnx2_restart_timer;
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goto bnx2_restart_timer;
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msg = (u32) ++bp->fw_drv_pulse_wr_seq;
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msg = (u32) ++bp->fw_drv_pulse_wr_seq;
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REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
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REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
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if ((bp->phy_flags & PHY_SERDES_FLAG) &&
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if ((bp->phy_flags & PHY_SERDES_FLAG) &&
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(CHIP_NUM(bp) == CHIP_NUM_5706)) {
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(CHIP_NUM(bp) == CHIP_NUM_5706)) {
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@ -5483,10 +5541,18 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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bnx2_init_nvram(bp);
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bnx2_init_nvram(bp);
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reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
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if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
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BNX2_SHM_HDR_SIGNATURE_SIG)
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bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
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else
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bp->shmem_base = HOST_VIEW_SHMEM_BASE;
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/* Get the permanent MAC address. First we need to make sure the
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/* Get the permanent MAC address. First we need to make sure the
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* firmware is actually running.
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* firmware is actually running.
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*/
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*/
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reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
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reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
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if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
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if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
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BNX2_DEV_INFO_SIGNATURE_MAGIC) {
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BNX2_DEV_INFO_SIGNATURE_MAGIC) {
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@ -5495,14 +5561,13 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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goto err_out_unmap;
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goto err_out_unmap;
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}
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}
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bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
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bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
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BNX2_DEV_INFO_BC_REV);
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reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
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reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
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bp->mac_addr[0] = (u8) (reg >> 8);
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bp->mac_addr[0] = (u8) (reg >> 8);
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bp->mac_addr[1] = (u8) reg;
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bp->mac_addr[1] = (u8) reg;
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reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
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reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
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bp->mac_addr[2] = (u8) (reg >> 24);
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bp->mac_addr[2] = (u8) (reg >> 24);
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bp->mac_addr[3] = (u8) (reg >> 16);
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bp->mac_addr[3] = (u8) (reg >> 16);
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bp->mac_addr[4] = (u8) (reg >> 8);
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bp->mac_addr[4] = (u8) (reg >> 8);
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@ -5538,7 +5603,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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bp->flags |= NO_WOL_FLAG;
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bp->flags |= NO_WOL_FLAG;
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if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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bp->phy_addr = 2;
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bp->phy_addr = 2;
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reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
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reg = REG_RD_IND(bp, bp->shmem_base +
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BNX2_SHARED_HW_CFG_CONFIG);
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BNX2_SHARED_HW_CFG_CONFIG);
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if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
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if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
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bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
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bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
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@ -5562,8 +5627,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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if (bp->phy_flags & PHY_SERDES_FLAG) {
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if (bp->phy_flags & PHY_SERDES_FLAG) {
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bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
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bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
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reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
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reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
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BNX2_PORT_HW_CFG_CONFIG);
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reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
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reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
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if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
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if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
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bp->autoneg = 0;
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bp->autoneg = 0;
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@ -3715,6 +3715,15 @@ struct l2_fhdr {
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#define BNX2_MCP_ROM 0x00150000
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#define BNX2_MCP_ROM 0x00150000
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#define BNX2_MCP_SCRATCH 0x00160000
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#define BNX2_MCP_SCRATCH 0x00160000
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#define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH
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#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
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#define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000
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#define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
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#define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
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#define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4
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#define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8
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#define NUM_MC_HASH_REGISTERS 8
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#define NUM_MC_HASH_REGISTERS 8
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@ -4052,6 +4061,8 @@ struct bnx2 {
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u8 mac_addr[8];
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u8 mac_addr[8];
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u32 shmem_base;
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u32 fw_ver;
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u32 fw_ver;
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int pm_cap;
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int pm_cap;
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@ -4191,6 +4202,38 @@ struct fw_info {
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#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
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#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
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#define BNX2_LINK_STATUS 0x0000000c
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#define BNX2_LINK_STATUS 0x0000000c
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#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
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#define BNX2_LINK_STATUS_LINK_UP 0x1
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#define BNX2_LINK_STATUS_LINK_DOWN 0x0
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#define BNX2_LINK_STATUS_SPEED_MASK 0x1e
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#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
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#define BNX2_LINK_STATUS_10HALF (1<<1)
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#define BNX2_LINK_STATUS_10FULL (2<<1)
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#define BNX2_LINK_STATUS_100HALF (3<<1)
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#define BNX2_LINK_STATUS_100BASE_T4 (4<<1)
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#define BNX2_LINK_STATUS_100FULL (5<<1)
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#define BNX2_LINK_STATUS_1000HALF (6<<1)
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#define BNX2_LINK_STATUS_1000FULL (7<<1)
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#define BNX2_LINK_STATUS_2500HALF (8<<1)
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#define BNX2_LINK_STATUS_2500FULL (9<<1)
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#define BNX2_LINK_STATUS_AN_ENABLED (1<<5)
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#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6)
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#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7)
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#define BNX2_LINK_STATUS_RESERVED (1<<8)
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#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
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#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
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#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
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#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
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#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
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#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
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#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
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#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16)
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#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17)
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#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
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#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
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#define BNX2_LINK_STATUS_SERDES_LINK (1<<20)
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#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
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#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
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#define BNX2_DRV_PULSE_MB 0x00000010
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#define BNX2_DRV_PULSE_MB 0x00000010
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#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
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#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
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