Merge tag 'drm-fixes-5.4-2019-10-30' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
drm-fixes-5.4-2019-10-30: amdgpu: - clang fixes - Updated golden settings - GPUVM fixes for navi - Navi sdma fix - Navi display fixes - Freesync fix - Gamma fix for DCN - DP dongle detection fix - Fix for undervolting on vega10 radeon: - enable kexec fix for PPC scheduler: - set an error on fence if hw job failed Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191030162339.44366-1-alexander.deucher@amd.com
This commit is contained in:
commit
e54de91a24
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@ -218,7 +218,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
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struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
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struct dma_fence *fence = NULL, *finished;
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struct amdgpu_job *job;
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int r;
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int r = 0;
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job = to_amdgpu_job(sched_job);
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finished = &job->base.s_fence->finished;
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@ -243,6 +243,8 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
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job->fence = dma_fence_get(fence);
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amdgpu_job_free_resources(job);
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fence = r ? ERR_PTR(r) : fence;
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return fence;
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}
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@ -93,7 +93,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
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{
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
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@ -140,7 +140,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
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@ -179,7 +179,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
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@ -151,6 +151,15 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
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WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
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tmp = mmGCVM_L2_CNTL3_DEFAULT;
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if (adev->gmc.translate_further) {
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
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L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
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} else {
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
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L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
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}
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WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
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tmp = mmGCVM_L2_CNTL4_DEFAULT;
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@ -309,6 +309,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
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job->vm_needs_flush = true;
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job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
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amdgpu_ring_pad_ib(ring, &job->ibs[0]);
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r = amdgpu_job_submit(job, &adev->mman.entity,
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AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
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@ -137,6 +137,15 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
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tmp = mmMMVM_L2_CNTL3_DEFAULT;
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if (adev->gmc.translate_further) {
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
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L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
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} else {
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
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L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
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}
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
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tmp = mmMMVM_L2_CNTL4_DEFAULT;
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@ -254,6 +254,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
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};
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static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
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@ -24,15 +24,20 @@
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# It calculates Bandwidth and Watermarks values for HW programming
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#
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ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
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cc_stack_align := -mpreferred-stack-boundary=4
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else ifneq ($(call cc-option, -mstack-alignment=16),)
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cc_stack_align := -mstack-alignment=16
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calcs_ccflags := -mhard-float -msse
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ifdef CONFIG_CC_IS_GCC
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ifeq ($(call cc-ifversion, -lt, 0701, y), y)
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IS_OLD_GCC = 1
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endif
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endif
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calcs_ccflags := -mhard-float -msse $(cc_stack_align)
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ifdef CONFIG_CC_IS_CLANG
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ifdef IS_OLD_GCC
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# Stack alignment mismatch, proceed with caution.
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# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
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# (8B stack alignment).
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calcs_ccflags += -mpreferred-stack-boundary=4
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else
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calcs_ccflags += -msse2
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endif
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@ -580,6 +580,10 @@ static bool construct(struct dc *dc,
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#ifdef CONFIG_DRM_AMD_DC_DCN2_0
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// Allocate memory for the vm_helper
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dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
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if (!dc->vm_helper) {
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dm_error("%s: failed to create dc->vm_helper\n", __func__);
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goto fail;
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}
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#endif
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memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
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@ -2767,6 +2767,15 @@ void core_link_enable_stream(
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CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
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COLOR_DEPTH_UNDEFINED);
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/* This second call is needed to reconfigure the DIG
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* as a workaround for the incorrect value being applied
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* from transmitter control.
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*/
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if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
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stream->link->link_enc->funcs->setup(
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stream->link->link_enc,
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pipe_ctx->stream->signal);
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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if (pipe_ctx->stream->timing.flags.DSC) {
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if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
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@ -374,6 +374,7 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
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enum display_dongle_type *dongle = &sink_cap->dongle_type;
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uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
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bool is_type2_dongle = false;
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int retry_count = 2;
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struct dp_hdmi_dongle_signature_data *dongle_signature;
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/* Assume we have no valid DP passive dongle connected */
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@ -386,6 +387,16 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
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DP_HDMI_DONGLE_ADDRESS,
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type2_dongle_buf,
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sizeof(type2_dongle_buf))) {
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/* Passive HDMI dongles can sometimes fail here without retrying*/
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while (retry_count > 0) {
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if (i2c_read(ddc,
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DP_HDMI_DONGLE_ADDRESS,
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type2_dongle_buf,
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sizeof(type2_dongle_buf)))
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break;
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retry_count--;
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}
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if (retry_count == 0) {
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*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
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sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
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@ -394,6 +405,7 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
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DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
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return;
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}
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}
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/* Check if Type 2 dongle.*/
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if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
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@ -404,6 +404,9 @@ bool resource_are_streams_timing_synchronizable(
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if (stream1->view_format != stream2->view_format)
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return false;
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if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
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return false;
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return true;
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}
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static bool is_dp_and_hdmi_sharable(
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@ -1540,6 +1543,9 @@ bool dc_is_stream_unchanged(
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if (!are_stream_backends_same(old_stream, stream))
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return false;
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if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
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return false;
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return true;
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}
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@ -393,6 +393,10 @@ bool cm_helper_translate_curve_to_hw_format(
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rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
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rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
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rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
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rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
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rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
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// All 3 color channels have same x
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corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
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dc_fixpt_from_int(region_start));
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@ -464,13 +468,6 @@ bool cm_helper_translate_curve_to_hw_format(
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i = 1;
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while (i != hw_points + 1) {
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if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
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rgb_plus_1->red = rgb->red;
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if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
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rgb_plus_1->green = rgb->green;
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if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
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rgb_plus_1->blue = rgb->blue;
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rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
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rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
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rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
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@ -562,6 +559,10 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
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rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
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rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
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rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
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rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
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rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
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|
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corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
|
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dc_fixpt_from_int(region_start));
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corner_points[0].green.x = corner_points[0].red.x;
|
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|
@ -624,13 +625,6 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
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|
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i = 1;
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while (i != hw_points + 1) {
|
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if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
|
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rgb_plus_1->red = rgb->red;
|
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if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
|
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rgb_plus_1->green = rgb->green;
|
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if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
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rgb_plus_1->blue = rgb->blue;
|
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|
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rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
|
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rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
|
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rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
|
||||
|
|
|
@ -10,15 +10,20 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
|
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DCN20 += dcn20_dsc.o
|
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endif
|
||||
|
||||
ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
|
||||
cc_stack_align := -mpreferred-stack-boundary=4
|
||||
else ifneq ($(call cc-option, -mstack-alignment=16),)
|
||||
cc_stack_align := -mstack-alignment=16
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse
|
||||
|
||||
ifdef CONFIG_CC_IS_GCC
|
||||
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
|
||||
IS_OLD_GCC = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse $(cc_stack_align)
|
||||
|
||||
ifdef CONFIG_CC_IS_CLANG
|
||||
ifdef IS_OLD_GCC
|
||||
# Stack alignment mismatch, proceed with caution.
|
||||
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
|
||||
# (8B stack alignment).
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -mpreferred-stack-boundary=4
|
||||
else
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2
|
||||
endif
|
||||
|
||||
|
|
|
@ -814,7 +814,7 @@ static const struct resource_caps res_cap_nv14 = {
|
|||
.num_audio = 6,
|
||||
.num_stream_encoder = 5,
|
||||
.num_pll = 5,
|
||||
.num_dwb = 0,
|
||||
.num_dwb = 1,
|
||||
.num_ddc = 5,
|
||||
};
|
||||
|
||||
|
|
|
@ -3,15 +3,20 @@
|
|||
|
||||
DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o
|
||||
|
||||
ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
|
||||
cc_stack_align := -mpreferred-stack-boundary=4
|
||||
else ifneq ($(call cc-option, -mstack-alignment=16),)
|
||||
cc_stack_align := -mstack-alignment=16
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse
|
||||
|
||||
ifdef CONFIG_CC_IS_GCC
|
||||
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
|
||||
IS_OLD_GCC = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse $(cc_stack_align)
|
||||
|
||||
ifdef CONFIG_CC_IS_CLANG
|
||||
ifdef IS_OLD_GCC
|
||||
# Stack alignment mismatch, proceed with caution.
|
||||
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
|
||||
# (8B stack alignment).
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -mpreferred-stack-boundary=4
|
||||
else
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2
|
||||
endif
|
||||
|
||||
|
|
|
@ -24,15 +24,20 @@
|
|||
# It provides the general basic services required by other DAL
|
||||
# subcomponents.
|
||||
|
||||
ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
|
||||
cc_stack_align := -mpreferred-stack-boundary=4
|
||||
else ifneq ($(call cc-option, -mstack-alignment=16),)
|
||||
cc_stack_align := -mstack-alignment=16
|
||||
dml_ccflags := -mhard-float -msse
|
||||
|
||||
ifdef CONFIG_CC_IS_GCC
|
||||
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
|
||||
IS_OLD_GCC = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
dml_ccflags := -mhard-float -msse $(cc_stack_align)
|
||||
|
||||
ifdef CONFIG_CC_IS_CLANG
|
||||
ifdef IS_OLD_GCC
|
||||
# Stack alignment mismatch, proceed with caution.
|
||||
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
|
||||
# (8B stack alignment).
|
||||
dml_ccflags += -mpreferred-stack-boundary=4
|
||||
else
|
||||
dml_ccflags += -msse2
|
||||
endif
|
||||
|
||||
|
|
|
@ -2577,7 +2577,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
|
|||
mode_lib->vba.MinActiveDRAMClockChangeMargin
|
||||
+ mode_lib->vba.DRAMClockChangeLatency;
|
||||
|
||||
if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
|
||||
if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
|
||||
mode_lib->vba.DRAMClockChangeWatermark += 25;
|
||||
mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
|
||||
} else {
|
||||
if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
|
||||
|
|
|
@ -1,15 +1,20 @@
|
|||
#
|
||||
# Makefile for the 'dsc' sub-component of DAL.
|
||||
|
||||
ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
|
||||
cc_stack_align := -mpreferred-stack-boundary=4
|
||||
else ifneq ($(call cc-option, -mstack-alignment=16),)
|
||||
cc_stack_align := -mstack-alignment=16
|
||||
dsc_ccflags := -mhard-float -msse
|
||||
|
||||
ifdef CONFIG_CC_IS_GCC
|
||||
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
|
||||
IS_OLD_GCC = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
dsc_ccflags := -mhard-float -msse $(cc_stack_align)
|
||||
|
||||
ifdef CONFIG_CC_IS_CLANG
|
||||
ifdef IS_OLD_GCC
|
||||
# Stack alignment mismatch, proceed with caution.
|
||||
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
|
||||
# (8B stack alignment).
|
||||
dsc_ccflags += -mpreferred-stack-boundary=4
|
||||
else
|
||||
dsc_ccflags += -msse2
|
||||
endif
|
||||
|
||||
|
|
|
@ -5098,9 +5098,7 @@ static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
|
|||
|
||||
if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
|
||||
podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
|
||||
for (i = 0; i < podn_vdd_dep->count - 1; i++)
|
||||
od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
|
||||
if (od_vddc_lookup_table->entries[i].us_vdd < podn_vdd_dep->entries[i].vddc)
|
||||
for (i = 0; i < podn_vdd_dep->count; i++)
|
||||
od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
|
||||
} else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
|
||||
podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
|
||||
|
|
|
@ -379,11 +379,25 @@ radeon_pci_remove(struct pci_dev *pdev)
|
|||
static void
|
||||
radeon_pci_shutdown(struct pci_dev *pdev)
|
||||
{
|
||||
#ifdef CONFIG_PPC64
|
||||
struct drm_device *ddev = pci_get_drvdata(pdev);
|
||||
#endif
|
||||
|
||||
/* if we are running in a VM, make sure the device
|
||||
* torn down properly on reboot/shutdown
|
||||
*/
|
||||
if (radeon_device_is_virtual())
|
||||
radeon_pci_remove(pdev);
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
/* Some adapters need to be suspended before a
|
||||
* shutdown occurs in order to prevent an error
|
||||
* during kexec.
|
||||
* Make this power specific becauase it breaks
|
||||
* some non-power boards.
|
||||
*/
|
||||
radeon_suspend_kms(ddev, true, true, false);
|
||||
#endif
|
||||
}
|
||||
|
||||
static int radeon_pmops_suspend(struct device *dev)
|
||||
|
|
|
@ -479,6 +479,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
|
|||
struct drm_sched_job *s_job, *tmp;
|
||||
uint64_t guilty_context;
|
||||
bool found_guilty = false;
|
||||
struct dma_fence *fence;
|
||||
|
||||
list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
|
||||
struct drm_sched_fence *s_fence = s_job->s_fence;
|
||||
|
@ -492,7 +493,16 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
|
|||
dma_fence_set_error(&s_fence->finished, -ECANCELED);
|
||||
|
||||
dma_fence_put(s_job->s_fence->parent);
|
||||
s_job->s_fence->parent = sched->ops->run_job(s_job);
|
||||
fence = sched->ops->run_job(s_job);
|
||||
|
||||
if (IS_ERR_OR_NULL(fence)) {
|
||||
s_job->s_fence->parent = NULL;
|
||||
dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
|
||||
} else {
|
||||
s_job->s_fence->parent = fence;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(drm_sched_resubmit_jobs);
|
||||
|
@ -720,7 +730,7 @@ static int drm_sched_main(void *param)
|
|||
fence = sched->ops->run_job(sched_job);
|
||||
drm_sched_fence_scheduled(s_fence);
|
||||
|
||||
if (fence) {
|
||||
if (!IS_ERR_OR_NULL(fence)) {
|
||||
s_fence->parent = dma_fence_get(fence);
|
||||
r = dma_fence_add_callback(fence, &sched_job->cb,
|
||||
drm_sched_process_job);
|
||||
|
@ -730,8 +740,11 @@ static int drm_sched_main(void *param)
|
|||
DRM_ERROR("fence add callback failed (%d)\n",
|
||||
r);
|
||||
dma_fence_put(fence);
|
||||
} else
|
||||
} else {
|
||||
|
||||
dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
|
||||
drm_sched_process_job(NULL, &sched_job->cb);
|
||||
}
|
||||
|
||||
wake_up(&sched->job_scheduled);
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue