pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car E3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Takeshi Kihara
Geert Uytterhoeven
parent
a040f3dec8
commit
e551122cdb
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@ -500,7 +500,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
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#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
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#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
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#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
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#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
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#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
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#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
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#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
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@ -1022,35 +1022,35 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
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PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
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PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
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PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
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PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
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PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
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PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
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PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
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PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
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PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
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PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
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PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
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PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
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PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
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PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
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PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
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PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
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PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
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PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
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@ -1116,21 +1116,21 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
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PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
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PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
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PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
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PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
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PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
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PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
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PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
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@ -1275,7 +1275,7 @@ static const u16 pinmux_data[] = {
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/* IPSR14 */
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PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
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PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
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PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
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PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
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PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
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@ -501,7 +501,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
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#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
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#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
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#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
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#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
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#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
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#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
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#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
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@ -1017,35 +1017,35 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
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PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
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PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
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PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
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PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
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PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
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PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
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PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
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PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
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PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
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PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
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PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
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PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
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PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
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PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
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PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
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PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
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PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
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PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
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PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
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PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
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@ -1112,20 +1112,20 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
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PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
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PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
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PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
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PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
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PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
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PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
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PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
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PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
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PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
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PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
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@ -1269,7 +1269,7 @@ static const u16 pinmux_data[] = {
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/* IPSR14 */
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PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
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PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
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PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
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PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
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PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
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@ -415,7 +415,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
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#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
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#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
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#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
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#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
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#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
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#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
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#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
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#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
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@ -982,23 +982,23 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
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PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
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PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
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PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
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PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
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PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
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PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
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/* IPSR9 */
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PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
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PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
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PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
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PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
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PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
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PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
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PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
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PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
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PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
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@ -1035,7 +1035,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
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PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
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PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
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PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
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PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
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PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
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@ -1044,7 +1044,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
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PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
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PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDFC_0),
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PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
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||||
PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
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||||
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
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||||
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
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@ -1054,13 +1054,13 @@ static const u16 pinmux_data[] = {
|
|||
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||||
/* IPSR11 */
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PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
|
||||
PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
|
||||
PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
|
||||
PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
|
||||
PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
|
||||
PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
|
||||
PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
|
||||
PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
|
||||
PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
|
||||
|
|
@ -1078,14 +1078,14 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
|
||||
PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
|
||||
PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
|
||||
PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
|
||||
PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
|
||||
|
|
|
|||
Loading…
Reference in New Issue