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Merge branch 'renesas/clock' into next/boards 

* renesas/clock:
  ARM: shmobile: r8a7790: remove old style audio clock
  ARM: shmobile: r8a7778: remove old style audio clock
  ARM: shmobile: r8a7791: Rename VSP1_SY clocks to VSP1_S
  ARM: shmobile: r8a7790: Rename VSP1_(SY|RT) clocks to VSP1_(S|R)
  ARM: shmobile: r8a7791: Fix the I2C clocks parents in legacy code
  ARM: shmobile: r8a7790: Fix the I2C clocks parents in legacy code
  ARM: shmobile: Introduce shmobile_clk_workaround()
  ARM: shmobile: r8a7791: Use rcar_gen2_read_mode_pins() helper
This commit is contained in:
Olof Johansson 2014-05-05 14:14:24 -07:00
parent f1e9637f4b 932616eed0
commit e80c9c2c2d
10 changed files with 81 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/r8a7790.dtsi
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@ -673,7 +673,7 @@
renesas,clock-indices = <
R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
>;
clock-output-names =
"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",

2
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -688,7 +688,7 @@
renesas,clock-indices = <
R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
>;
clock-output-names =
"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",

2
arch/arm/mach-shmobile/Makefile
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@ -21,8 +21,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
# Clock objects
ifndef CONFIG_COMMON_CLK
obj-y += clock.o
ifndef CONFIG_COMMON_CLK
obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o
obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o

22
arch/arm/mach-shmobile/clock-r8a7778.c
View File

@ -175,10 +175,6 @@ static struct clk mstp_clks[MSTP_NR] = {
static struct clk_lookup lookups[] = {
/* main */
CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
CLKDEV_CON_ID("audio_clk_internal", &s1_clk),
CLKDEV_CON_ID("shyway_clk", &s_clk),
CLKDEV_CON_ID("peripheral_clk", &p_clk),
@ -234,15 +230,15 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP531]),
CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP530]),
CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP529]),
CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP528]),
CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP527]),
CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP526]),
CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP525]),
CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]),
CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]),
};
void __init r8a7778_clock_init(void)

32
arch/arm/mach-shmobile/clock-r8a7790.c
View File

@ -249,10 +249,10 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
[MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
[MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
[MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
[MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
[MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
[MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
[MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
[MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
@ -294,10 +294,6 @@ static struct clk mstp_clks[MSTP_NR] = {
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
CLKDEV_CON_ID("audio_clk_internal", &m2_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
CLKDEV_CON_ID("main", &main_clk),
@ -381,16 +377,16 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP1031]),
CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP1030]),
CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP1029]),
CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP1028]),
CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP1027]),
CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP1026]),
CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP1025]),
CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP1024]),
CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP1023]),
CLKDEV_ICK_ID("scu.9", "rcar_sound", &mstp_clks[MSTP1022]),
CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),

23
arch/arm/mach-shmobile/clock-r8a7791.c
View File

@ -25,6 +25,7 @@
#include <linux/clkdev.h>
#include <mach/clock.h>
#include <mach/common.h>
#include <mach/rcar-gen2.h>
/*
* MD EXTAL PLL0 PLL1 PLL3
@ -43,8 +44,6 @@
* see "p1 / 2" on R8A7791_CLOCK_ROOT() below
*/
#define MD(nr) (1 << nr)
#define CPG_BASE 0xe6150000
#define CPG_LEN 0x1000
@ -68,7 +67,6 @@
#define MSTPSR9 IOMEM(0xe61509a4)
#define MSTPSR11 IOMEM(0xe61509ac)
#define MODEMR 0xE6160060
#define SDCKCR 0xE6150074
#define SD1CKCR 0xE6150078
#define SD2CKCR 0xE615026c
@ -190,12 +188,12 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */
[MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */
[MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */
[MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
[MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
[MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
[MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
[MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
[MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
[MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
[MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
[MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
[MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
@ -295,14 +293,9 @@ static struct clk_lookup lookups[] = {
void __init r8a7791_clock_init(void)
{
void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
u32 mode;
u32 mode = rcar_gen2_read_mode_pins();
int k, ret = 0;
BUG_ON(!modemr);
mode = ioread32(modemr);
iounmap(modemr);
switch (mode & (MD(14) | MD(13))) {
case 0:
R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);

28
arch/arm/mach-shmobile/clock.c
View File

@ -21,6 +21,32 @@
*/
#include <linux/kernel.h>
#include <linux/init.h>
#ifdef CONFIG_COMMON_CLK
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <mach/clock.h>
void __init shmobile_clk_workaround(const struct clk_name *clks,
int nr_clks, bool enable)
{
const struct clk_name *clkn;
struct clk *clk;
unsigned int i;
for (i = 0; i < nr_clks; ++i) {
clkn = clks + i;
clk = clk_get(NULL, clkn->clk);
if (!IS_ERR(clk)) {
clk_register_clkdev(clk, clkn->con_id, clkn->dev_id);
if (enable)
clk_prepare_enable(clk);
clk_put(clk);
}
}
}
#else /* CONFIG_COMMON_CLK */
#include <linux/sh_clk.h>
#include <linux/export.h>
#include <mach/clock.h>
@ -58,3 +84,5 @@ void __clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(__clk_put);
#endif /* CONFIG_COMMON_CLK */

16
arch/arm/mach-shmobile/include/mach/clock.h
View File

@ -1,6 +1,21 @@
#ifndef CLOCK_H
#define CLOCK_H
#ifdef CONFIG_COMMON_CLK
/* temporary clock configuration helper for platform devices */
struct clk_name {
const char *clk;
const char *con_id;
const char *dev_id;
};
void shmobile_clk_workaround(const struct clk_name *clks, int nr_clks,
bool enable);
#else /* CONFIG_COMMON_CLK */
/* legacy clock implementation */
unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
@ -36,4 +51,5 @@ do { \
(p)->div = d; \
} while (0)
#endif /* CONFIG_COMMON_CLK */
#endif

4
include/dt-bindings/clock/r8a7790-clock.h
View File

@ -33,8 +33,8 @@
#define R8A7790_CLK_TMU0 25
#define R8A7790_CLK_VSP1_DU1 27
#define R8A7790_CLK_VSP1_DU0 28
#define R8A7790_CLK_VSP1_RT 30
#define R8A7790_CLK_VSP1_SY 31
#define R8A7790_CLK_VSP1_R 30
#define R8A7790_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7790_CLK_SCIFA2 2

2
include/dt-bindings/clock/r8a7791-clock.h
View File

@ -32,7 +32,7 @@
#define R8A7791_CLK_TMU0 25
#define R8A7791_CLK_VSP1_DU1 27
#define R8A7791_CLK_VSP1_DU0 28
#define R8A7791_CLK_VSP1_SY 31
#define R8A7791_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7791_CLK_SCIFA2 2