ARM: EXYNOS: Add support for MSHC controller clocks
Add clock instances for bic("bus interface unit clock") and ciu("card interface unit clock") of the all four MSHC controller instances. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -569,34 +569,29 @@ static struct clk exynos5_init_clocks_off[] = {
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.enable = exynos5_clk_ip_peris_ctrl,
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.ctrlbit = (1 << 19),
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}, {
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.name = "hsmmc",
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.devname = "exynos4-sdhci.0",
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.name = "biu", /* bus interface unit clock */
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.devname = "dw_mmc.0",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 12),
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}, {
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.name = "hsmmc",
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.devname = "exynos4-sdhci.1",
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.name = "biu",
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.devname = "dw_mmc.1",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 13),
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}, {
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.name = "hsmmc",
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.devname = "exynos4-sdhci.2",
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.name = "biu",
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.devname = "dw_mmc.2",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 14),
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}, {
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.name = "hsmmc",
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.devname = "exynos4-sdhci.3",
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.name = "biu",
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.devname = "dw_mmc.3",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 15),
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}, {
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.name = "dwmci",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 16),
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}, {
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.name = "sata",
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.devname = "ahci",
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@ -1015,8 +1010,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
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static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "exynos4-sdhci.0",
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.name = "ciu", /* card interface unit clock */
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.devname = "dw_mmc.0",
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.parent = &exynos5_clk_dout_mmc0.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 0),
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@ -1026,8 +1021,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
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static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "exynos4-sdhci.1",
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.name = "ciu",
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.devname = "dw_mmc.1",
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.parent = &exynos5_clk_dout_mmc1.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 4),
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@ -1037,8 +1032,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
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static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "exynos4-sdhci.2",
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.name = "ciu",
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.devname = "dw_mmc.2",
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.parent = &exynos5_clk_dout_mmc2.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 8),
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@ -1048,8 +1043,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
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static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "exynos4-sdhci.3",
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.name = "ciu",
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.devname = "dw_mmc.3",
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.parent = &exynos5_clk_dout_mmc3.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 12),
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@ -1122,14 +1117,6 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
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static struct clksrc_clk exynos5_clksrcs[] = {
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{
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.clk = {
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.name = "sclk_dwmci",
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.parent = &exynos5_clk_dout_mmc4.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 16),
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},
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.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
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}, {
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.clk = {
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.name = "sclk_fimd",
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.devname = "s3cfb.1",
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