sh: hook up shared mstp32 clock code to sh7785
Hook up the shared 32-bit module stop bit code to sh7785. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -193,65 +193,34 @@ static struct clk *clks[] = {
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&umem_clk,
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&umem_clk,
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};
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};
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static int mstpcr_clk_enable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
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clk->enable_reg);
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return 0;
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}
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static void mstpcr_clk_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
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clk->enable_reg);
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}
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static struct clk_ops mstpcr_clk_ops = {
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.enable = mstpcr_clk_enable,
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.disable = mstpcr_clk_disable,
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.recalc = followparent_recalc,
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};
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#define MSTPCR0 0xffc80030
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#define MSTPCR0 0xffc80030
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#define MSTPCR1 0xffc80034
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#define MSTPCR1 0xffc80034
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#define CLK(_name, _id, _parent, _enable_reg, \
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static struct clk mstp_clks[] = {
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_enable_bit, _flags) \
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{ \
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.name = _name, \
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.id = _id, \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_enable_reg, \
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.enable_bit = _enable_bit, \
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.flags = _flags, \
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.ops = &mstpcr_clk_ops, \
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}
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static struct clk mstpcr_clks[] = {
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/* MSTPCR0 */
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/* MSTPCR0 */
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CLK("scif_fck", 5, &peripheral_clk, MSTPCR0, 29, 0),
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SH_CLK_MSTP32("scif_fck", 5, &peripheral_clk, MSTPCR0, 29, 0),
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CLK("scif_fck", 4, &peripheral_clk, MSTPCR0, 28, 0),
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SH_CLK_MSTP32("scif_fck", 4, &peripheral_clk, MSTPCR0, 28, 0),
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CLK("scif_fck", 3, &peripheral_clk, MSTPCR0, 27, 0),
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SH_CLK_MSTP32("scif_fck", 3, &peripheral_clk, MSTPCR0, 27, 0),
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CLK("scif_fck", 2, &peripheral_clk, MSTPCR0, 26, 0),
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SH_CLK_MSTP32("scif_fck", 2, &peripheral_clk, MSTPCR0, 26, 0),
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CLK("scif_fck", 1, &peripheral_clk, MSTPCR0, 25, 0),
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SH_CLK_MSTP32("scif_fck", 1, &peripheral_clk, MSTPCR0, 25, 0),
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CLK("scif_fck", 0, &peripheral_clk, MSTPCR0, 24, 0),
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SH_CLK_MSTP32("scif_fck", 0, &peripheral_clk, MSTPCR0, 24, 0),
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CLK("ssi_fck", 1, &peripheral_clk, MSTPCR0, 21, 0),
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SH_CLK_MSTP32("ssi_fck", 1, &peripheral_clk, MSTPCR0, 21, 0),
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CLK("ssi_fck", 0, &peripheral_clk, MSTPCR0, 20, 0),
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SH_CLK_MSTP32("ssi_fck", 0, &peripheral_clk, MSTPCR0, 20, 0),
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CLK("hac_fck", 1, &peripheral_clk, MSTPCR0, 17, 0),
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SH_CLK_MSTP32("hac_fck", 1, &peripheral_clk, MSTPCR0, 17, 0),
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CLK("hac_fck", 0, &peripheral_clk, MSTPCR0, 16, 0),
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SH_CLK_MSTP32("hac_fck", 0, &peripheral_clk, MSTPCR0, 16, 0),
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CLK("mmcif_fck", -1, &peripheral_clk, MSTPCR0, 13, 0),
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SH_CLK_MSTP32("mmcif_fck", -1, &peripheral_clk, MSTPCR0, 13, 0),
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CLK("flctl_fck", -1, &peripheral_clk, MSTPCR0, 12, 0),
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SH_CLK_MSTP32("flctl_fck", -1, &peripheral_clk, MSTPCR0, 12, 0),
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CLK("tmu345_fck", -1, &peripheral_clk, MSTPCR0, 9, 0),
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SH_CLK_MSTP32("tmu345_fck", -1, &peripheral_clk, MSTPCR0, 9, 0),
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CLK("tmu012_fck", -1, &peripheral_clk, MSTPCR0, 8, 0),
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SH_CLK_MSTP32("tmu012_fck", -1, &peripheral_clk, MSTPCR0, 8, 0),
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CLK("siof_fck", -1, &peripheral_clk, MSTPCR0, 3, 0),
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SH_CLK_MSTP32("siof_fck", -1, &peripheral_clk, MSTPCR0, 3, 0),
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CLK("hspi_fck", -1, &peripheral_clk, MSTPCR0, 2, 0),
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SH_CLK_MSTP32("hspi_fck", -1, &peripheral_clk, MSTPCR0, 2, 0),
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/* MSTPCR1 */
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/* MSTPCR1 */
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CLK("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
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SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
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CLK("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
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SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
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CLK("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
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SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
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CLK("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
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SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
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CLK("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
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SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
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};
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};
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int __init arch_clk_init(void)
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int __init arch_clk_init(void)
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@ -260,8 +229,9 @@ int __init arch_clk_init(void)
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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ret |= clk_register(clks[i]);
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ret |= clk_register(clks[i]);
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for (i = 0; i < ARRAY_SIZE(mstpcr_clks); i++)
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ret |= clk_register(&mstpcr_clks[i]);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
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return ret;
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return ret;
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}
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}
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