ARM: Introduce plat-tcc irq framework
Introduce lowlevel interrupt routines. Signed-off-by: "Hans J. Koch" <hjk@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Hans J. Koch
Thomas Gleixner
parent
da15797eae
commit
e9268ef225
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@ -3,4 +3,4 @@
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#
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# Common support
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obj-y += clock.o
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obj-y += clock.o irq.o
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@ -2,5 +2,6 @@
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#define MACH_TCC8K_COMMON_H
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extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
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extern void tcc8k_init_irq(void);
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#endif
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@ -0,0 +1,111 @@
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/*
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* Copyright (C) Telechips, Inc.
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* Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
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*
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* Licensed under the terms of the GNU GPL version 2.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/tcc8k-regs.h>
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#include <mach/irqs.h>
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#include "common.h"
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/* Disable IRQ */
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static void tcc8000_mask_ack_irq0(unsigned int irq)
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{
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PIC0_IEN &= ~(1 << irq);
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PIC0_CREQ |= (1 << irq);
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}
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static void tcc8000_mask_ack_irq1(unsigned int irq)
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{
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PIC1_IEN &= ~(1 << (irq - 32));
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PIC1_CREQ |= (1 << (irq - 32));
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}
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static void tcc8000_mask_irq0(unsigned int irq)
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{
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PIC0_IEN &= ~(1 << irq);
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}
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static void tcc8000_mask_irq1(unsigned int irq)
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{
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PIC1_IEN &= ~(1 << (irq - 32));
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}
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static void tcc8000_ack_irq0(unsigned int irq)
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{
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PIC0_CREQ |= (1 << irq);
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}
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static void tcc8000_ack_irq1(unsigned int irq)
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{
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PIC1_CREQ |= (1 << (irq - 32));
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}
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/* Enable IRQ */
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static void tcc8000_unmask_irq0(unsigned int irq)
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{
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PIC0_IEN |= (1 << irq);
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PIC0_INTOEN |= (1 << irq);
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}
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static void tcc8000_unmask_irq1(unsigned int irq)
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{
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PIC1_IEN |= (1 << (irq - 32));
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PIC1_INTOEN |= (1 << (irq - 32));
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}
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static struct irq_chip tcc8000_irq_chip0 = {
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.name = "tcc_irq0",
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.mask = tcc8000_mask_irq0,
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.ack = tcc8000_ack_irq0,
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.mask_ack = tcc8000_mask_ack_irq0,
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.unmask = tcc8000_unmask_irq0,
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};
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static struct irq_chip tcc8000_irq_chip1 = {
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.name = "tcc_irq1",
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.mask = tcc8000_mask_irq1,
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.ack = tcc8000_ack_irq1,
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.mask_ack = tcc8000_mask_ack_irq1,
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.unmask = tcc8000_unmask_irq1,
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};
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void __init tcc8k_init_irq(void)
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{
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int irqno;
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/* Mask and clear all interrupts */
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PIC0_IEN = 0x00000000;
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PIC0_CREQ = 0xffffffff;
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PIC1_IEN = 0x00000000;
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PIC1_CREQ = 0xffffffff;
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PIC0_MEN0 = 0x00000003;
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PIC1_MEN1 = 0x00000003;
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PIC1_MEN = 0x00000003;
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/* let all IRQs be level triggered */
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PIC0_TMODE = 0xffffffff;
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PIC1_TMODE = 0xffffffff;
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/* all IRQs are IRQs (not FIQs) */
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PIC0_IRQSEL = 0xffffffff;
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PIC1_IRQSEL = 0xffffffff;
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for (irqno = 0; irqno < NR_IRQS; irqno++) {
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if (irqno < 32)
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set_irq_chip(irqno, &tcc8000_irq_chip0);
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else
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set_irq_chip(irqno, &tcc8000_irq_chip1);
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set_irq_handler(irqno, handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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}
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@ -0,0 +1,83 @@
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/*
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* IRQ definitions for TCC8xxx
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*
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* Copyright (C) 2008-2009 Telechips
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* Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
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*
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* Licensed under the terms of the GPL v2.
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*
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*/
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#ifndef __ASM_ARCH_TCC_IRQS_H
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#define __ASM_ARCH_TCC_IRQS_H
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#define NR_IRQS 64
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/* PIC0 interrupts */
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#define INT_ADMA1 0
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#define INT_BDMA 1
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#define INT_ADMA0 2
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#define INT_GDMA1 3
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#define INT_I2S0RX 4
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#define INT_I2S0TX 5
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#define INT_TC 6
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#define INT_UART0 7
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#define INT_USBD 8
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#define INT_SPI0TX 9
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#define INT_UDMA 10
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#define INT_LIRQ 11
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#define INT_GDMA2 12
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#define INT_GDMA0 13
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#define INT_TC32 14
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#define INT_LCD 15
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#define INT_ADC 16
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#define INT_I2C 17
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#define INT_RTCP 18
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#define INT_RTCA 19
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#define INT_NFC 20
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#define INT_SD0 21
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#define INT_GSB0 22
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#define INT_PK 23
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#define INT_USBH0 24
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#define INT_USBH1 25
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#define INT_G2D 26
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#define INT_ECC 27
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#define INT_SPI0RX 28
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#define INT_UART1 29
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#define INT_MSCL 30
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#define INT_GSB1 31
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/* PIC1 interrupts */
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#define INT_E0 32
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#define INT_E1 33
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#define INT_E2 34
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#define INT_E3 35
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#define INT_E4 36
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#define INT_E5 37
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#define INT_E6 38
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#define INT_E7 39
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#define INT_UART2 40
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#define INT_UART3 41
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#define INT_SPI1TX 42
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#define INT_SPI1RX 43
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#define INT_GSB2 44
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#define INT_SPDIF 45
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#define INT_CDIF 46
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#define INT_VBON 47
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#define INT_VBOFF 48
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#define INT_SD1 49
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#define INT_UART4 50
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#define INT_GDMA3 51
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#define INT_I2S1RX 52
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#define INT_I2S1TX 53
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#define INT_CAN0 54
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#define INT_CAN1 55
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#define INT_GSB3 56
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#define INT_KRST 57
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#define INT_UNUSED 58
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#define INT_SD0D3 59
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#define INT_SD1D3 60
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#define INT_GPS0 61
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#define INT_GPS1 62
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#define INT_GPS2 63
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#endif /* ASM_ARCH_TCC_IRQS_H */
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