sl82c105: rework PIO support (take 2)
Get rid of the 'pio_speed' member of 'ide_drive_t' that was only used by this driver by storing the PIO mode timings in the 'drive_data' instead -- this allows us to greatly simplify the process of "reloading" of the chip's timing register and do it right in sl82c150_dma_off_quietly() and to get rid of two extra arguments to config_for_pio() -- which got renamed to sl82c105_tune_pio() and now returns a PIO mode selected, with ide_config_drive_speed() call moved into the tuneproc() method, now called sl82c105_tune_drive() with the code to set drive's 'io_32bit' and 'unmask' flags in its turn moved to its proper place in the init_hwif() method. Also, while at it, rename get_timing_sl82c105() into get_pio_timings() and get rid of the code in it clamping cycle counts to 32 which was both incorrect and never executed anyway... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Sergei Shtylyov
Bartlomiej Zolnierkiewicz
parent
62ea6d8021
commit
e93df705af
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@ -11,6 +11,8 @@
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* Merge in Russell's HW workarounds, fix various problems
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* with the timing registers setup.
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* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
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*
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
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*/
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#include <linux/types.h>
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@ -47,25 +49,19 @@
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#define CTRL_P0EN (1 << 0)
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/*
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* Convert a PIO mode and cycle time to the required on/off
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* times for the interface. This has protection against run-away
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* timings.
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* Convert a PIO mode and cycle time to the required on/off times
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* for the interface. This has protection against runaway timings.
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*/
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static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
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static unsigned int get_pio_timings(ide_pio_data_t *p)
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{
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unsigned int cmd_on;
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unsigned int cmd_off;
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unsigned int cmd_on, cmd_off;
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cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
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cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
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cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
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if (cmd_on > 32)
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cmd_on = 32;
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if (cmd_on == 0)
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cmd_on = 1;
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if (cmd_off > 32)
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cmd_off = 32;
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if (cmd_off == 0)
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cmd_off = 1;
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@ -73,44 +69,34 @@ static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
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}
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/*
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* Configure the drive and chipset for PIO
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* Configure the chipset for PIO mode.
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*/
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static void config_for_pio(ide_drive_t *drive, int pio, int report, int chipset_only)
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static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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ide_pio_data_t p;
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u16 drv_ctrl = 0x909;
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unsigned int xfer_mode, reg;
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u16 drv_ctrl;
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DBG(("config_for_pio(drive:%s, pio:%d, report:%d, chipset_only:%d)\n",
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drive->name, pio, report, chipset_only));
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reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
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DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));
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pio = ide_get_best_pio_mode(drive, pio, 5, &p);
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xfer_mode = XFER_PIO_0 + pio;
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drive->drive_data = drv_ctrl = get_pio_timings(&p);
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if (chipset_only || ide_config_drive_speed(drive, xfer_mode) == 0) {
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drv_ctrl = get_timing_sl82c105(&p);
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drive->pio_speed = xfer_mode;
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} else
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drive->pio_speed = XFER_PIO_0;
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if (drive->using_dma == 0) {
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if (!drive->using_dma) {
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/*
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* If we are actually using MW DMA, then we can not
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* reprogram the interface drive control register.
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*/
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pci_write_config_word(dev, reg, drv_ctrl);
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pci_read_config_word(dev, reg, &drv_ctrl);
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if (report) {
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printk("%s: selected %s (%dns) (%04X)\n", drive->name,
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ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
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}
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pci_write_config_word(dev, reg, drv_ctrl);
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pci_read_config_word (dev, reg, &drv_ctrl);
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}
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printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
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ide_xfer_verbose(pio + XFER_PIO_0), p.cycle_time, drv_ctrl);
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return pio;
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}
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/*
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@ -267,14 +253,14 @@ static int sl82c105_ide_dma_on (ide_drive_t *drive)
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static void sl82c105_dma_off_quietly(ide_drive_t *drive)
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{
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u8 speed = XFER_PIO_0;
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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int reg = 0x44 + drive->dn * 4;
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DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
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pci_write_config_word(dev, reg, drive->drive_data);
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ide_dma_off_quietly(drive);
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if (drive->pio_speed)
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speed = drive->pio_speed - XFER_PIO_0;
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config_for_pio(drive, speed, 0, 1);
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}
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/*
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@ -323,18 +309,12 @@ static void sl82c105_resetproc(ide_drive_t *drive)
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* We only deal with PIO mode here - DMA mode 'using_dma' is not
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* initialised at the point that this function is called.
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*/
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static void tune_sl82c105(ide_drive_t *drive, u8 pio)
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static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
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{
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DBG(("tune_sl82c105(drive:%s)\n", drive->name));
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DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));
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config_for_pio(drive, pio, 1, 0);
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/*
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* We support 32-bit I/O on this interface, and it
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* doesn't have problems with interrupts.
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*/
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drive->io_32bit = 1;
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drive->unmask = 1;
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pio = sl82c105_tune_pio(drive, pio);
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(void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
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}
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/*
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@ -401,19 +381,22 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
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DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
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hwif->tuneproc = tune_sl82c105;
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hwif->selectproc = sl82c105_selectproc;
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hwif->resetproc = sl82c105_resetproc;
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hwif->tuneproc = &sl82c105_tune_drive;
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hwif->selectproc = &sl82c105_selectproc;
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hwif->resetproc = &sl82c105_resetproc;
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/*
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* We support 32-bit I/O on this interface, and
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* it doesn't have problems with interrupts.
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*/
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hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
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hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
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/*
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* Default to PIO 0 for fallback unless tuned otherwise.
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* We always autotune PIO, this is done before DMA is checked,
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* so there's no risk of accidentally disabling DMA
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*/
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hwif->drives[0].pio_speed = XFER_PIO_0;
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hwif->drives[0].autotune = 1;
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hwif->drives[1].pio_speed = XFER_PIO_0;
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hwif->drives[1].autotune = 1;
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hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
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hwif->atapi_dma = 0;
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hwif->mwdma_mask = 0;
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@ -613,7 +613,6 @@ typedef struct ide_drive_s {
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u8 quirk_list; /* considered quirky, set for a specific host */
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u8 init_speed; /* transfer rate set at boot */
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u8 pio_speed; /* unused by core, used by some drivers for fallback from DMA */
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u8 current_speed; /* current transfer rate set */
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u8 desired_speed; /* desired transfer rate set */
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u8 dn; /* now wide spread use */
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