KVM: arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl
Userspace requires to store and restore of line_level for level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -191,6 +191,12 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
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#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
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#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
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#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
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(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
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#define VGIC_LEVEL_INFO_LINE_LEVEL 0
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#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
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@ -211,6 +211,12 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
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#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
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#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
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#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
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(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
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#define VGIC_LEVEL_INFO_LINE_LEVEL 0
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#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
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@ -512,6 +512,21 @@ static int vgic_v3_attr_regs_access(struct kvm_device *dev,
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regid, reg);
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break;
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}
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case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
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unsigned int info, intid;
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info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
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KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
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if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
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intid = attr->attr &
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KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
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ret = vgic_v3_line_level_info_uaccess(vcpu, is_write,
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intid, reg);
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} else {
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ret = -EINVAL;
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}
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break;
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}
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default:
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ret = -EINVAL;
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break;
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@ -554,6 +569,17 @@ static int vgic_v3_set_attr(struct kvm_device *dev,
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return vgic_v3_attr_regs_access(dev, attr, ®, true);
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}
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case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
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u32 __user *uaddr = (u32 __user *)(long)attr->addr;
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u64 reg;
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u32 tmp32;
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if (get_user(tmp32, uaddr))
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return -EFAULT;
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reg = tmp32;
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return vgic_v3_attr_regs_access(dev, attr, ®, true);
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}
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}
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return -ENXIO;
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}
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@ -589,8 +615,18 @@ static int vgic_v3_get_attr(struct kvm_device *dev,
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return ret;
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return put_user(reg, uaddr);
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}
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}
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case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
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u32 __user *uaddr = (u32 __user *)(long)attr->addr;
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u64 reg;
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u32 tmp32;
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ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
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if (ret)
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return ret;
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tmp32 = reg;
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return put_user(tmp32, uaddr);
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}
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}
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return -ENXIO;
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}
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@ -611,6 +647,13 @@ static int vgic_v3_has_attr(struct kvm_device *dev,
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return vgic_v3_has_attr_regs(dev, attr);
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case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
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return 0;
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case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
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if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
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KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
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VGIC_LEVEL_INFO_LINE_LEVEL)
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return 0;
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break;
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}
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case KVM_DEV_ARM_VGIC_GRP_CTRL:
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switch (attr->attr) {
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case KVM_DEV_ARM_VGIC_CTRL_INIT:
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@ -803,3 +803,17 @@ int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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else
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return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
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}
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int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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u32 intid, u64 *val)
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{
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if (intid % 32)
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return -EINVAL;
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if (is_write)
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vgic_write_irq_line_level_info(vcpu, intid, *val);
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else
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*val = vgic_read_irq_line_level_info(vcpu, intid);
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return 0;
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}
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@ -362,6 +362,60 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
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}
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}
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u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
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{
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int i;
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u64 val = 0;
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int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
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for (i = 0; i < 32; i++) {
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struct vgic_irq *irq;
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if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
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continue;
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irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
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val |= (1U << i);
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vgic_put_irq(vcpu->kvm, irq);
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}
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return val;
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}
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void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
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const u64 val)
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{
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int i;
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int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
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for (i = 0; i < 32; i++) {
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struct vgic_irq *irq;
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bool new_level;
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if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
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continue;
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irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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/*
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* Line level is set irrespective of irq type
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* (level or edge) to avoid dependency that VM should
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* restore irq config before line level.
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*/
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new_level = !!(val & (1U << i));
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spin_lock(&irq->irq_lock);
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irq->line_level = new_level;
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if (new_level)
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vgic_queue_irq_unlock(vcpu->kvm, irq);
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else
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spin_unlock(&irq->irq_lock);
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vgic_put_irq(vcpu->kvm, irq);
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}
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}
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static int match_region(const void *key, const void *elt)
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{
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const unsigned int offset = (unsigned long)key;
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@ -177,6 +177,11 @@ void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
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int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
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bool is_write, int offset, u32 *val);
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u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid);
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void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
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const u64 val);
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
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unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
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@ -164,6 +164,8 @@ int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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u64 id, u64 *val);
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int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
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u64 *reg);
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int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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u32 intid, u64 *val);
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int kvm_register_vgic_device(unsigned long type);
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void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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