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Merge branch 'sunxi/soc2' into next/soc 

From Maxime Ripard:

Here is a pull request to add the support for Allwinner A10 SoCs.

* sunxi/soc2:
  ARM: sunxi: Add sunxi restart function via onchip watchdog
  ARM: sunxi: Add sun4i and cubieboard support
  ARM: sunxi: Add earlyprintk support for UART0 (sun4i)
  ARM: sunxi: Restructure sunxi dts/dtsi files

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2012-11-21 10:52:05 -08:00
parent 41739b60b3 67bea88dd8
commit e9f6d13513
9 changed files with 186 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt Normal file
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@ -0,0 +1,13 @@
Allwinner sunXi Watchdog timer
Required properties:
- compatible : should be "allwinner,sunxi-wdt"
- reg : Specifies base physical address and size of the registers.
Example:
wdt: watchdog@01c20c90 {
compatible = "allwinner,sunxi-wdt";
reg = <0x01c20c90 0x10>;
};

9
arch/arm/Kconfig.debug
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@ -345,6 +345,13 @@ choice
Say Y here if you want kernel low-level debugging support
on SOCFPGA based platforms.
config DEBUG_SUNXI_UART0
bool "Kernel low-level debugging messages via sunXi UART0"
depends on ARCH_SUNXI
help
Say Y here if you want kernel low-level debugging support
on Allwinner A1X based platforms on the UART0.
config DEBUG_SUNXI_UART1
bool "Kernel low-level debugging messages via sunXi UART1"
depends on ARCH_SUNXI
@ -431,7 +438,7 @@ config DEBUG_LL_INCLUDE
default "debug/mvebu.S" if DEBUG_MVEBU_UART
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
default "debug/sunxi.S" if DEBUG_SUNXI_UART1
default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
default "mach/debug-macro.S"

3
arch/arm/boot/dts/Makefile
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@ -86,7 +86,8 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear310-evb.dtb \
spear320-evb.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \
sun5i-olinuxino.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \

38
arch/arm/boot/dts/sun4i-cubieboard.dts Normal file
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@ -0,0 +1,38 @@
/*
* Copyright 2012 Stefan Roese
* Stefan Roese <sr@denx.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun4i.dtsi"
/ {
model = "Cubietech Cubieboard";
compatible = "cubietech,cubieboard", "allwinner,sun4i";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
soc {
uart0: uart@01c28000 {
status = "okay";
};
uart1: uart@01c28400 {
status = "okay";
};
};
};

6
arch/arm/boot/dts/sun5i-olinuxino.dts
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@ -18,8 +18,12 @@
model = "Olimex A13-Olinuxino";
compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
soc {
duart: uart@01c28400 {
uart1: uart@01c28400 {
status = "okay";
};
};

56
arch/arm/boot/dts/sun5i.dtsi
View File

@ -11,64 +11,10 @@
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/include/ "sunxi.dtsi"
/ {
interrupt-parent = <&intc>;
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
};
};
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
memory {
reg = <0x40000000 0x20000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x01c20000 0x300000>;
ranges;
timer@01c20c00 {
compatible = "allwinner,sunxi-timer";
reg = <0x01c20c00 0x400>;
interrupts = <22>;
clocks = <&osc>;
};
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sunxi-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
uart1: uart@01c28400 {
compatible = "ns8250";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
clock-frequency = <24000000>;
status = "disabled";
};
};
};

80
arch/arm/boot/dts/sunxi.dtsi Normal file
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@ -0,0 +1,80 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&intc>;
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
};
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x01c20000 0x300000>;
ranges;
timer@01c20c00 {
compatible = "allwinner,sunxi-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
clocks = <&osc>;
};
wdt: watchdog@01c20c90 {
compatible = "allwinner,sunxi-wdt";
reg = <0x01c20c90 0x10>;
};
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sunxi-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
uart0: uart@01c28000 {
compatible = "ns8250";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
clock-frequency = <24000000>;
status = "disabled";
};
uart1: uart@01c28400 {
compatible = "ns8250";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
clock-frequency = <24000000>;
status = "disabled";
};
};
};

5
arch/arm/include/debug/sunxi.S
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@ -10,7 +10,10 @@
* published by the Free Software Foundation.
*/
#ifdef CONFIG_DEBUG_SUNXI_UART1
#if defined(CONFIG_DEBUG_SUNXI_UART0)
#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28000
#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28000
#elif defined(CONFIG_DEBUG_SUNXI_UART1)
#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28400
#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28400
#endif

35
arch/arm/mach-sunxi/sunxi.c
View File

@ -12,6 +12,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/io.h>
@ -26,6 +27,36 @@
#include "sunxi.h"
#define WATCHDOG_CTRL_REG 0x00
#define WATCHDOG_MODE_REG 0x04
static void __iomem *wdt_base;
static void sunxi_setup_restart(void)
{
struct device_node *np = of_find_compatible_node(NULL, NULL,
"allwinner,sunxi-wdt");
if (WARN(!np, "unable to setup watchdog restart"))
return;
wdt_base = of_iomap(np, 0);
WARN(!wdt_base, "failed to map watchdog base address");
}
static void sunxi_restart(char mode, const char *cmd)
{
if (!wdt_base)
return;
/* Enable timer and set reset bit in the watchdog */
writel(3, wdt_base + WATCHDOG_MODE_REG);
writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG);
while(1) {
mdelay(5);
writel(3, wdt_base + WATCHDOG_MODE_REG);
}
}
static struct map_desc sunxi_io_desc[] __initdata = {
{
.virtual = (unsigned long) SUNXI_REGS_VIRT_BASE,
@ -42,10 +73,13 @@ void __init sunxi_map_io(void)
static void __init sunxi_dt_init(void)
{
sunxi_setup_restart();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun4i",
"allwinner,sun5i",
NULL,
};
@ -55,6 +89,7 @@ DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
.map_io = sunxi_map_io,
.init_irq = sunxi_init_irq,
.handle_irq = sunxi_handle_irq,
.restart = sunxi_restart,
.timer = &sunxi_timer,
.dt_compat = sunxi_board_dt_compat,
MACHINE_END