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ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'. 

The 'big-endian-data' property is originally used to indicate whether the
LSB firstly or MSB firstly will be transmitted to the CODEC or received
from the CODEC, and there has nothing relation to the memory data.

Generally, if the audio data in big endian format, which will be using the
bytes reversion, Here this can only be used to bits reversion.

So using the 'lsb-first' instead of 'big-endian-data' can make the code
to be readable easier and more easy to understand what this property is
used to do.

This property used for configuring whether the LSB or the MSB is transmitted
first for the fifo data.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Xiubo Li 2014-08-29 15:12:12 +08:00 committed by Mark Brown
parent 025b78b809
commit eadb0019d2
3 changed files with 8 additions and 8 deletions
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8
Documentation/devicetree/bindings/sound/fsl-sai.txt
View File

@ -20,9 +20,9 @@ Required properties:
See ../pinctrl/pinctrl-bindings.txt for details of the property values. See ../pinctrl/pinctrl-bindings.txt for details of the property values.
- big-endian: Boolean property, required if all the FTM_PWM registers - big-endian: Boolean property, required if all the FTM_PWM registers
are big-endian rather than little-endian. are big-endian rather than little-endian.
- big-endian-data: If this property is absent, the little endian mode will - lsb-first: Configures whether the LSB or the MSB is transmitted first for
be in use as default, or the big endian mode will be in use for all the the fifo data. If this property is absent, the MSB is transmitted first as
fifo data. default, or the LSB is transmitted first.
- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
that SAI will work in the synchronous mode (sync Tx with Rx) which means that SAI will work in the synchronous mode (sync Tx with Rx) which means
both the transimitter and receiver will send and receive data by following both the transimitter and receiver will send and receive data by following
@ -53,5 +53,5 @@ sai2: sai@40031000 {
dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
big-endian; big-endian;
big-endian-data; lsb-first;
}; };

6
sound/soc/fsl/fsl_sai.c
View File

@ -175,7 +175,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
bool tx = fsl_dir == FSL_FMT_TRANSMITTER; bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
u32 val_cr2 = 0, val_cr4 = 0; u32 val_cr2 = 0, val_cr4 = 0;
if (!sai->big_endian_data) if (!sai->is_lsb_first)
val_cr4 |= FSL_SAI_CR4_MF; val_cr4 |= FSL_SAI_CR4_MF;
/* DAI mode */ /* DAI mode */
@ -304,7 +304,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
val_cr5 |= FSL_SAI_CR5_WNW(word_width); val_cr5 |= FSL_SAI_CR5_WNW(word_width);
val_cr5 |= FSL_SAI_CR5_W0W(word_width); val_cr5 |= FSL_SAI_CR5_W0W(word_width);
if (sai->big_endian_data) if (sai->is_lsb_first)
val_cr5 |= FSL_SAI_CR5_FBT(0); val_cr5 |= FSL_SAI_CR5_FBT(0);
else else
val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
@ -573,7 +573,7 @@ static int fsl_sai_probe(struct platform_device *pdev)
if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai")) if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
sai->sai_on_imx = true; sai->sai_on_imx = true;
sai->big_endian_data = of_property_read_bool(np, "big-endian-data"); sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res); base = devm_ioremap_resource(&pdev->dev, res);

2
sound/soc/fsl/fsl_sai.h
View File

@ -132,7 +132,7 @@ struct fsl_sai {
struct clk *bus_clk; struct clk *bus_clk;
struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
bool big_endian_data; bool is_lsb_first;
bool is_dsp_mode; bool is_dsp_mode;
bool sai_on_imx; bool sai_on_imx;
bool synchronous[2]; bool synchronous[2];