ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution
Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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Vineet Gupta
parent
72d7288061
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eaf0ecc33f
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@ -0,0 +1,46 @@
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* ARC-HS Interrupt Distribution Unit
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This optional 2nd level interrupt controller can be used in SMP configurations for
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dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
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Properties:
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- compatible: "snps,archs-idu-intc"
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- interrupt-controller: This is an interrupt controller.
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- interrupt-parent: <reference to parent core intc>
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- #interrupt-cells: Must be <2>.
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- interrupts: <...> specifies the upstream core irqs
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First cell specifies the "common" IRQ from peripheral to IDU
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Second cell specifies the irq distribution mode to cores
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0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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Example:
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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/*
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* <hwirq distribution>
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* distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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*/
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#interrupt-cells = <2>;
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/* upstream core irqs: downstream these are "COMMON" irq 0,1.. */
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interrupts = <24 25 26 27 28 29 30 31>;
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};
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some_device: serial@c0fc1000 {
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interrupt-parent = <&idu_intc>;
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interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */
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};
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@ -14,10 +14,10 @@
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#include <asm/mcip.h>
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static char smp_cpuinfo_buf[128];
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static int idu_detected;
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static DEFINE_RAW_SPINLOCK(mcip_lock);
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/*
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* Any SMP specific init any CPU does when it comes up.
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* Here we setup the CPU to enable Inter-Processor-Interrupts
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@ -150,6 +150,8 @@ void mcip_init_early_smp(void)
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IS_AVAIL1(mp.dbg, "DEBUG "),
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IS_AVAIL1(mp.grtc, "GRTC"));
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idu_detected = mp.idu;
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if (mp.dbg) {
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__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
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__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
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@ -158,3 +160,182 @@ void mcip_init_early_smp(void)
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if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
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panic("kernel trying to use non-existent GRTC\n");
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}
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/***************************************************************************
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* ARCv2 Interrupt Distribution Unit (IDU)
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*
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* Connects external "COMMON" IRQs to core intc, providing:
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* -dynamic routing (IRQ affinity)
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* -load balancing (Round Robin interrupt distribution)
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* -1:N distribution
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*
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* It physically resides in the MCIP hw block
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*/
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include "../../drivers/irqchip/irqchip.h"
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/*
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* Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
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*/
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static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
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{
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__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
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}
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static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
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unsigned int distr)
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{
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union {
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unsigned int word;
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struct {
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unsigned int distr:2, pad:2, lvl:1, pad2:27;
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};
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} data;
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data.distr = distr;
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data.lvl = lvl;
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__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
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}
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static void idu_irq_mask(struct irq_data *data)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void idu_irq_unmask(struct irq_data *data)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static int
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idu_irq_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool f)
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{
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return IRQ_SET_MASK_OK;
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}
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static struct irq_chip idu_irq_chip = {
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.name = "MCIP IDU Intc",
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.irq_mask = idu_irq_mask,
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.irq_unmask = idu_irq_unmask,
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#ifdef CONFIG_SMP
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.irq_set_affinity = idu_irq_set_affinity,
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#endif
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};
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static int idu_first_irq;
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static void idu_cascade_isr(unsigned int core_irq, struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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unsigned int idu_irq;
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idu_irq = core_irq - idu_first_irq;
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generic_handle_irq(irq_find_mapping(domain, idu_irq));
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}
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static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
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irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
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return 0;
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}
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static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type)
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{
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irq_hw_number_t hwirq = *out_hwirq = intspec[0];
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int distri = intspec[1];
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unsigned long flags;
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*out_type = IRQ_TYPE_NONE;
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/* XXX: validate distribution scheme again online cpu mask */
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if (distri == 0) {
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/* 0 - Round Robin to all cpus, otherwise 1 bit per core */
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raw_spin_lock_irqsave(&mcip_lock, flags);
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idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
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idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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} else {
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/*
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* DEST based distribution for Level Triggered intr can only
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* have 1 CPU, so generalize it to always contain 1 cpu
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*/
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int cpu = ffs(distri);
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if (cpu != fls(distri))
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pr_warn("IDU irq %lx distri mode set to cpu %x\n",
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hwirq, cpu);
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raw_spin_lock_irqsave(&mcip_lock, flags);
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idu_set_dest(hwirq, cpu);
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idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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return 0;
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}
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static const struct irq_domain_ops idu_irq_ops = {
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.xlate = idu_irq_xlate,
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.map = idu_irq_map,
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};
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/*
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* [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
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* [24, 23+C]: If C > 0 then "C" common IRQs
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* [24+C, N]: Not statically assigned, private-per-core
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*/
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static int __init
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idu_of_init(struct device_node *intc, struct device_node *parent)
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{
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struct irq_domain *domain;
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/* Read IDU BCR to confirm nr_irqs */
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int nr_irqs = of_irq_count(intc);
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int i, irq;
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if (!idu_detected)
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panic("IDU not detected, but DeviceTree using it");
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pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
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domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
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/* Parent interrupts (core-intc) are already mapped */
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for (i = 0; i < nr_irqs; i++) {
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/*
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* Return parent uplink IRQs (towards core intc) 24,25,.....
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* this step has been done before already
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* however we need it to get the parent virq and set IDU handler
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* as first level isr
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*/
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irq = irq_of_parse_and_map(intc, i);
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if (!i)
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idu_first_irq = irq;
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irq_set_handler_data(irq, domain);
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irq_set_chained_handler(irq, idu_cascade_isr);
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}
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__mcip_cmd(CMD_IDU_ENABLE, 0);
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return 0;
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}
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IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);
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