Documentation: x86: Contiguous cbm isn't all X86
Since commit 4d05bf71f1
("x86/resctrl: Introduce AMD QOS feature")
resctrl has supported non-contiguous cache bit masks. The interface
for this is currently try-it-and-see.
Update the documentation to say Intel CPUs have this requirement,
instead of X86.
Cc: Babu Moger <Babu.Moger@amd.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
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@ -342,7 +342,7 @@ For cache resources we describe the portion of the cache that is available
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for allocation using a bitmask. The maximum value of the mask is defined
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for allocation using a bitmask. The maximum value of the mask is defined
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by each cpu model (and may be different for different cache levels). It
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by each cpu model (and may be different for different cache levels). It
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is found using CPUID, but is also provided in the "info" directory of
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is found using CPUID, but is also provided in the "info" directory of
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the resctrl file system in "info/{resource}/cbm_mask". X86 hardware
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the resctrl file system in "info/{resource}/cbm_mask". Intel hardware
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requires that these masks have all the '1' bits in a contiguous block. So
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requires that these masks have all the '1' bits in a contiguous block. So
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0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9
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0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9
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and 0xA are not. On a system with a 20-bit mask each bit represents 5%
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and 0xA are not. On a system with a 20-bit mask each bit represents 5%
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