perf/x86: Fixes for Nehalem-EX uncore driver
This patch includes following fixes and update: - Only some events in the Sbox and Mbox can use the match/mask registers, add code to check this. - The format definitions for xbr_mm_cfg and xbr_match registers in the Rbox are wrong, xbr_mm_cfg should use 32 bits, xbr_match should use 64 bits. - Cleanup the Rbox code. Compute the addresses extra registers in the enable_event function instead of the hw_config function. This simplifies the code in nhmex_rbox_alter_er(). Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1344229882-3907-2-git-send-email-zheng.z.yan@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
parent
cffa59baa5
commit
ebb6cc0359
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@ -796,7 +796,6 @@ static struct intel_uncore_type *nhm_msr_uncores[] = {
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DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
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DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
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DEFINE_UNCORE_FORMAT_ATTR(mm_cfg, mm_cfg, "config:63");
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DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
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DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
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@ -1032,24 +1031,22 @@ static struct intel_uncore_type nhmex_uncore_bbox = {
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static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
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if (event->attr.config & NHMEX_S_PMON_MM_CFG_EN) {
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reg1->config = event->attr.config1;
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reg2->config = event->attr.config2;
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} else {
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reg1->config = ~0ULL;
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reg2->config = ~0ULL;
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}
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/* only TO_R_PROG_EV event uses the match/mask register */
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if ((hwc->config & NHMEX_PMON_CTL_EV_SEL_MASK) !=
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NHMEX_S_EVENT_TO_R_PROG_EV)
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return 0;
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if (box->pmu->pmu_idx == 0)
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reg1->reg = NHMEX_S0_MSR_MM_CFG;
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else
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reg1->reg = NHMEX_S1_MSR_MM_CFG;
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reg1->idx = 0;
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reg1->config = event->attr.config1;
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reg2->config = event->attr.config2;
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return 0;
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}
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@ -1059,8 +1056,8 @@ static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct per
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
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wrmsrl(reg1->reg, 0);
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if (reg1->config != ~0ULL || reg2->config != ~0ULL) {
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if (reg1->idx != EXTRA_REG_NONE) {
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wrmsrl(reg1->reg, 0);
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wrmsrl(reg1->reg + 1, reg1->config);
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wrmsrl(reg1->reg + 2, reg2->config);
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wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
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@ -1074,7 +1071,6 @@ static struct attribute *nhmex_uncore_sbox_formats_attr[] = {
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&format_attr_edge.attr,
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&format_attr_inv.attr,
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&format_attr_thresh8.attr,
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&format_attr_mm_cfg.attr,
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&format_attr_match.attr,
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&format_attr_mask.attr,
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NULL,
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@ -1264,7 +1260,8 @@ again:
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}
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/* for the match/mask registers */
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if ((uncore_box_is_fake(box) || !reg2->alloc) &&
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if (reg2->idx != EXTRA_REG_NONE &&
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(uncore_box_is_fake(box) || !reg2->alloc) &&
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!nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))
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goto fail;
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@ -1278,7 +1275,8 @@ again:
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if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))
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nhmex_mbox_alter_er(event, idx[0], true);
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reg1->alloc |= alloc;
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reg2->alloc = 1;
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if (reg2->idx != EXTRA_REG_NONE)
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reg2->alloc = 1;
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}
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return NULL;
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fail:
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@ -1342,9 +1340,6 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event
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struct extra_reg *er;
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unsigned msr;
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int reg_idx = 0;
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if (WARN_ON_ONCE(reg1->idx != -1))
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return -EINVAL;
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/*
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* The mbox events may require 2 extra MSRs at the most. But only
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* the lower 32 bits in these MSRs are significant, so we can use
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@ -1355,11 +1350,6 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event
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continue;
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if (event->attr.config1 & ~er->valid_mask)
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return -EINVAL;
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if (er->idx == __BITS_VALUE(reg1->idx, 0, 8) ||
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er->idx == __BITS_VALUE(reg1->idx, 1, 8))
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continue;
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if (WARN_ON_ONCE(reg_idx >= 2))
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return -EINVAL;
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msr = er->msr + type->msr_offset * box->pmu->pmu_idx;
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if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
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@ -1368,6 +1358,8 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event
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/* always use the 32~63 bits to pass the PLD config */
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if (er->idx == EXTRA_REG_NHMEX_M_PLD)
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reg_idx = 1;
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else if (WARN_ON_ONCE(reg_idx > 0))
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return -EINVAL;
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reg1->idx &= ~(0xff << (reg_idx * 8));
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reg1->reg &= ~(0xffff << (reg_idx * 16));
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@ -1376,17 +1368,21 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event
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reg1->config = event->attr.config1;
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reg_idx++;
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}
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/* use config2 to pass the filter config */
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reg2->idx = EXTRA_REG_NHMEX_M_FILTER;
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if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)
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reg2->config = event->attr.config2;
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else
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reg2->config = ~0ULL;
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if (box->pmu->pmu_idx == 0)
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reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;
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else
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reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;
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/*
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* The mbox only provides ability to perform address matching
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* for the PLD events.
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*/
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if (reg_idx == 2) {
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reg2->idx = EXTRA_REG_NHMEX_M_FILTER;
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if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)
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reg2->config = event->attr.config2;
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else
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reg2->config = ~0ULL;
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if (box->pmu->pmu_idx == 0)
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reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;
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else
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reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;
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}
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return 0;
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}
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@ -1422,34 +1418,36 @@ static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct per
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wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),
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nhmex_mbox_shared_reg_config(box, idx));
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wrmsrl(reg2->reg, 0);
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if (reg2->config != ~0ULL) {
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wrmsrl(reg2->reg + 1,
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reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK);
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wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &
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(reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));
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wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);
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if (reg2->idx != EXTRA_REG_NONE) {
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wrmsrl(reg2->reg, 0);
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if (reg2->config != ~0ULL) {
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wrmsrl(reg2->reg + 1,
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reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK);
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wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &
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(reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));
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wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);
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}
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}
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wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
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}
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DEFINE_UNCORE_FORMAT_ATTR(count_mode, count_mode, "config:2-3");
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DEFINE_UNCORE_FORMAT_ATTR(storage_mode, storage_mode, "config:4-5");
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DEFINE_UNCORE_FORMAT_ATTR(wrap_mode, wrap_mode, "config:6");
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DEFINE_UNCORE_FORMAT_ATTR(flag_mode, flag_mode, "config:7");
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DEFINE_UNCORE_FORMAT_ATTR(inc_sel, inc_sel, "config:9-13");
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DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel, set_flag_sel, "config:19-21");
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DEFINE_UNCORE_FORMAT_ATTR(filter_cfg, filter_cfg, "config2:63");
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DEFINE_UNCORE_FORMAT_ATTR(filter_match, filter_match, "config2:0-33");
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DEFINE_UNCORE_FORMAT_ATTR(filter_mask, filter_mask, "config2:34-61");
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DEFINE_UNCORE_FORMAT_ATTR(dsp, dsp, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(thr, thr, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(fvc, fvc, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(pgt, pgt, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(map, map, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(iss, iss, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(pld, pld, "config1:32-63");
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DEFINE_UNCORE_FORMAT_ATTR(count_mode, count_mode, "config:2-3");
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DEFINE_UNCORE_FORMAT_ATTR(storage_mode, storage_mode, "config:4-5");
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DEFINE_UNCORE_FORMAT_ATTR(wrap_mode, wrap_mode, "config:6");
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DEFINE_UNCORE_FORMAT_ATTR(flag_mode, flag_mode, "config:7");
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DEFINE_UNCORE_FORMAT_ATTR(inc_sel, inc_sel, "config:9-13");
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DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel, set_flag_sel, "config:19-21");
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DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en, filter_cfg_en, "config2:63");
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DEFINE_UNCORE_FORMAT_ATTR(filter_match, filter_match, "config2:0-33");
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DEFINE_UNCORE_FORMAT_ATTR(filter_mask, filter_mask, "config2:34-61");
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DEFINE_UNCORE_FORMAT_ATTR(dsp, dsp, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(thr, thr, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(fvc, fvc, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(pgt, pgt, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(map, map, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(iss, iss, "config1:0-31");
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DEFINE_UNCORE_FORMAT_ATTR(pld, pld, "config1:32-63");
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static struct attribute *nhmex_uncore_mbox_formats_attr[] = {
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&format_attr_count_mode.attr,
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@ -1458,7 +1456,7 @@ static struct attribute *nhmex_uncore_mbox_formats_attr[] = {
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&format_attr_flag_mode.attr,
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&format_attr_inc_sel.attr,
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&format_attr_set_flag_sel.attr,
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&format_attr_filter_cfg.attr,
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&format_attr_filter_cfg_en.attr,
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&format_attr_filter_match.attr,
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&format_attr_filter_mask.attr,
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&format_attr_dsp.attr,
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@ -1513,7 +1511,7 @@ void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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int port;
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/* adjust the main event selector */
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/* adjust the main event selector and extra register index */
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if (reg1->idx % 2) {
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reg1->idx--;
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hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
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@ -1522,29 +1520,17 @@ void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
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hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
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}
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/* adjust address or config of extra register */
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/* adjust extra register config */
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port = reg1->idx / 6 + box->pmu->pmu_idx * 4;
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switch (reg1->idx % 6) {
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case 0:
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reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG0(port);
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break;
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case 1:
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reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG1(port);
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break;
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case 2:
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/* the 8~15 bits to the 0~7 bits */
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/* shift the 8~15 bits to the 0~7 bits */
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reg1->config >>= 8;
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break;
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case 3:
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/* the 0~7 bits to the 8~15 bits */
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/* shift the 0~7 bits to the 8~15 bits */
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reg1->config <<= 8;
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break;
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case 4:
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reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port);
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break;
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case 5:
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reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port);
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break;
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};
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}
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@ -1671,7 +1657,7 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
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int port, idx;
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int idx;
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idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>
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NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
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@ -1681,27 +1667,11 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event
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reg1->idx = idx;
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reg1->config = event->attr.config1;
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port = idx / 6 + box->pmu->pmu_idx * 4;
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idx %= 6;
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switch (idx) {
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case 0:
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reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG0(port);
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break;
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case 1:
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reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG1(port);
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break;
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case 2:
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case 3:
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reg1->reg = NHMEX_R_MSR_PORTN_QLX_CFG(port);
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break;
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switch (idx % 6) {
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case 4:
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case 5:
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if (idx == 4)
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reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port);
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else
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reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port);
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reg2->config = event->attr.config2;
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hwc->config |= event->attr.config & (~0ULL << 32);
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reg2->config = event->attr.config2;
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break;
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};
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return 0;
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@ -1727,28 +1697,34 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
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int idx, er_idx;
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int idx, port;
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idx = reg1->idx % 6;
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er_idx = idx;
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if (er_idx > 2)
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er_idx--;
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er_idx += (reg1->idx / 6) * 5;
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idx = reg1->idx;
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port = idx / 6 + box->pmu->pmu_idx * 4;
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switch (idx) {
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switch (idx % 6) {
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case 0:
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wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);
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break;
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case 1:
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wrmsrl(reg1->reg, reg1->config);
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wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);
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break;
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case 2:
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case 3:
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wrmsrl(reg1->reg, nhmex_rbox_shared_reg_config(box, er_idx));
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wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),
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nhmex_rbox_shared_reg_config(box, 2 + (idx / 6) * 5));
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break;
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case 4:
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),
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hwc->config >> 32);
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config);
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break;
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case 5:
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wrmsrl(reg1->reg, reg1->config);
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wrmsrl(reg1->reg + 1, hwc->config >> 32);
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wrmsrl(reg1->reg + 2, reg2->config);
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port),
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hwc->config >> 32);
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
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break;
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};
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@ -1756,8 +1732,8 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per
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(hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
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}
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DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config:32-63");
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DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config1:0-63");
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DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config:32-63");
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DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config1:0-63");
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DEFINE_UNCORE_FORMAT_ATTR(xbr_mask, xbr_mask, "config2:0-63");
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DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg, qlx_cfg, "config1:0-15");
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||||
DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg, iperf_cfg, "config1:0-31");
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||||
|
@ -2303,6 +2279,7 @@ int uncore_pmu_event_init(struct perf_event *event)
|
|||
event->hw.idx = -1;
|
||||
event->hw.last_tag = ~0ULL;
|
||||
event->hw.extra_reg.idx = EXTRA_REG_NONE;
|
||||
event->hw.branch_reg.idx = EXTRA_REG_NONE;
|
||||
|
||||
if (event->attr.config == UNCORE_FIXED_EVENT) {
|
||||
/* no fixed counter */
|
||||
|
|
|
@ -230,6 +230,7 @@
|
|||
#define NHMEX_S1_MSR_MASK 0xe5a
|
||||
|
||||
#define NHMEX_S_PMON_MM_CFG_EN (0x1ULL << 63)
|
||||
#define NHMEX_S_EVENT_TO_R_PROG_EV 0
|
||||
|
||||
/* NHM-EX Mbox */
|
||||
#define NHMEX_M0_MSR_GLOBAL_CTL 0xca0
|
||||
|
|
Loading…
Reference in New Issue