mxc timer: make compile time independent
Currently we depend on hardcoded base addresses for the timer. This prevents us from compiling in more than one i.MX architecture at a time. This patch changes the base address to a runtime calculated one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
cd4a05f9df
commit
ec996ba9b5
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@ -1,158 +0,0 @@
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/*
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* mxc_timer.h
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*
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* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
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*
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* Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __PLAT_MXC_TIMER_H
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#define __PLAT_MXC_TIMER_H
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#include <linux/clk.h>
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#include <mach/hardware.h>
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#ifdef CONFIG_ARCH_MX1
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#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
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#define TIMER_INTERRUPT TIM1_INT
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#define TCTL_VAL TCTL_CLK_PCLK1
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#define TCTL_IRQEN (1<<4)
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#define TCTL_FRR (1<<8)
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#define TCTL_CLK_PCLK1 (1<<1)
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#define TCTL_CLK_PCLK1_4 (2<<1)
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#define TCTL_CLK_TIN (3<<1)
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#define TCTL_CLK_32 (4<<1)
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#define MXC_TCTL 0x00
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#define MXC_TPRER 0x04
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#define MXC_TCMP 0x08
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#define MXC_TCR 0x0c
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#define MXC_TCN 0x10
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#define MXC_TSTAT 0x14
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#define TSTAT_CAPT (1<<1)
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#define TSTAT_COMP (1<<0)
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static inline void gpt_irq_disable(void)
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{
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unsigned int tmp;
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tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
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__raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
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}
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static inline void gpt_irq_enable(void)
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{
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__raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
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TIMER_BASE + MXC_TCTL);
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}
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static void gpt_irq_acknowledge(void)
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{
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__raw_writel(0, TIMER_BASE + MXC_TSTAT);
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}
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#endif /* CONFIG_ARCH_MX1 */
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#ifdef CONFIG_ARCH_MX2
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#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
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#define TIMER_INTERRUPT MXC_INT_GPT1
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#define MXC_TCTL 0x00
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#define TCTL_VAL TCTL_CLK_PCLK1
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#define TCTL_CLK_PCLK1 (1<<1)
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#define TCTL_CLK_PCLK1_4 (2<<1)
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#define TCTL_IRQEN (1<<4)
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#define TCTL_FRR (1<<8)
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#define MXC_TPRER 0x04
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#define MXC_TCMP 0x08
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#define MXC_TCR 0x0c
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#define MXC_TCN 0x10
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#define MXC_TSTAT 0x14
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#define TSTAT_CAPT (1<<1)
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#define TSTAT_COMP (1<<0)
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static inline void gpt_irq_disable(void)
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{
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unsigned int tmp;
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tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
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__raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
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}
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static inline void gpt_irq_enable(void)
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{
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__raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
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TIMER_BASE + MXC_TCTL);
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}
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static void gpt_irq_acknowledge(void)
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{
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__raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
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}
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#endif /* CONFIG_ARCH_MX2 */
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#ifdef CONFIG_ARCH_MX3
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#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
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#define TIMER_INTERRUPT MXC_INT_GPT
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#define MXC_TCTL 0x00
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#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN)
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#define TCTL_CLK_IPG (1<<6)
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#define TCTL_FRR (1<<9)
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#define TCTL_WAITEN (1<<3)
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#define MXC_TPRER 0x04
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#define MXC_TSTAT 0x08
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#define TSTAT_OF1 (1<<0)
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#define TSTAT_OF2 (1<<1)
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#define TSTAT_OF3 (1<<2)
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#define TSTAT_IF1 (1<<3)
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#define TSTAT_IF2 (1<<4)
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#define TSTAT_ROV (1<<5)
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#define MXC_IR 0x0c
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#define MXC_TCMP 0x10
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#define MXC_TCMP2 0x14
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#define MXC_TCMP3 0x18
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#define MXC_TCR 0x1c
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#define MXC_TCN 0x24
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static inline void gpt_irq_disable(void)
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{
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__raw_writel(0, TIMER_BASE + MXC_IR);
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}
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static inline void gpt_irq_enable(void)
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{
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__raw_writel(1<<0, TIMER_BASE + MXC_IR);
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}
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static inline void gpt_irq_acknowledge(void)
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{
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__raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
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}
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#endif /* CONFIG_ARCH_MX3 */
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#define TCTL_SWR (1<<15)
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#define TCTL_CC (1<<10)
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#define TCTL_OM (1<<9)
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#define TCTL_CAP_RIS (1<<6)
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#define TCTL_CAP_FAL (2<<6)
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#define TCTL_CAP_RIS_FAL (3<<6)
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#define TCTL_CAP_ENA (1<<5)
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#define TCTL_TEN (1<<0)
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#endif
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@ -29,22 +29,85 @@
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#include <mach/hardware.h>
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#include <asm/mach/time.h>
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#include <mach/common.h>
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#include <mach/mxc_timer.h>
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/* defines common for all i.MX */
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#define MXC_TCTL 0x00
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#define MXC_TCTL_TEN (1 << 0)
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#define MXC_TPRER 0x04
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/* MX1, MX21, MX27 */
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#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
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#define MX1_2_TCTL_IRQEN (1 << 4)
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#define MX1_2_TCTL_FRR (1 << 8)
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#define MX1_2_TCMP 0x08
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#define MX1_2_TCN 0x10
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#define MX1_2_TSTAT 0x14
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/* MX21, MX27 */
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#define MX2_TSTAT_CAPT (1 << 1)
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#define MX2_TSTAT_COMP (1 << 0)
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/* MX31, MX35 */
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#define MX3_TCTL_WAITEN (1 << 3)
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#define MX3_TCTL_CLK_IPG (1 << 6)
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#define MX3_TCTL_FRR (1 << 9)
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#define MX3_IR 0x0c
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#define MX3_TSTAT 0x08
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#define MX3_TSTAT_OF1 (1 << 0)
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#define MX3_TCN 0x24
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#define MX3_TCMP 0x10
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static struct clock_event_device clockevent_mxc;
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static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
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/* clock source */
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static void __iomem *timer_base;
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static cycle_t mxc_get_cycles(struct clocksource *cs)
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static inline void gpt_irq_disable(void)
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{
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return __raw_readl(TIMER_BASE + MXC_TCN);
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unsigned int tmp;
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if (cpu_is_mx3())
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__raw_writel(0, timer_base + MX3_IR);
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else {
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tmp = __raw_readl(timer_base + MXC_TCTL);
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__raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
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}
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}
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static inline void gpt_irq_enable(void)
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{
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if (cpu_is_mx3())
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__raw_writel(1<<0, timer_base + MX3_IR);
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else {
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__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
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timer_base + MXC_TCTL);
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}
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}
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static void gpt_irq_acknowledge(void)
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{
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if (cpu_is_mx1())
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__raw_writel(0, timer_base + MX1_2_TSTAT);
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if (cpu_is_mx2())
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__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
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if (cpu_is_mx3())
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__raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
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}
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static cycle_t mx1_2_get_cycles(struct clocksource *cs)
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{
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return __raw_readl(timer_base + MX1_2_TCN);
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}
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static cycle_t mx3_get_cycles(struct clocksource *cs)
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{
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return __raw_readl(timer_base + MX3_TCN);
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}
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static struct clocksource clocksource_mxc = {
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.name = "mxc_timer1",
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.rating = 200,
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.read = mxc_get_cycles,
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.read = mx1_2_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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@ -54,6 +117,9 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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if (cpu_is_mx3())
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clocksource_mxc.read = mx3_get_cycles;
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clocksource_mxc.mult = clocksource_hz2mult(c,
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clocksource_mxc.shift);
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clocksource_register(&clocksource_mxc);
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@ -63,15 +129,29 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
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/* clock event */
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static int mxc_set_next_event(unsigned long evt,
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static int mx1_2_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long tcmp;
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tcmp = __raw_readl(TIMER_BASE + MXC_TCN) + evt;
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__raw_writel(tcmp, TIMER_BASE + MXC_TCMP);
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tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
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return (int)(tcmp - __raw_readl(TIMER_BASE + MXC_TCN)) < 0 ?
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__raw_writel(tcmp, timer_base + MX1_2_TCMP);
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return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
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-ETIME : 0;
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}
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static int mx3_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long tcmp;
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tcmp = __raw_readl(timer_base + MX3_TCN) + evt;
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__raw_writel(tcmp, timer_base + MX3_TCMP);
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return (int)(tcmp - __raw_readl(timer_base + MX3_TCN)) < 0 ?
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-ETIME : 0;
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}
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@ -100,8 +180,13 @@ static void mxc_set_mode(enum clock_event_mode mode,
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if (mode != clockevent_mode) {
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/* Set event time into far-far future */
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__raw_writel(__raw_readl(TIMER_BASE + MXC_TCN) - 3,
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TIMER_BASE + MXC_TCMP);
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if (cpu_is_mx3())
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__raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
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timer_base + MX3_TCMP);
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else
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__raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
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timer_base + MX1_2_TCMP);
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/* Clear pending interrupt */
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gpt_irq_acknowledge();
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}
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@ -148,7 +233,10 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
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struct clock_event_device *evt = &clockevent_mxc;
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uint32_t tstat;
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tstat = __raw_readl(TIMER_BASE + MXC_TSTAT);
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if (cpu_is_mx3())
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tstat = __raw_readl(timer_base + MX1_2_TSTAT);
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else
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tstat = __raw_readl(timer_base + MX3_TSTAT);
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gpt_irq_acknowledge();
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@ -168,7 +256,7 @@ static struct clock_event_device clockevent_mxc = {
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_mode = mxc_set_mode,
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.set_next_event = mxc_set_next_event,
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.set_next_event = mx1_2_set_next_event,
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.rating = 200,
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};
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@ -176,6 +264,9 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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if (cpu_is_mx3())
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clockevent_mxc.set_next_event = mx3_set_next_event;
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clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
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clockevent_mxc.shift);
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clockevent_mxc.max_delta_ns =
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@ -192,23 +283,47 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
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void __init mxc_timer_init(struct clk *timer_clk)
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{
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uint32_t tctl_val;
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int irq;
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clk_enable(timer_clk);
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if (cpu_is_mx1()) {
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#ifdef CONFIG_ARCH_MX1
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timer_base = IO_ADDRESS(TIM1_BASE_ADDR);
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irq = TIM1_INT;
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#endif
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} else if (cpu_is_mx2()) {
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#ifdef CONFIG_ARCH_MX2
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timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
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irq = MXC_INT_GPT1;
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#endif
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} else if (cpu_is_mx3()) {
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#ifdef CONFIG_ARCH_MX3
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timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
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irq = MXC_INT_GPT;
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#endif
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} else
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BUG();
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/*
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* Initialise to a known state (all timers off, and timing reset)
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*/
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__raw_writel(0, TIMER_BASE + MXC_TCTL);
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__raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */
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__raw_writel(TCTL_FRR | /* free running */
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TCTL_VAL | /* set clocksource and arch specific bits */
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TCTL_TEN, /* start the timer */
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TIMER_BASE + MXC_TCTL);
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__raw_writel(0, timer_base + MXC_TCTL);
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__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
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if (cpu_is_mx3())
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tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
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else
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tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
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__raw_writel(tctl_val, timer_base + MXC_TCTL);
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/* init and register the timer to the framework */
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mxc_clocksource_init(timer_clk);
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mxc_clockevent_init(timer_clk);
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/* Make irqs happen */
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setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
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setup_irq(irq, &mxc_timer_irq);
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}
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