x86: use symbolic constants for MSR_IA32_MISC_ENABLE bits
Impact: Cleanup. No functional changes. Signed-off-by: Vegard Nossum <vegard.nossum@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -204,12 +204,12 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
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}
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/* Enable Enhanced PowerSaver */
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rdmsrl(MSR_IA32_MISC_ENABLE, val);
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if (!(val & 1 << 16)) {
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val |= 1 << 16;
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if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
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val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
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wrmsrl(MSR_IA32_MISC_ENABLE, val);
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/* Can be locked at 0 */
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rdmsrl(MSR_IA32_MISC_ENABLE, val);
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if (!(val & 1 << 16)) {
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if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
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printk(KERN_INFO "eps: Can't enable Enhanced PowerSaver\n");
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return -ENODEV;
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}
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@ -390,14 +390,14 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
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enable it if not. */
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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if (!(l & (1<<16))) {
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l |= (1<<16);
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if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
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l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
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dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
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wrmsr(MSR_IA32_MISC_ENABLE, l, h);
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/* check to see if it stuck */
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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if (!(l & (1<<16))) {
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if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
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printk(KERN_INFO PFX
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"couldn't enable Enhanced SpeedStep\n");
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return -ENODEV;
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@ -147,10 +147,10 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
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*/
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if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
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rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
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if ((lo & (1<<9)) == 0) {
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if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
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printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
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printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
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lo |= (1<<9); /* Disable hw prefetching */
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lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
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wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
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}
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}
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@ -49,13 +49,13 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
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*/
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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h = apic_read(APIC_LVTTHMR);
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if ((l & (1 << 3)) && (h & APIC_DM_SMI)) {
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if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
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printk(KERN_DEBUG
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"CPU%d: Thermal monitoring handled by SMI\n", cpu);
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return;
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}
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if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13)))
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if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
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tm2 = 1;
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if (h & APIC_VECTOR_MASK) {
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@ -73,7 +73,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
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wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
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wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
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l = apic_read(APIC_LVTTHMR);
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apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
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@ -85,7 +85,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
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*/
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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h = apic_read(APIC_LVTTHMR);
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if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
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if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
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printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
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cpu);
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return; /* -EBUSY */
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@ -111,7 +111,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
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vendor_thermal_interrupt = intel_thermal_interrupt;
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
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wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
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l = apic_read(APIC_LVTTHMR);
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apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
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