Merge remote-tracking branch 'pci/pci/gavin-window-alignment' into next
Merge Gavin patches from the PCI tree as subsequent powerpc patches are going to depend on them Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
commit
eda485f06d
|
@ -210,3 +210,15 @@ Users:
|
|||
firmware assigned instance number of the PCI
|
||||
device that can help in understanding the firmware
|
||||
intended order of the PCI device.
|
||||
|
||||
What: /sys/bus/pci/devices/.../d3cold_allowed
|
||||
Date: July 2012
|
||||
Contact: Huang Ying <ying.huang@intel.com>
|
||||
Description:
|
||||
d3cold_allowed is bit to control whether the corresponding PCI
|
||||
device can be put into D3Cold state. If it is cleared, the
|
||||
device will never be put into D3Cold state. If it is set, the
|
||||
device may be put into D3Cold state if other requirements are
|
||||
satisfied too. Reading this attribute will show the current
|
||||
value of d3cold_allowed bit. Writing this attribute will set
|
||||
the value of d3cold_allowed bit.
|
||||
|
|
|
@ -579,7 +579,7 @@ Why: KVM tracepoints provide mostly equivalent information in a much more
|
|||
----------------------------
|
||||
|
||||
What: at91-mci driver ("CONFIG_MMC_AT91")
|
||||
When: 3.7
|
||||
When: 3.8
|
||||
Why: There are two mci drivers: at91-mci and atmel-mci. The PDC support
|
||||
was added to atmel-mci as a first step to support more chips.
|
||||
Then at91-mci was kept only for old IP versions (on at91rm9200 and
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -6,7 +6,7 @@ config ARM
|
|||
select HAVE_DMA_API_DEBUG
|
||||
select HAVE_IDE if PCI || ISA || PCMCIA
|
||||
select HAVE_DMA_ATTRS
|
||||
select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
|
||||
select HAVE_DMA_CONTIGUOUS if MMU
|
||||
select HAVE_MEMBLOCK
|
||||
select RTC_LIB
|
||||
select SYS_SUPPORTS_APM_EMULATION
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||
};
|
||||
|
||||
ahb {
|
||||
|
|
|
@ -33,7 +33,7 @@ CONFIG_AEABI=y
|
|||
CONFIG_FORCE_MAX_ZONEORDER=13
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"
|
||||
CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"
|
||||
CONFIG_CMDLINE_FORCE=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_VFP=y
|
||||
|
|
|
@ -202,6 +202,13 @@ static inline void dma_free_writecombine(struct device *dev, size_t size,
|
|||
return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
|
||||
}
|
||||
|
||||
/*
|
||||
* This can be called during early boot to increase the size of the atomic
|
||||
* coherent DMA pool above the default value of 256KiB. It must be called
|
||||
* before postcore_initcall.
|
||||
*/
|
||||
extern void __init init_dma_coherent_pool_size(unsigned long size);
|
||||
|
||||
/*
|
||||
* This can be called during boot to increase the size of the consistent
|
||||
* DMA region above it's default value of 2MB. It must be called before the
|
||||
|
|
|
@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void)
|
|||
at91_st_read(AT91_ST_SR);
|
||||
|
||||
/* Make IRQs happen for the system timer */
|
||||
setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
|
||||
setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
|
||||
|
||||
/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
|
||||
* directly for the clocksource and all clockevents, after adjusting
|
||||
|
|
|
@ -726,6 +726,8 @@ static struct resource rtt_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -744,10 +746,12 @@ static void __init at91_add_device_rtt_rtc(void)
|
|||
* The second resource is needed:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9260_rtt_device.num_resources = 2;
|
||||
at91sam9260_rtt_device.num_resources = 3;
|
||||
rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
|
||||
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
|
|
@ -609,6 +609,8 @@ static struct resource rtt_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -626,10 +628,12 @@ static void __init at91_add_device_rtt_rtc(void)
|
|||
* The second resource is needed:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9261_rtt_device.num_resources = 2;
|
||||
at91sam9261_rtt_device.num_resources = 3;
|
||||
rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
|
||||
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
|
|
@ -990,6 +990,8 @@ static struct resource rtt0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -1006,6 +1008,8 @@ static struct resource rtt1_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -1027,14 +1031,14 @@ static void __init at91_add_device_rtt_rtc(void)
|
|||
* The second resource is needed only for the chosen RTT:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9263_rtt0_device.num_resources = 2;
|
||||
at91sam9263_rtt0_device.num_resources = 3;
|
||||
at91sam9263_rtt1_device.num_resources = 1;
|
||||
pdev = &at91sam9263_rtt0_device;
|
||||
r = rtt0_resources;
|
||||
break;
|
||||
case 1:
|
||||
at91sam9263_rtt0_device.num_resources = 1;
|
||||
at91sam9263_rtt1_device.num_resources = 2;
|
||||
at91sam9263_rtt1_device.num_resources = 3;
|
||||
pdev = &at91sam9263_rtt1_device;
|
||||
r = rtt1_resources;
|
||||
break;
|
||||
|
@ -1047,6 +1051,8 @@ static void __init at91_add_device_rtt_rtc(void)
|
|||
pdev->name = "rtc-at91sam9";
|
||||
r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
r[1].end = r[1].start + 3;
|
||||
r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
|
|
@ -1293,6 +1293,8 @@ static struct resource rtt_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -1310,10 +1312,12 @@ static void __init at91_add_device_rtt_rtc(void)
|
|||
* The second resource is needed:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9g45_rtt_device.num_resources = 2;
|
||||
at91sam9g45_rtt_device.num_resources = 3;
|
||||
rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
|
||||
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
|
|
@ -688,6 +688,8 @@ static struct resource rtt_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -705,10 +707,12 @@ static void __init at91_add_device_rtt_rtc(void)
|
|||
* The second resource is needed:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9rl_rtt_device.num_resources = 2;
|
||||
at91sam9rl_rtt_device.num_resources = 3;
|
||||
rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
|
||||
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
|
|
@ -63,6 +63,12 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
|
|||
|
||||
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
||||
|
||||
#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
|
||||
|| cpu_is_at91sam9263() \
|
||||
|| cpu_is_at91sam9rl())
|
||||
|
||||
#define cpu_has_210M_plla() (cpu_is_at91sam9260())
|
||||
|
||||
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|
@ -706,6 +712,12 @@ static int __init at91_pmc_init(unsigned long main_clock)
|
|||
} else if (cpu_has_800M_plla()) {
|
||||
if (plla.rate_hz > 800000000)
|
||||
pll_overclock = true;
|
||||
} else if (cpu_has_240M_plla()) {
|
||||
if (plla.rate_hz > 240000000)
|
||||
pll_overclock = true;
|
||||
} else if (cpu_has_210M_plla()) {
|
||||
if (plla.rate_hz > 210000000)
|
||||
pll_overclock = true;
|
||||
} else {
|
||||
if (plla.rate_hz > 209000000)
|
||||
pll_overclock = true;
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/sched.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/system_misc.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define IRQ_SOURCE(base_addr) (base_addr + 0x00)
|
||||
|
|
|
@ -517,6 +517,13 @@ void __init kirkwood_wdt_init(void)
|
|||
void __init kirkwood_init_early(void)
|
||||
{
|
||||
orion_time_set_base(TIMER_VIRT_BASE);
|
||||
|
||||
/*
|
||||
* Some Kirkwood devices allocate their coherent buffers from atomic
|
||||
* context. Increase size of atomic coherent pool to make sure such
|
||||
* the allocations won't fail.
|
||||
*/
|
||||
init_dma_coherent_pool_size(SZ_1M);
|
||||
}
|
||||
|
||||
int kirkwood_tclk;
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/ata_platform.h>
|
||||
|
|
|
@ -520,13 +520,14 @@ static struct platform_device hdmi_lcdc_device = {
|
|||
};
|
||||
|
||||
/* GPIO KEY */
|
||||
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
|
||||
#define GPIO_KEY(c, g, d, ...) \
|
||||
{ .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
|
||||
|
||||
static struct gpio_keys_button gpio_buttons[] = {
|
||||
GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW1"),
|
||||
GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW2"),
|
||||
GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW3"),
|
||||
GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW4"),
|
||||
GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1),
|
||||
GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"),
|
||||
GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"),
|
||||
GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"),
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data gpio_key_info = {
|
||||
|
@ -901,8 +902,8 @@ static struct platform_device *eva_devices[] __initdata = {
|
|||
&camera_device,
|
||||
&ceu0_device,
|
||||
&fsi_device,
|
||||
&fsi_hdmi_device,
|
||||
&fsi_wm8978_device,
|
||||
&fsi_hdmi_device,
|
||||
};
|
||||
|
||||
static void __init eva_clock_init(void)
|
||||
|
|
|
@ -695,6 +695,7 @@ static struct platform_device usbhs0_device = {
|
|||
* - J30 "open"
|
||||
* - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
|
||||
* - add .get_vbus = usbhs_get_vbus in usbhs1_private
|
||||
* - check usbhs0_device(pio)/usbhs1_device(irq) order in mackerel_devices.
|
||||
*/
|
||||
#define IRQ8 evt2irq(0x0300)
|
||||
#define USB_PHY_MODE (1 << 4)
|
||||
|
@ -1325,8 +1326,8 @@ static struct platform_device *mackerel_devices[] __initdata = {
|
|||
&nor_flash_device,
|
||||
&smc911x_device,
|
||||
&lcdc_device,
|
||||
&usbhs1_device,
|
||||
&usbhs0_device,
|
||||
&usbhs1_device,
|
||||
&leds_device,
|
||||
&fsi_device,
|
||||
&fsi_ak4643_device,
|
||||
|
|
|
@ -67,7 +67,7 @@ static struct smsc911x_platform_config smsc911x_platdata = {
|
|||
|
||||
static struct platform_device eth_device = {
|
||||
.name = "smsc911x",
|
||||
.id = 0,
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_platdata,
|
||||
},
|
||||
|
|
|
@ -259,9 +259,9 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
|
|||
return 0; /* always allow wakeup */
|
||||
}
|
||||
|
||||
#define RELOC_BASE 0x1000
|
||||
#define RELOC_BASE 0x1200
|
||||
|
||||
/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */
|
||||
/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
|
||||
#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
|
||||
|
||||
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
|
||||
|
|
|
@ -367,17 +367,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
|
|||
/* Tegra PCIE requires relaxed ordering */
|
||||
static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
|
||||
{
|
||||
u16 val16;
|
||||
int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
||||
|
||||
if (pos <= 0) {
|
||||
dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
|
||||
val16 |= PCI_EXP_DEVCTL_RELAX_EN;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
|
||||
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
|
||||
|
||||
|
|
|
@ -267,17 +267,19 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
|
|||
vunmap(cpu_addr);
|
||||
}
|
||||
|
||||
#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
|
||||
|
||||
struct dma_pool {
|
||||
size_t size;
|
||||
spinlock_t lock;
|
||||
unsigned long *bitmap;
|
||||
unsigned long nr_pages;
|
||||
void *vaddr;
|
||||
struct page *page;
|
||||
struct page **pages;
|
||||
};
|
||||
|
||||
static struct dma_pool atomic_pool = {
|
||||
.size = SZ_256K,
|
||||
.size = DEFAULT_DMA_COHERENT_POOL_SIZE,
|
||||
};
|
||||
|
||||
static int __init early_coherent_pool(char *p)
|
||||
|
@ -287,6 +289,21 @@ static int __init early_coherent_pool(char *p)
|
|||
}
|
||||
early_param("coherent_pool", early_coherent_pool);
|
||||
|
||||
void __init init_dma_coherent_pool_size(unsigned long size)
|
||||
{
|
||||
/*
|
||||
* Catch any attempt to set the pool size too late.
|
||||
*/
|
||||
BUG_ON(atomic_pool.vaddr);
|
||||
|
||||
/*
|
||||
* Set architecture specific coherent pool size only if
|
||||
* it has not been changed by kernel command line parameter.
|
||||
*/
|
||||
if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
|
||||
atomic_pool.size = size;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialise the coherent pool for atomic allocations.
|
||||
*/
|
||||
|
@ -297,6 +314,7 @@ static int __init atomic_pool_init(void)
|
|||
unsigned long nr_pages = pool->size >> PAGE_SHIFT;
|
||||
unsigned long *bitmap;
|
||||
struct page *page;
|
||||
struct page **pages;
|
||||
void *ptr;
|
||||
int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
|
||||
|
||||
|
@ -304,21 +322,31 @@ static int __init atomic_pool_init(void)
|
|||
if (!bitmap)
|
||||
goto no_bitmap;
|
||||
|
||||
pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
|
||||
if (!pages)
|
||||
goto no_pages;
|
||||
|
||||
if (IS_ENABLED(CONFIG_CMA))
|
||||
ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page);
|
||||
else
|
||||
ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
|
||||
&page, NULL);
|
||||
if (ptr) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nr_pages; i++)
|
||||
pages[i] = page + i;
|
||||
|
||||
spin_lock_init(&pool->lock);
|
||||
pool->vaddr = ptr;
|
||||
pool->page = page;
|
||||
pool->pages = pages;
|
||||
pool->bitmap = bitmap;
|
||||
pool->nr_pages = nr_pages;
|
||||
pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
|
||||
(unsigned)pool->size / 1024);
|
||||
return 0;
|
||||
}
|
||||
no_pages:
|
||||
kfree(bitmap);
|
||||
no_bitmap:
|
||||
pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
|
||||
|
@ -443,27 +471,45 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
|
|||
if (pageno < pool->nr_pages) {
|
||||
bitmap_set(pool->bitmap, pageno, count);
|
||||
ptr = pool->vaddr + PAGE_SIZE * pageno;
|
||||
*ret_page = pool->page + pageno;
|
||||
*ret_page = pool->pages[pageno];
|
||||
} else {
|
||||
pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
|
||||
"Please increase it with coherent_pool= kernel parameter!\n",
|
||||
(unsigned)pool->size / 1024);
|
||||
}
|
||||
spin_unlock_irqrestore(&pool->lock, flags);
|
||||
|
||||
return ptr;
|
||||
}
|
||||
|
||||
static bool __in_atomic_pool(void *start, size_t size)
|
||||
{
|
||||
struct dma_pool *pool = &atomic_pool;
|
||||
void *end = start + size;
|
||||
void *pool_start = pool->vaddr;
|
||||
void *pool_end = pool->vaddr + pool->size;
|
||||
|
||||
if (start < pool_start || start > pool_end)
|
||||
return false;
|
||||
|
||||
if (end <= pool_end)
|
||||
return true;
|
||||
|
||||
WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
|
||||
start, end - 1, pool_start, pool_end - 1);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int __free_from_pool(void *start, size_t size)
|
||||
{
|
||||
struct dma_pool *pool = &atomic_pool;
|
||||
unsigned long pageno, count;
|
||||
unsigned long flags;
|
||||
|
||||
if (start < pool->vaddr || start > pool->vaddr + pool->size)
|
||||
if (!__in_atomic_pool(start, size))
|
||||
return 0;
|
||||
|
||||
if (start + size > pool->vaddr + pool->size) {
|
||||
WARN(1, "freeing wrong coherent size from pool\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
pageno = (start - pool->vaddr) >> PAGE_SHIFT;
|
||||
count = size >> PAGE_SHIFT;
|
||||
|
||||
|
@ -1090,10 +1136,22 @@ static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t si
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct page **__atomic_get_pages(void *addr)
|
||||
{
|
||||
struct dma_pool *pool = &atomic_pool;
|
||||
struct page **pages = pool->pages;
|
||||
int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
|
||||
|
||||
return pages + offs;
|
||||
}
|
||||
|
||||
static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
|
||||
{
|
||||
struct vm_struct *area;
|
||||
|
||||
if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
|
||||
return __atomic_get_pages(cpu_addr);
|
||||
|
||||
if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
|
||||
return cpu_addr;
|
||||
|
||||
|
@ -1103,6 +1161,34 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static void *__iommu_alloc_atomic(struct device *dev, size_t size,
|
||||
dma_addr_t *handle)
|
||||
{
|
||||
struct page *page;
|
||||
void *addr;
|
||||
|
||||
addr = __alloc_from_pool(size, &page);
|
||||
if (!addr)
|
||||
return NULL;
|
||||
|
||||
*handle = __iommu_create_mapping(dev, &page, size);
|
||||
if (*handle == DMA_ERROR_CODE)
|
||||
goto err_mapping;
|
||||
|
||||
return addr;
|
||||
|
||||
err_mapping:
|
||||
__free_from_pool(addr, size);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __iommu_free_atomic(struct device *dev, struct page **pages,
|
||||
dma_addr_t handle, size_t size)
|
||||
{
|
||||
__iommu_remove_mapping(dev, handle, size);
|
||||
__free_from_pool(page_address(pages[0]), size);
|
||||
}
|
||||
|
||||
static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
|
||||
dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
|
||||
{
|
||||
|
@ -1113,6 +1199,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
|
|||
*handle = DMA_ERROR_CODE;
|
||||
size = PAGE_ALIGN(size);
|
||||
|
||||
if (gfp & GFP_ATOMIC)
|
||||
return __iommu_alloc_atomic(dev, size, handle);
|
||||
|
||||
pages = __iommu_alloc_buffer(dev, size, gfp);
|
||||
if (!pages)
|
||||
return NULL;
|
||||
|
@ -1179,6 +1268,11 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
|
|||
return;
|
||||
}
|
||||
|
||||
if (__in_atomic_pool(cpu_addr, size)) {
|
||||
__iommu_free_atomic(dev, pages, handle, size);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
|
||||
unmap_kernel_range((unsigned long)cpu_addr, size);
|
||||
vunmap(cpu_addr);
|
||||
|
|
|
@ -117,16 +117,11 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
|
|||
}
|
||||
|
||||
/* Enable the PCIe normal error reporting */
|
||||
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
||||
if (pos) {
|
||||
/* Update Device Control */
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
|
||||
config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
|
||||
config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
|
||||
config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
|
||||
config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
|
||||
}
|
||||
config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
|
||||
config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
|
||||
config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
|
||||
config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
|
||||
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
|
||||
|
||||
/* Find the Advanced Error Reporting capability */
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
|
||||
|
|
|
@ -215,6 +215,9 @@ struct machdep_calls {
|
|||
/* Called after scan and before resource survey */
|
||||
void (*pcibios_fixup_phb)(struct pci_controller *hose);
|
||||
|
||||
/* Called during PCI resource reassignment */
|
||||
resource_size_t (*pcibios_window_alignment)(struct pci_bus *, unsigned long type);
|
||||
|
||||
/* Called to shutdown machine specific hardware not already controlled
|
||||
* by other drivers.
|
||||
*/
|
||||
|
|
|
@ -99,6 +99,26 @@ void pcibios_free_controller(struct pci_controller *phb)
|
|||
kfree(phb);
|
||||
}
|
||||
|
||||
/*
|
||||
* The function is used to return the minimal alignment
|
||||
* for memory or I/O windows of the associated P2P bridge.
|
||||
* By default, 4KiB alignment for I/O windows and 1MiB for
|
||||
* memory windows.
|
||||
*/
|
||||
resource_size_t pcibios_window_alignment(struct pci_bus *bus,
|
||||
unsigned long type)
|
||||
{
|
||||
if (ppc_md.pcibios_window_alignment)
|
||||
return ppc_md.pcibios_window_alignment(bus, type);
|
||||
|
||||
/*
|
||||
* PCI core will figure out the default
|
||||
* alignment: 4KiB for I/O and 1MiB for
|
||||
* memory window.
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
static resource_size_t pcibios_io_size(const struct pci_controller *hose)
|
||||
{
|
||||
#ifdef CONFIG_PPC64
|
||||
|
|
|
@ -854,7 +854,7 @@ static void __devinit pnv_ioda_setup_PEs(struct pci_bus *bus)
|
|||
if (pe == NULL)
|
||||
continue;
|
||||
/* Leaving the PCIe domain ... single PE# */
|
||||
if (dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
|
||||
if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
|
||||
pnv_ioda_setup_bus_PE(dev, pe);
|
||||
else if (dev->subordinate)
|
||||
pnv_ioda_setup_PEs(dev->subordinate);
|
||||
|
@ -1138,6 +1138,44 @@ static void __devinit pnv_pci_ioda_fixup_phb(struct pci_controller *hose)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns the alignment for I/O or memory windows for P2P
|
||||
* bridges. That actually depends on how PEs are segmented.
|
||||
* For now, we return I/O or M32 segment size for PE sensitive
|
||||
* P2P bridges. Otherwise, the default values (4KiB for I/O,
|
||||
* 1MiB for memory) will be returned.
|
||||
*
|
||||
* The current PCI bus might be put into one PE, which was
|
||||
* create against the parent PCI bridge. For that case, we
|
||||
* needn't enlarge the alignment so that we can save some
|
||||
* resources.
|
||||
*/
|
||||
static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
|
||||
unsigned long type)
|
||||
{
|
||||
struct pci_dev *bridge;
|
||||
struct pci_controller *hose = pci_bus_to_host(bus);
|
||||
struct pnv_phb *phb = hose->private_data;
|
||||
int num_pci_bridges = 0;
|
||||
|
||||
bridge = bus->self;
|
||||
while (bridge) {
|
||||
if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||
num_pci_bridges++;
|
||||
if (num_pci_bridges >= 2)
|
||||
return 1;
|
||||
}
|
||||
|
||||
bridge = bridge->bus->self;
|
||||
}
|
||||
|
||||
/* We need support prefetchable memory window later */
|
||||
if (type & IORESOURCE_MEM)
|
||||
return phb->ioda.m32_segsize;
|
||||
|
||||
return phb->ioda.io_segsize;
|
||||
}
|
||||
|
||||
/* Prevent enabling devices for which we couldn't properly
|
||||
* assign a PE
|
||||
*/
|
||||
|
@ -1305,6 +1343,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
|
|||
*/
|
||||
ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb;
|
||||
ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
|
||||
ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
|
||||
pci_add_flags(PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC);
|
||||
|
||||
/* Reset IODA tables to a clean state */
|
||||
|
|
|
@ -246,16 +246,13 @@ static void __devinit fixup_read_and_payload_sizes(void)
|
|||
|
||||
/* Scan for the smallest maximum payload size. */
|
||||
while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
|
||||
int pcie_caps_offset;
|
||||
u32 devcap;
|
||||
int max_payload;
|
||||
|
||||
pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
||||
if (pcie_caps_offset == 0)
|
||||
if (!pci_is_pcie(dev))
|
||||
continue;
|
||||
|
||||
pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
|
||||
&devcap);
|
||||
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
|
||||
max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
|
||||
if (max_payload < smallest_max_payload)
|
||||
smallest_max_payload = max_payload;
|
||||
|
@ -263,21 +260,10 @@ static void __devinit fixup_read_and_payload_sizes(void)
|
|||
|
||||
/* Now, set the max_payload_size for all devices to that value. */
|
||||
new_values = (max_read_size << 12) | (smallest_max_payload << 5);
|
||||
while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
|
||||
int pcie_caps_offset;
|
||||
u16 devctl;
|
||||
|
||||
pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
||||
if (pcie_caps_offset == 0)
|
||||
continue;
|
||||
|
||||
pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
|
||||
&devctl);
|
||||
devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
|
||||
devctl |= new_values;
|
||||
pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
|
||||
devctl);
|
||||
}
|
||||
while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
|
||||
pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
|
||||
new_values);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -114,7 +114,7 @@ static void deliver_alarm(void)
|
|||
skew += this_tick - last_tick;
|
||||
|
||||
while (skew >= one_tick) {
|
||||
alarm_handler(SIGVTALRM, NULL);
|
||||
alarm_handler(SIGVTALRM, NULL, NULL);
|
||||
skew -= one_tick;
|
||||
}
|
||||
|
||||
|
|
|
@ -1283,7 +1283,7 @@ static void xen_flush_tlb_others(const struct cpumask *cpus,
|
|||
cpumask_clear_cpu(smp_processor_id(), to_cpumask(args->mask));
|
||||
|
||||
args->op.cmd = MMUEXT_TLB_FLUSH_MULTI;
|
||||
if (start != TLB_FLUSH_ALL && (end - start) <= PAGE_SIZE) {
|
||||
if (end != TLB_FLUSH_ALL && (end - start) <= PAGE_SIZE) {
|
||||
args->op.cmd = MMUEXT_INVLPG_MULTI;
|
||||
args->op.arg1.linear_addr = start;
|
||||
}
|
||||
|
|
|
@ -599,7 +599,7 @@ bool __init early_can_reuse_p2m_middle(unsigned long set_pfn, unsigned long set_
|
|||
if (p2m_index(set_pfn))
|
||||
return false;
|
||||
|
||||
for (pfn = 0; pfn <= MAX_DOMAIN_PAGES; pfn += P2M_PER_PAGE) {
|
||||
for (pfn = 0; pfn < MAX_DOMAIN_PAGES; pfn += P2M_PER_PAGE) {
|
||||
topidx = p2m_top_index(pfn);
|
||||
|
||||
if (!p2m_top[topidx])
|
||||
|
|
|
@ -250,7 +250,7 @@ int __init dma_declare_contiguous(struct device *dev, unsigned long size,
|
|||
return -EINVAL;
|
||||
|
||||
/* Sanitise input arguments */
|
||||
alignment = PAGE_SIZE << max(MAX_ORDER, pageblock_order);
|
||||
alignment = PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
|
||||
base = ALIGN(base, alignment);
|
||||
size = ALIGN(size, alignment);
|
||||
limit &= ~(alignment - 1);
|
||||
|
|
|
@ -294,7 +294,7 @@ config GPIO_MAX732X_IRQ
|
|||
|
||||
config GPIO_MC9S08DZ60
|
||||
bool "MX35 3DS BOARD MC9S08DZ60 GPIO functions"
|
||||
depends on I2C && MACH_MX35_3DS
|
||||
depends on I2C=y && MACH_MX35_3DS
|
||||
help
|
||||
Select this to enable the MC9S08DZ60 GPIO driver
|
||||
|
||||
|
|
|
@ -247,9 +247,9 @@ static int __devinit em_gio_irq_domain_init(struct em_gio_priv *p)
|
|||
|
||||
p->irq_base = irq_alloc_descs(pdata->irq_base, 0,
|
||||
pdata->number_of_pins, numa_node_id());
|
||||
if (IS_ERR_VALUE(p->irq_base)) {
|
||||
if (p->irq_base < 0) {
|
||||
dev_err(&pdev->dev, "cannot get irq_desc\n");
|
||||
return -ENXIO;
|
||||
return p->irq_base;
|
||||
}
|
||||
pr_debug("gio: hw base = %d, nr = %d, sw base = %d\n",
|
||||
pdata->gpio_base, pdata->number_of_pins, p->irq_base);
|
||||
|
|
|
@ -170,6 +170,7 @@ static int __devinit rdc321x_gpio_probe(struct platform_device *pdev)
|
|||
rdc321x_gpio_dev->reg2_data_base = r->start + 0x4;
|
||||
|
||||
rdc321x_gpio_dev->chip.label = "rdc321x-gpio";
|
||||
rdc321x_gpio_dev->chip.owner = THIS_MODULE;
|
||||
rdc321x_gpio_dev->chip.direction_input = rdc_gpio_direction_input;
|
||||
rdc321x_gpio_dev->chip.direction_output = rdc_gpio_config;
|
||||
rdc321x_gpio_dev->chip.get = rdc_gpio_get_value;
|
||||
|
|
|
@ -82,7 +82,7 @@ int of_get_named_gpio_flags(struct device_node *np, const char *propname,
|
|||
gpiochip_find(&gg_data, of_gpiochip_find_and_xlate);
|
||||
|
||||
of_node_put(gg_data.gpiospec.np);
|
||||
pr_debug("%s exited with status %d\n", __func__, ret);
|
||||
pr_debug("%s exited with status %d\n", __func__, gg_data.out_gpio);
|
||||
return gg_data.out_gpio;
|
||||
}
|
||||
EXPORT_SYMBOL(of_get_named_gpio_flags);
|
||||
|
|
|
@ -77,13 +77,9 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
|
|||
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
|
||||
{
|
||||
u16 ctl, v;
|
||||
int cap, err;
|
||||
int err;
|
||||
|
||||
cap = pci_pcie_cap(rdev->pdev);
|
||||
if (!cap)
|
||||
return;
|
||||
|
||||
err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
|
||||
err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
|
||||
if (err)
|
||||
return;
|
||||
|
||||
|
@ -95,7 +91,7 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
|
|||
if ((v == 0) || (v == 6) || (v == 7)) {
|
||||
ctl &= ~PCI_EXP_DEVCTL_READRQ;
|
||||
ctl |= (2 << 12);
|
||||
pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
|
||||
pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -996,7 +996,8 @@ static void hid_process_event(struct hid_device *hid, struct hid_field *field,
|
|||
struct hid_driver *hdrv = hid->driver;
|
||||
int ret;
|
||||
|
||||
hid_dump_input(hid, usage, value);
|
||||
if (!list_empty(&hid->debug_list))
|
||||
hid_dump_input(hid, usage, value);
|
||||
|
||||
if (hdrv && hdrv->event && hid_match_usage(hid, usage)) {
|
||||
ret = hdrv->event(hid, field, usage, value);
|
||||
|
@ -1558,7 +1559,9 @@ static const struct hid_device_id hid_have_special_driver[] = {
|
|||
{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_LABTEC, USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_LCPOWER, USB_DEVICE_ID_LCPOWER_LC1000 ) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_TPKBD) },
|
||||
#if IS_ENABLED(CONFIG_HID_LENOVO_TPKBD)
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_TPKBD) },
|
||||
#endif
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER) },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER_2) },
|
||||
|
|
|
@ -439,7 +439,7 @@ static int logi_dj_recv_query_paired_devices(struct dj_receiver_dev *djrcv_dev)
|
|||
struct dj_report *dj_report;
|
||||
int retval;
|
||||
|
||||
dj_report = kzalloc(sizeof(dj_report), GFP_KERNEL);
|
||||
dj_report = kzalloc(sizeof(struct dj_report), GFP_KERNEL);
|
||||
if (!dj_report)
|
||||
return -ENOMEM;
|
||||
dj_report->report_id = REPORT_ID_DJ_SHORT;
|
||||
|
@ -456,7 +456,7 @@ static int logi_dj_recv_switch_to_dj_mode(struct dj_receiver_dev *djrcv_dev,
|
|||
struct dj_report *dj_report;
|
||||
int retval;
|
||||
|
||||
dj_report = kzalloc(sizeof(dj_report), GFP_KERNEL);
|
||||
dj_report = kzalloc(sizeof(struct dj_report), GFP_KERNEL);
|
||||
if (!dj_report)
|
||||
return -ENOMEM;
|
||||
dj_report->report_id = REPORT_ID_DJ_SHORT;
|
||||
|
|
|
@ -70,6 +70,7 @@ static const struct hid_blacklist {
|
|||
{ USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_AXIS_295, HID_QUIRK_NOGET },
|
||||
{ USB_VENDOR_ID_DMI, USB_DEVICE_ID_DMI_ENC, HID_QUIRK_NOGET },
|
||||
{ USB_VENDOR_ID_ELO, USB_DEVICE_ID_ELO_TS2700, HID_QUIRK_NOGET },
|
||||
{ USB_VENDOR_ID_MGE, USB_DEVICE_ID_MGE_UPS, HID_QUIRK_NOGET },
|
||||
{ USB_VENDOR_ID_PIXART, USB_DEVICE_ID_PIXART_OPTICAL_TOUCH_SCREEN, HID_QUIRK_NO_INIT_REPORTS },
|
||||
{ USB_VENDOR_ID_PIXART, USB_DEVICE_ID_PIXART_OPTICAL_TOUCH_SCREEN1, HID_QUIRK_NO_INIT_REPORTS },
|
||||
{ USB_VENDOR_ID_PIXART, USB_DEVICE_ID_PIXART_OPTICAL_TOUCH_SCREEN2, HID_QUIRK_NO_INIT_REPORTS },
|
||||
|
|
|
@ -241,16 +241,16 @@ good:
|
|||
|
||||
if (hca_pcie_cap) {
|
||||
devctl = hca_header[(hca_pcie_cap + PCI_EXP_DEVCTL) / 4];
|
||||
if (pci_write_config_word(mdev->pdev, hca_pcie_cap + PCI_EXP_DEVCTL,
|
||||
devctl)) {
|
||||
if (pcie_capability_write_word(mdev->pdev, PCI_EXP_DEVCTL,
|
||||
devctl)) {
|
||||
err = -ENODEV;
|
||||
mthca_err(mdev, "Couldn't restore HCA PCI Express "
|
||||
"Device Control register, aborting.\n");
|
||||
goto out;
|
||||
}
|
||||
linkctl = hca_header[(hca_pcie_cap + PCI_EXP_LNKCTL) / 4];
|
||||
if (pci_write_config_word(mdev->pdev, hca_pcie_cap + PCI_EXP_LNKCTL,
|
||||
linkctl)) {
|
||||
if (pcie_capability_write_word(mdev->pdev, PCI_EXP_LNKCTL,
|
||||
linkctl)) {
|
||||
err = -ENODEV;
|
||||
mthca_err(mdev, "Couldn't restore HCA PCI Express "
|
||||
"Link control register, aborting.\n");
|
||||
|
|
|
@ -273,10 +273,9 @@ int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
|
|||
struct qib_msix_entry *entry)
|
||||
{
|
||||
u16 linkstat, speed;
|
||||
int pos = 0, pose, ret = 1;
|
||||
int pos = 0, ret = 1;
|
||||
|
||||
pose = pci_pcie_cap(dd->pcidev);
|
||||
if (!pose) {
|
||||
if (!pci_is_pcie(dd->pcidev)) {
|
||||
qib_dev_err(dd, "Can't find PCI Express capability!\n");
|
||||
/* set up something... */
|
||||
dd->lbus_width = 1;
|
||||
|
@ -298,7 +297,7 @@ int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
|
|||
if (!pos)
|
||||
qib_enable_intx(dd->pcidev);
|
||||
|
||||
pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat);
|
||||
pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
|
||||
/*
|
||||
* speed is bits 0-3, linkwidth is bits 4-8
|
||||
* no defines for them in headers
|
||||
|
@ -516,7 +515,6 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
|
|||
{
|
||||
int r;
|
||||
struct pci_dev *parent;
|
||||
int ppos;
|
||||
u16 devid;
|
||||
u32 mask, bits, val;
|
||||
|
||||
|
@ -529,8 +527,7 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
|
|||
qib_devinfo(dd->pcidev, "Parent not root\n");
|
||||
return 1;
|
||||
}
|
||||
ppos = pci_pcie_cap(parent);
|
||||
if (!ppos)
|
||||
if (!pci_is_pcie(parent))
|
||||
return 1;
|
||||
if (parent->vendor != 0x8086)
|
||||
return 1;
|
||||
|
@ -587,7 +584,6 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
|
|||
{
|
||||
int ret = 1; /* Assume the worst */
|
||||
struct pci_dev *parent;
|
||||
int ppos, epos;
|
||||
u16 pcaps, pctl, ecaps, ectl;
|
||||
int rc_sup, ep_sup;
|
||||
int rc_cur, ep_cur;
|
||||
|
@ -598,19 +594,15 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
|
|||
qib_devinfo(dd->pcidev, "Parent not root\n");
|
||||
goto bail;
|
||||
}
|
||||
ppos = pci_pcie_cap(parent);
|
||||
if (ppos) {
|
||||
pci_read_config_word(parent, ppos + PCI_EXP_DEVCAP, &pcaps);
|
||||
pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl);
|
||||
} else
|
||||
|
||||
if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
|
||||
goto bail;
|
||||
pcie_capability_read_word(parent, PCI_EXP_DEVCAP, &pcaps);
|
||||
pcie_capability_read_word(parent, PCI_EXP_DEVCTL, &pctl);
|
||||
/* Find out supported and configured values for endpoint (us) */
|
||||
epos = pci_pcie_cap(dd->pcidev);
|
||||
if (epos) {
|
||||
pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCAP, &ecaps);
|
||||
pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, &ectl);
|
||||
} else
|
||||
goto bail;
|
||||
pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCAP, &ecaps);
|
||||
pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
|
||||
|
||||
ret = 0;
|
||||
/* Find max payload supported by root, endpoint */
|
||||
rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD);
|
||||
|
@ -629,14 +621,14 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
|
|||
rc_cur = rc_sup;
|
||||
pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) |
|
||||
val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
|
||||
pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
|
||||
pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
|
||||
}
|
||||
/* If less than (allowed, supported), bump endpoint payload */
|
||||
if (rc_sup > ep_cur) {
|
||||
ep_cur = rc_sup;
|
||||
ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) |
|
||||
val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
|
||||
pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
|
||||
pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -654,13 +646,13 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
|
|||
rc_cur = rc_sup;
|
||||
pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) |
|
||||
val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
|
||||
pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
|
||||
pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
|
||||
}
|
||||
if (rc_sup > ep_cur) {
|
||||
ep_cur = rc_sup;
|
||||
ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) |
|
||||
val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
|
||||
pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
|
||||
pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
|
||||
}
|
||||
bail:
|
||||
return ret;
|
||||
|
|
|
@ -358,6 +358,7 @@ static void imx_keypad_inhibit(struct imx_keypad *keypad)
|
|||
/* Inhibit KDI and KRI interrupts. */
|
||||
reg_val = readw(keypad->mmio_base + KPSR);
|
||||
reg_val &= ~(KBD_STAT_KRIE | KBD_STAT_KDIE);
|
||||
reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD;
|
||||
writew(reg_val, keypad->mmio_base + KPSR);
|
||||
|
||||
/* Colums as open drain and disable all rows */
|
||||
|
@ -515,7 +516,9 @@ static int __devinit imx_keypad_probe(struct platform_device *pdev)
|
|||
input_set_drvdata(input_dev, keypad);
|
||||
|
||||
/* Ensure that the keypad will stay dormant until opened */
|
||||
clk_enable(keypad->clk);
|
||||
imx_keypad_inhibit(keypad);
|
||||
clk_disable(keypad->clk);
|
||||
|
||||
error = request_irq(irq, imx_keypad_irq_handler, 0,
|
||||
pdev->name, keypad);
|
||||
|
|
|
@ -176,6 +176,20 @@ static const struct dmi_system_id __initconst i8042_dmi_noloop_table[] = {
|
|||
DMI_MATCH(DMI_PRODUCT_NAME, "Spring Peak"),
|
||||
},
|
||||
},
|
||||
{
|
||||
/* Gigabyte T1005 - defines wrong chassis type ("Other") */
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "GIGABYTE"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "T1005"),
|
||||
},
|
||||
},
|
||||
{
|
||||
/* Gigabyte T1005M/P - defines wrong chassis type ("Other") */
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "GIGABYTE"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "T1005M/P"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
||||
|
|
|
@ -1848,7 +1848,10 @@ static const struct wacom_features wacom_features_0x2A =
|
|||
{ "Wacom Intuos5 M", WACOM_PKGLEN_INTUOS, 44704, 27940, 2047,
|
||||
63, INTUOS5, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES };
|
||||
static const struct wacom_features wacom_features_0xF4 =
|
||||
{ "Wacom Cintiq 24HD", WACOM_PKGLEN_INTUOS, 104480, 65600, 2047,
|
||||
{ "Wacom Cintiq 24HD", WACOM_PKGLEN_INTUOS, 104480, 65600, 2047,
|
||||
63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES };
|
||||
static const struct wacom_features wacom_features_0xF8 =
|
||||
{ "Wacom Cintiq 24HD touch", WACOM_PKGLEN_INTUOS, 104480, 65600, 2047,
|
||||
63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES };
|
||||
static const struct wacom_features wacom_features_0x3F =
|
||||
{ "Wacom Cintiq 21UX", WACOM_PKGLEN_INTUOS, 87200, 65600, 1023,
|
||||
|
@ -2091,6 +2094,7 @@ const struct usb_device_id wacom_ids[] = {
|
|||
{ USB_DEVICE_WACOM(0xEF) },
|
||||
{ USB_DEVICE_WACOM(0x47) },
|
||||
{ USB_DEVICE_WACOM(0xF4) },
|
||||
{ USB_DEVICE_WACOM(0xF8) },
|
||||
{ USB_DEVICE_WACOM(0xFA) },
|
||||
{ USB_DEVICE_LENOVO(0x6004) },
|
||||
{ }
|
||||
|
|
|
@ -602,6 +602,7 @@ edt_ft5x06_ts_teardown_debugfs(struct edt_ft5x06_ts_data *tsdata)
|
|||
{
|
||||
if (tsdata->debug_dir)
|
||||
debugfs_remove_recursive(tsdata->debug_dir);
|
||||
kfree(tsdata->raw_buffer);
|
||||
}
|
||||
|
||||
#else
|
||||
|
@ -843,7 +844,6 @@ static int __devexit edt_ft5x06_ts_remove(struct i2c_client *client)
|
|||
if (gpio_is_valid(pdata->reset_pin))
|
||||
gpio_free(pdata->reset_pin);
|
||||
|
||||
kfree(tsdata->raw_buffer);
|
||||
kfree(tsdata);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -2351,7 +2351,7 @@ static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
|
|||
return 0;
|
||||
if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
|
||||
return 0;
|
||||
} else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
|
||||
} else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
|
@ -3546,10 +3546,10 @@ found:
|
|||
struct pci_dev *bridge = bus->self;
|
||||
|
||||
if (!bridge || !pci_is_pcie(bridge) ||
|
||||
bridge->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
|
||||
pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
|
||||
return 0;
|
||||
|
||||
if (bridge->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
|
||||
if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
|
||||
for (i = 0; i < atsru->devices_cnt; i++)
|
||||
if (atsru->devices[i] == bridge)
|
||||
return 1;
|
||||
|
|
|
@ -1411,7 +1411,8 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
|
|||
/* complete ongoing async transfer before issuing discard */
|
||||
if (card->host->areq)
|
||||
mmc_blk_issue_rw_rq(mq, NULL);
|
||||
if (req->cmd_flags & REQ_SECURE)
|
||||
if (req->cmd_flags & REQ_SECURE &&
|
||||
!(card->quirks & MMC_QUIRK_SEC_ERASE_TRIM_BROKEN))
|
||||
ret = mmc_blk_issue_secdiscard_rq(mq, req);
|
||||
else
|
||||
ret = mmc_blk_issue_discard_rq(mq, req);
|
||||
|
@ -1716,6 +1717,7 @@ force_ro_fail:
|
|||
#define CID_MANFID_SANDISK 0x2
|
||||
#define CID_MANFID_TOSHIBA 0x11
|
||||
#define CID_MANFID_MICRON 0x13
|
||||
#define CID_MANFID_SAMSUNG 0x15
|
||||
|
||||
static const struct mmc_fixup blk_fixups[] =
|
||||
{
|
||||
|
@ -1752,6 +1754,28 @@ static const struct mmc_fixup blk_fixups[] =
|
|||
MMC_FIXUP(CID_NAME_ANY, CID_MANFID_MICRON, 0x200, add_quirk_mmc,
|
||||
MMC_QUIRK_LONG_READ_TIME),
|
||||
|
||||
/*
|
||||
* On these Samsung MoviNAND parts, performing secure erase or
|
||||
* secure trim can result in unrecoverable corruption due to a
|
||||
* firmware bug.
|
||||
*/
|
||||
MMC_FIXUP("M8G2FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
|
||||
MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
|
||||
MMC_FIXUP("MAG4FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
|
||||
MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
|
||||
MMC_FIXUP("MBG8FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
|
||||
MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
|
||||
MMC_FIXUP("MCGAFA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
|
||||
MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
|
||||
MMC_FIXUP("VAL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
|
||||
MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
|
||||
MMC_FIXUP("VYL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
|
||||
MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
|
||||
MMC_FIXUP("KYL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
|
||||
MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
|
||||
MMC_FIXUP("VZL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
|
||||
MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
|
||||
|
||||
END_FIXUP
|
||||
};
|
||||
|
||||
|
|
|
@ -81,6 +81,7 @@ struct atmel_mci_caps {
|
|||
bool has_bad_data_ordering;
|
||||
bool need_reset_after_xfer;
|
||||
bool need_blksz_mul_4;
|
||||
bool need_notbusy_for_read_ops;
|
||||
};
|
||||
|
||||
struct atmel_mci_dma {
|
||||
|
@ -1625,7 +1626,8 @@ static void atmci_tasklet_func(unsigned long priv)
|
|||
__func__);
|
||||
atmci_set_completed(host, EVENT_XFER_COMPLETE);
|
||||
|
||||
if (host->data->flags & MMC_DATA_WRITE) {
|
||||
if (host->caps.need_notbusy_for_read_ops ||
|
||||
(host->data->flags & MMC_DATA_WRITE)) {
|
||||
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
||||
state = STATE_WAITING_NOTBUSY;
|
||||
} else if (host->mrq->stop) {
|
||||
|
@ -2218,6 +2220,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
|
|||
host->caps.has_bad_data_ordering = 1;
|
||||
host->caps.need_reset_after_xfer = 1;
|
||||
host->caps.need_blksz_mul_4 = 1;
|
||||
host->caps.need_notbusy_for_read_ops = 0;
|
||||
|
||||
/* keep only major version number */
|
||||
switch (version & 0xf00) {
|
||||
|
@ -2238,6 +2241,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
|
|||
case 0x200:
|
||||
host->caps.has_rwproof = 1;
|
||||
host->caps.need_blksz_mul_4 = 0;
|
||||
host->caps.need_notbusy_for_read_ops = 1;
|
||||
case 0x100:
|
||||
host->caps.has_bad_data_ordering = 0;
|
||||
host->caps.need_reset_after_xfer = 0;
|
||||
|
|
|
@ -49,13 +49,6 @@
|
|||
#define bfin_write_SDH_CFG bfin_write_RSI_CFG
|
||||
#endif
|
||||
|
||||
struct dma_desc_array {
|
||||
unsigned long start_addr;
|
||||
unsigned short cfg;
|
||||
unsigned short x_count;
|
||||
short x_modify;
|
||||
} __packed;
|
||||
|
||||
struct sdh_host {
|
||||
struct mmc_host *mmc;
|
||||
spinlock_t lock;
|
||||
|
|
|
@ -627,6 +627,7 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot)
|
|||
{
|
||||
struct dw_mci *host = slot->host;
|
||||
u32 div;
|
||||
u32 clk_en_a;
|
||||
|
||||
if (slot->clock != host->current_speed) {
|
||||
div = host->bus_hz / slot->clock;
|
||||
|
@ -659,9 +660,11 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot)
|
|||
mci_send_cmd(slot,
|
||||
SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
|
||||
|
||||
/* enable clock */
|
||||
mci_writel(host, CLKENA, ((SDMMC_CLKEN_ENABLE |
|
||||
SDMMC_CLKEN_LOW_PWR) << slot->id));
|
||||
/* enable clock; only low power if no SDIO */
|
||||
clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
|
||||
if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
|
||||
clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
|
||||
mci_writel(host, CLKENA, clk_en_a);
|
||||
|
||||
/* inform CIU */
|
||||
mci_send_cmd(slot,
|
||||
|
@ -862,6 +865,30 @@ static int dw_mci_get_cd(struct mmc_host *mmc)
|
|||
return present;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable lower power mode.
|
||||
*
|
||||
* Low power mode will stop the card clock when idle. According to the
|
||||
* description of the CLKENA register we should disable low power mode
|
||||
* for SDIO cards if we need SDIO interrupts to work.
|
||||
*
|
||||
* This function is fast if low power mode is already disabled.
|
||||
*/
|
||||
static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
|
||||
{
|
||||
struct dw_mci *host = slot->host;
|
||||
u32 clk_en_a;
|
||||
const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
|
||||
|
||||
clk_en_a = mci_readl(host, CLKENA);
|
||||
|
||||
if (clk_en_a & clken_low_pwr) {
|
||||
mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
|
||||
mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
|
||||
SDMMC_CMD_PRV_DAT_WAIT, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
|
||||
{
|
||||
struct dw_mci_slot *slot = mmc_priv(mmc);
|
||||
|
@ -871,6 +898,14 @@ static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
|
|||
/* Enable/disable Slot Specific SDIO interrupt */
|
||||
int_mask = mci_readl(host, INTMASK);
|
||||
if (enb) {
|
||||
/*
|
||||
* Turn off low power mode if it was enabled. This is a bit of
|
||||
* a heavy operation and we disable / enable IRQs a lot, so
|
||||
* we'll leave low power mode disabled and it will get
|
||||
* re-enabled again in dw_mci_setup_bus().
|
||||
*/
|
||||
dw_mci_disable_low_power(slot);
|
||||
|
||||
mci_writel(host, INTMASK,
|
||||
(int_mask | SDMMC_INT_SDIO(slot->id)));
|
||||
} else {
|
||||
|
@ -1429,22 +1464,10 @@ static void dw_mci_read_data_pio(struct dw_mci *host)
|
|||
nbytes += len;
|
||||
remain -= len;
|
||||
} while (remain);
|
||||
sg_miter->consumed = offset;
|
||||
|
||||
sg_miter->consumed = offset;
|
||||
status = mci_readl(host, MINTSTS);
|
||||
mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
|
||||
if (status & DW_MCI_DATA_ERROR_FLAGS) {
|
||||
host->data_status = status;
|
||||
data->bytes_xfered += nbytes;
|
||||
sg_miter_stop(sg_miter);
|
||||
host->sg = NULL;
|
||||
smp_wmb();
|
||||
|
||||
set_bit(EVENT_DATA_ERROR, &host->pending_events);
|
||||
|
||||
tasklet_schedule(&host->tasklet);
|
||||
return;
|
||||
}
|
||||
} while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
|
||||
data->bytes_xfered += nbytes;
|
||||
|
||||
|
@ -1497,23 +1520,10 @@ static void dw_mci_write_data_pio(struct dw_mci *host)
|
|||
nbytes += len;
|
||||
remain -= len;
|
||||
} while (remain);
|
||||
sg_miter->consumed = offset;
|
||||
|
||||
sg_miter->consumed = offset;
|
||||
status = mci_readl(host, MINTSTS);
|
||||
mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
|
||||
if (status & DW_MCI_DATA_ERROR_FLAGS) {
|
||||
host->data_status = status;
|
||||
data->bytes_xfered += nbytes;
|
||||
sg_miter_stop(sg_miter);
|
||||
host->sg = NULL;
|
||||
|
||||
smp_wmb();
|
||||
|
||||
set_bit(EVENT_DATA_ERROR, &host->pending_events);
|
||||
|
||||
tasklet_schedule(&host->tasklet);
|
||||
return;
|
||||
}
|
||||
} while (status & SDMMC_INT_TXDR); /* if TXDR write again */
|
||||
data->bytes_xfered += nbytes;
|
||||
|
||||
|
@ -1547,12 +1557,11 @@ static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
|
|||
static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct dw_mci *host = dev_id;
|
||||
u32 status, pending;
|
||||
u32 pending;
|
||||
unsigned int pass_count = 0;
|
||||
int i;
|
||||
|
||||
do {
|
||||
status = mci_readl(host, RINTSTS);
|
||||
pending = mci_readl(host, MINTSTS); /* read-only mask reg */
|
||||
|
||||
/*
|
||||
|
@ -1570,7 +1579,7 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
|
|||
|
||||
if (pending & DW_MCI_CMD_ERROR_FLAGS) {
|
||||
mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
|
||||
host->cmd_status = status;
|
||||
host->cmd_status = pending;
|
||||
smp_wmb();
|
||||
set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
|
||||
}
|
||||
|
@ -1578,18 +1587,16 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
|
|||
if (pending & DW_MCI_DATA_ERROR_FLAGS) {
|
||||
/* if there is an error report DATA_ERROR */
|
||||
mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
|
||||
host->data_status = status;
|
||||
host->data_status = pending;
|
||||
smp_wmb();
|
||||
set_bit(EVENT_DATA_ERROR, &host->pending_events);
|
||||
if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
|
||||
SDMMC_INT_SBE | SDMMC_INT_EBE)))
|
||||
tasklet_schedule(&host->tasklet);
|
||||
tasklet_schedule(&host->tasklet);
|
||||
}
|
||||
|
||||
if (pending & SDMMC_INT_DATA_OVER) {
|
||||
mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
|
||||
if (!host->data_status)
|
||||
host->data_status = status;
|
||||
host->data_status = pending;
|
||||
smp_wmb();
|
||||
if (host->dir_status == DW_MCI_RECV_STATUS) {
|
||||
if (host->sg != NULL)
|
||||
|
@ -1613,7 +1620,7 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
|
|||
|
||||
if (pending & SDMMC_INT_CMD_DONE) {
|
||||
mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
|
||||
dw_mci_cmd_interrupt(host, status);
|
||||
dw_mci_cmd_interrupt(host, pending);
|
||||
}
|
||||
|
||||
if (pending & SDMMC_INT_CD) {
|
||||
|
|
|
@ -285,11 +285,11 @@ static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
|
|||
writel(stat & MXS_MMC_IRQ_BITS,
|
||||
host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
|
||||
|
||||
spin_unlock(&host->lock);
|
||||
|
||||
if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
|
||||
mmc_signal_sdio_irq(host->mmc);
|
||||
|
||||
spin_unlock(&host->lock);
|
||||
|
||||
if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
|
||||
cmd->error = -ETIMEDOUT;
|
||||
else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
|
||||
|
@ -644,11 +644,6 @@ static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
|||
host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
||||
writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
|
||||
host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
|
||||
|
||||
if (readl(host->base + HW_SSP_STATUS(host)) &
|
||||
BM_SSP_STATUS_SDIO_IRQ)
|
||||
mmc_signal_sdio_irq(host->mmc);
|
||||
|
||||
} else {
|
||||
writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
|
||||
host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
||||
|
@ -657,6 +652,11 @@ static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
|||
}
|
||||
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
|
||||
if (enable && readl(host->base + HW_SSP_STATUS(host)) &
|
||||
BM_SSP_STATUS_SDIO_IRQ)
|
||||
mmc_signal_sdio_irq(host->mmc);
|
||||
|
||||
}
|
||||
|
||||
static const struct mmc_host_ops mxs_mmc_ops = {
|
||||
|
|
|
@ -668,7 +668,7 @@ mmc_omap_clk_timer(unsigned long data)
|
|||
static void
|
||||
mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
|
||||
{
|
||||
int n;
|
||||
int n, nwords;
|
||||
|
||||
if (host->buffer_bytes_left == 0) {
|
||||
host->sg_idx++;
|
||||
|
@ -678,15 +678,23 @@ mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
|
|||
n = 64;
|
||||
if (n > host->buffer_bytes_left)
|
||||
n = host->buffer_bytes_left;
|
||||
|
||||
nwords = n / 2;
|
||||
nwords += n & 1; /* handle odd number of bytes to transfer */
|
||||
|
||||
host->buffer_bytes_left -= n;
|
||||
host->total_bytes_left -= n;
|
||||
host->data->bytes_xfered += n;
|
||||
|
||||
if (write) {
|
||||
__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
|
||||
__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
|
||||
host->buffer, nwords);
|
||||
} else {
|
||||
__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
|
||||
__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
|
||||
host->buffer, nwords);
|
||||
}
|
||||
|
||||
host->buffer += nwords;
|
||||
}
|
||||
|
||||
static inline void mmc_omap_report_irq(u16 status)
|
||||
|
|
|
@ -48,14 +48,14 @@ static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
|
|||
int div = 1;
|
||||
u32 temp;
|
||||
|
||||
if (clock == 0)
|
||||
goto out;
|
||||
|
||||
temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
|
||||
temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
|
||||
| ESDHC_CLOCK_MASK);
|
||||
sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
|
||||
|
||||
if (clock == 0)
|
||||
goto out;
|
||||
|
||||
while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
|
||||
pre_div *= 2;
|
||||
|
||||
|
|
|
@ -340,7 +340,7 @@ retry:
|
|||
* of this LEB as it will be deleted and freed in 'ubi_add_to_av()'.
|
||||
*/
|
||||
err = ubi_add_to_av(ubi, ai, new_aeb->pnum, new_aeb->ec, vid_hdr, 0);
|
||||
kfree(new_aeb);
|
||||
kmem_cache_free(ai->aeb_slab_cache, new_aeb);
|
||||
ubi_free_vid_hdr(ubi, vid_hdr);
|
||||
return err;
|
||||
|
||||
|
@ -353,7 +353,7 @@ write_error:
|
|||
list_add(&new_aeb->u.list, &ai->erase);
|
||||
goto retry;
|
||||
}
|
||||
kfree(new_aeb);
|
||||
kmem_cache_free(ai->aeb_slab_cache, new_aeb);
|
||||
out_free:
|
||||
ubi_free_vid_hdr(ubi, vid_hdr);
|
||||
return err;
|
||||
|
|
|
@ -149,7 +149,7 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
|
|||
data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
|
||||
pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
|
||||
/* clear error status */
|
||||
pci_write_config_word(pdev, pci_pcie_cap(pdev) + PCI_EXP_DEVSTA,
|
||||
pcie_capability_write_word(pdev, PCI_EXP_DEVSTA,
|
||||
PCI_EXP_DEVSTA_NFED |
|
||||
PCI_EXP_DEVSTA_FED |
|
||||
PCI_EXP_DEVSTA_CED |
|
||||
|
|
|
@ -1162,14 +1162,9 @@ static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
|
|||
|
||||
static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u16 status;
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos)
|
||||
return false;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
|
||||
return status & PCI_EXP_DEVSTA_TRPND;
|
||||
}
|
||||
|
||||
|
@ -6135,8 +6130,7 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
|
|||
u16 devctl;
|
||||
int r_order, w_order;
|
||||
|
||||
pci_read_config_word(bp->pdev,
|
||||
pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
|
||||
pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
|
||||
DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
|
||||
w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
|
||||
if (bp->mrrs == -1)
|
||||
|
@ -9374,7 +9368,7 @@ static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
|
|||
|
||||
static int __devinit bnx2x_do_flr(struct bnx2x *bp)
|
||||
{
|
||||
int i, pos;
|
||||
int i;
|
||||
u16 status;
|
||||
struct pci_dev *dev = bp->pdev;
|
||||
|
||||
|
@ -9391,16 +9385,12 @@ static int __devinit bnx2x_do_flr(struct bnx2x *bp)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos)
|
||||
return -ENOTTY;
|
||||
|
||||
/* Wait for Transaction Pending bit clean */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (i)
|
||||
msleep((1 << (i - 1)) * 100);
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
|
||||
if (!(status & PCI_EXP_DEVSTA_TRPND))
|
||||
goto clear;
|
||||
}
|
||||
|
|
|
@ -3653,17 +3653,9 @@ static int tg3_power_down_prepare(struct tg3 *tp)
|
|||
tg3_enable_register_access(tp);
|
||||
|
||||
/* Restore the CLKREQ setting. */
|
||||
if (tg3_flag(tp, CLKREQ_BUG)) {
|
||||
u16 lnkctl;
|
||||
|
||||
pci_read_config_word(tp->pdev,
|
||||
pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
|
||||
&lnkctl);
|
||||
lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
|
||||
pci_write_config_word(tp->pdev,
|
||||
pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
|
||||
lnkctl);
|
||||
}
|
||||
if (tg3_flag(tp, CLKREQ_BUG))
|
||||
pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
|
||||
misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
|
||||
tw32(TG3PCI_MISC_HOST_CTRL,
|
||||
|
@ -4434,20 +4426,13 @@ relink:
|
|||
|
||||
/* Prevent send BD corruption. */
|
||||
if (tg3_flag(tp, CLKREQ_BUG)) {
|
||||
u16 oldlnkctl, newlnkctl;
|
||||
|
||||
pci_read_config_word(tp->pdev,
|
||||
pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
|
||||
&oldlnkctl);
|
||||
if (tp->link_config.active_speed == SPEED_100 ||
|
||||
tp->link_config.active_speed == SPEED_10)
|
||||
newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
|
||||
pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
else
|
||||
newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
|
||||
if (newlnkctl != oldlnkctl)
|
||||
pci_write_config_word(tp->pdev,
|
||||
pci_pcie_cap(tp->pdev) +
|
||||
PCI_EXP_LNKCTL, newlnkctl);
|
||||
pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
}
|
||||
|
||||
if (current_link_up != netif_carrier_ok(tp->dev)) {
|
||||
|
@ -8054,7 +8039,7 @@ static int tg3_chip_reset(struct tg3 *tp)
|
|||
|
||||
udelay(120);
|
||||
|
||||
if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
|
||||
if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
|
||||
u16 val16;
|
||||
|
||||
if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
|
||||
|
@ -8071,24 +8056,17 @@ static int tg3_chip_reset(struct tg3 *tp)
|
|||
}
|
||||
|
||||
/* Clear the "no snoop" and "relaxed ordering" bits. */
|
||||
pci_read_config_word(tp->pdev,
|
||||
pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
|
||||
&val16);
|
||||
val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
|
||||
PCI_EXP_DEVCTL_NOSNOOP_EN);
|
||||
val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
|
||||
/*
|
||||
* Older PCIe devices only support the 128 byte
|
||||
* MPS setting. Enforce the restriction.
|
||||
*/
|
||||
if (!tg3_flag(tp, CPMU_PRESENT))
|
||||
val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
|
||||
pci_write_config_word(tp->pdev,
|
||||
pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
|
||||
val16);
|
||||
val16 |= PCI_EXP_DEVCTL_PAYLOAD;
|
||||
pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
|
||||
|
||||
/* Clear error status */
|
||||
pci_write_config_word(tp->pdev,
|
||||
pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
|
||||
pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
|
||||
PCI_EXP_DEVSTA_CED |
|
||||
PCI_EXP_DEVSTA_NFED |
|
||||
PCI_EXP_DEVSTA_FED |
|
||||
|
@ -14565,9 +14543,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
|
|||
|
||||
tg3_flag_set(tp, PCI_EXPRESS);
|
||||
|
||||
pci_read_config_word(tp->pdev,
|
||||
pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
|
||||
&lnkctl);
|
||||
pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
|
||||
if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
|
||||
if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
|
||||
ASIC_REV_5906) {
|
||||
|
|
|
@ -3289,22 +3289,18 @@ static void config_pcie(struct adapter *adap)
|
|||
unsigned int log2_width, pldsize;
|
||||
unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
|
||||
|
||||
pci_read_config_word(adap->pdev,
|
||||
adap->pdev->pcie_cap + PCI_EXP_DEVCTL,
|
||||
&val);
|
||||
pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val);
|
||||
pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
|
||||
|
||||
pci_read_config_word(adap->pdev, 0x2, &devid);
|
||||
if (devid == 0x37) {
|
||||
pci_write_config_word(adap->pdev,
|
||||
adap->pdev->pcie_cap + PCI_EXP_DEVCTL,
|
||||
val & ~PCI_EXP_DEVCTL_READRQ &
|
||||
~PCI_EXP_DEVCTL_PAYLOAD);
|
||||
pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL,
|
||||
val & ~PCI_EXP_DEVCTL_READRQ &
|
||||
~PCI_EXP_DEVCTL_PAYLOAD);
|
||||
pldsize = 0;
|
||||
}
|
||||
|
||||
pci_read_config_word(adap->pdev, adap->pdev->pcie_cap + PCI_EXP_LNKCTL,
|
||||
&val);
|
||||
pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val);
|
||||
|
||||
fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
|
||||
fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
|
||||
|
@ -3425,15 +3421,13 @@ out_err:
|
|||
static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
|
||||
{
|
||||
static unsigned short speed_map[] = { 33, 66, 100, 133 };
|
||||
u32 pci_mode, pcie_cap;
|
||||
u32 pci_mode;
|
||||
|
||||
pcie_cap = pci_pcie_cap(adapter->pdev);
|
||||
if (pcie_cap) {
|
||||
if (pci_is_pcie(adapter->pdev)) {
|
||||
u16 val;
|
||||
|
||||
p->variant = PCI_VARIANT_PCIE;
|
||||
pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
|
||||
&val);
|
||||
pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
|
||||
p->width = (val >> 4) & 0x3f;
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -3694,15 +3694,7 @@ static void __devinit print_port_info(const struct net_device *dev)
|
|||
|
||||
static void __devinit enable_pcie_relaxed_ordering(struct pci_dev *dev)
|
||||
{
|
||||
u16 v;
|
||||
int pos;
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (pos > 0) {
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &v);
|
||||
v |= PCI_EXP_DEVCTL_RELAX_EN;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, v);
|
||||
}
|
||||
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -2741,11 +2741,9 @@ static void __devinit get_pci_mode(struct adapter *adapter,
|
|||
struct pci_params *p)
|
||||
{
|
||||
u16 val;
|
||||
u32 pcie_cap = pci_pcie_cap(adapter->pdev);
|
||||
|
||||
if (pcie_cap) {
|
||||
pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
|
||||
&val);
|
||||
if (pci_is_pcie(adapter->pdev)) {
|
||||
pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
|
||||
p->speed = val & PCI_EXP_LNKSTA_CLS;
|
||||
p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
|
||||
}
|
||||
|
|
|
@ -5584,16 +5584,15 @@ static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
|
|||
*/
|
||||
if (adapter->flags & FLAG_IS_QUAD_PORT) {
|
||||
struct pci_dev *us_dev = pdev->bus->self;
|
||||
int pos = pci_pcie_cap(us_dev);
|
||||
u16 devctl;
|
||||
|
||||
pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
|
||||
pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
|
||||
(devctl & ~PCI_EXP_DEVCTL_CERE));
|
||||
pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
|
||||
pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
|
||||
(devctl & ~PCI_EXP_DEVCTL_CERE));
|
||||
|
||||
e1000_power_off(pdev, sleep, wake);
|
||||
|
||||
pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
|
||||
pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
|
||||
} else {
|
||||
e1000_power_off(pdev, sleep, wake);
|
||||
}
|
||||
|
@ -5607,25 +5606,15 @@ static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
|
|||
#else
|
||||
static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
|
||||
{
|
||||
int pos;
|
||||
u16 reg16;
|
||||
|
||||
/*
|
||||
* Both device and parent should have the same ASPM setting.
|
||||
* Disable ASPM in downstream component first and then upstream.
|
||||
*/
|
||||
pos = pci_pcie_cap(pdev);
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
|
||||
reg16 &= ~state;
|
||||
pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
|
||||
pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state);
|
||||
|
||||
if (!pdev->bus->self)
|
||||
return;
|
||||
|
||||
pos = pci_pcie_cap(pdev->bus->self);
|
||||
pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, ®16);
|
||||
reg16 &= ~state;
|
||||
pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
|
||||
if (pdev->bus->self)
|
||||
pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
|
||||
state);
|
||||
}
|
||||
#endif
|
||||
static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
|
||||
|
|
|
@ -6538,28 +6538,20 @@ static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
|
|||
s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
|
||||
{
|
||||
struct igb_adapter *adapter = hw->back;
|
||||
u16 cap_offset;
|
||||
|
||||
cap_offset = adapter->pdev->pcie_cap;
|
||||
if (!cap_offset)
|
||||
if (pcie_capability_read_word(adapter->pdev, reg, value))
|
||||
return -E1000_ERR_CONFIG;
|
||||
|
||||
pci_read_config_word(adapter->pdev, cap_offset + reg, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
|
||||
{
|
||||
struct igb_adapter *adapter = hw->back;
|
||||
u16 cap_offset;
|
||||
|
||||
cap_offset = adapter->pdev->pcie_cap;
|
||||
if (!cap_offset)
|
||||
if (pcie_capability_write_word(adapter->pdev, reg, *value))
|
||||
return -E1000_ERR_CONFIG;
|
||||
|
||||
pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -7527,7 +7527,7 @@ static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
|
|||
goto skip_bad_vf_detection;
|
||||
|
||||
bdev = pdev->bus->self;
|
||||
while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
|
||||
while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
|
||||
bdev = bdev->bus->self;
|
||||
|
||||
if (!bdev)
|
||||
|
|
|
@ -141,16 +141,16 @@ int mlx4_reset(struct mlx4_dev *dev)
|
|||
/* Now restore the PCI headers */
|
||||
if (pcie_cap) {
|
||||
devctl = hca_header[(pcie_cap + PCI_EXP_DEVCTL) / 4];
|
||||
if (pci_write_config_word(dev->pdev, pcie_cap + PCI_EXP_DEVCTL,
|
||||
devctl)) {
|
||||
if (pcie_capability_write_word(dev->pdev, PCI_EXP_DEVCTL,
|
||||
devctl)) {
|
||||
err = -ENODEV;
|
||||
mlx4_err(dev, "Couldn't restore HCA PCI Express "
|
||||
"Device Control register, aborting.\n");
|
||||
goto out;
|
||||
}
|
||||
linkctl = hca_header[(pcie_cap + PCI_EXP_LNKCTL) / 4];
|
||||
if (pci_write_config_word(dev->pdev, pcie_cap + PCI_EXP_LNKCTL,
|
||||
linkctl)) {
|
||||
if (pcie_capability_write_word(dev->pdev, PCI_EXP_LNKCTL,
|
||||
linkctl)) {
|
||||
err = -ENODEV;
|
||||
mlx4_err(dev, "Couldn't restore HCA PCI Express "
|
||||
"Link control register, aborting.\n");
|
||||
|
|
|
@ -1078,22 +1078,16 @@ static int myri10ge_reset(struct myri10ge_priv *mgp)
|
|||
#ifdef CONFIG_MYRI10GE_DCA
|
||||
static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
|
||||
{
|
||||
int ret, cap, err;
|
||||
int ret;
|
||||
u16 ctl;
|
||||
|
||||
cap = pci_pcie_cap(pdev);
|
||||
if (!cap)
|
||||
return 0;
|
||||
|
||||
err = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
|
||||
if (err)
|
||||
return 0;
|
||||
pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &ctl);
|
||||
|
||||
ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
|
||||
if (ret != on) {
|
||||
ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
|
||||
ctl |= (on << 4);
|
||||
pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
|
||||
pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, ctl);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
@ -3192,18 +3186,13 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
|
|||
struct device *dev = &mgp->pdev->dev;
|
||||
int cap;
|
||||
unsigned err_cap;
|
||||
u16 val;
|
||||
u8 ext_type;
|
||||
int ret;
|
||||
|
||||
if (!myri10ge_ecrc_enable || !bridge)
|
||||
return;
|
||||
|
||||
/* check that the bridge is a root port */
|
||||
cap = pci_pcie_cap(bridge);
|
||||
pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
|
||||
ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
|
||||
if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
|
||||
if (pci_pcie_type(bridge) != PCI_EXP_TYPE_ROOT_PORT) {
|
||||
if (myri10ge_ecrc_enable > 1) {
|
||||
struct pci_dev *prev_bridge, *old_bridge = bridge;
|
||||
|
||||
|
@ -3218,11 +3207,8 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
|
|||
" to force ECRC\n");
|
||||
return;
|
||||
}
|
||||
cap = pci_pcie_cap(bridge);
|
||||
pci_read_config_word(bridge,
|
||||
cap + PCI_CAP_FLAGS, &val);
|
||||
ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
|
||||
} while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
|
||||
} while (pci_pcie_type(bridge) !=
|
||||
PCI_EXP_TYPE_ROOT_PORT);
|
||||
|
||||
dev_info(dev,
|
||||
"Forcing ECRC on non-root port %s"
|
||||
|
@ -3335,11 +3321,10 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
|
|||
int overridden = 0;
|
||||
|
||||
if (myri10ge_force_firmware == 0) {
|
||||
int link_width, exp_cap;
|
||||
int link_width;
|
||||
u16 lnk;
|
||||
|
||||
exp_cap = pci_pcie_cap(mgp->pdev);
|
||||
pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
|
||||
pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
|
||||
link_width = (lnk >> 4) & 0x3f;
|
||||
|
||||
/* Check to see if Link is less than 8 or if the
|
||||
|
|
|
@ -757,7 +757,7 @@ __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
|
|||
u16 lnk;
|
||||
|
||||
/* Get the negotiated link width and speed from PCI config space */
|
||||
pci_read_config_word(dev, dev->pcie_cap + PCI_EXP_LNKSTA, &lnk);
|
||||
pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
|
||||
|
||||
if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
|
||||
return VXGE_HW_ERR_INVALID_PCI_INFO;
|
||||
|
@ -1982,7 +1982,7 @@ u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
|
|||
struct pci_dev *dev = hldev->pdev;
|
||||
u16 lnk;
|
||||
|
||||
pci_read_config_word(dev, dev->pcie_cap + PCI_EXP_LNKSTA, &lnk);
|
||||
pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
|
||||
return (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
|
||||
}
|
||||
|
||||
|
|
|
@ -1382,7 +1382,7 @@ static void netxen_mask_aer_correctable(struct netxen_adapter *adapter)
|
|||
adapter->ahw.board_type != NETXEN_BRDTYPE_P3_10G_TP)
|
||||
return;
|
||||
|
||||
if (root->pcie_type != PCI_EXP_TYPE_ROOT_PORT)
|
||||
if (pci_pcie_type(root) != PCI_EXP_TYPE_ROOT_PORT)
|
||||
return;
|
||||
|
||||
aer_pos = pci_find_ext_capability(root, PCI_EXT_CAP_ID_ERR);
|
||||
|
|
|
@ -833,15 +833,8 @@ static void rtl_unlock_work(struct rtl8169_private *tp)
|
|||
|
||||
static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
|
||||
{
|
||||
int cap = pci_pcie_cap(pdev);
|
||||
|
||||
if (cap) {
|
||||
u16 ctl;
|
||||
|
||||
pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
|
||||
ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
|
||||
pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
|
||||
}
|
||||
pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_READRQ, force);
|
||||
}
|
||||
|
||||
struct rtl_cond {
|
||||
|
@ -4739,28 +4732,14 @@ static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
|
|||
|
||||
static void rtl_disable_clock_request(struct pci_dev *pdev)
|
||||
{
|
||||
int cap = pci_pcie_cap(pdev);
|
||||
|
||||
if (cap) {
|
||||
u16 ctl;
|
||||
|
||||
pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
|
||||
ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
|
||||
pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
|
||||
}
|
||||
pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
}
|
||||
|
||||
static void rtl_enable_clock_request(struct pci_dev *pdev)
|
||||
{
|
||||
int cap = pci_pcie_cap(pdev);
|
||||
|
||||
if (cap) {
|
||||
u16 ctl;
|
||||
|
||||
pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
|
||||
ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
|
||||
pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
|
||||
}
|
||||
pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
}
|
||||
|
||||
#define R8168_CPCMD_QUIRK_MASK (\
|
||||
|
@ -5405,14 +5384,9 @@ static void rtl_hw_start_8101(struct net_device *dev)
|
|||
tp->event_slow &= ~RxFIFOOver;
|
||||
|
||||
if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
|
||||
tp->mac_version == RTL_GIGA_MAC_VER_16) {
|
||||
int cap = pci_pcie_cap(pdev);
|
||||
|
||||
if (cap) {
|
||||
pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_NOSNOOP_EN);
|
||||
}
|
||||
}
|
||||
tp->mac_version == RTL_GIGA_MAC_VER_16)
|
||||
pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_NOSNOOP_EN);
|
||||
|
||||
RTL_W8(Cfg9346, Cfg9346_Unlock);
|
||||
|
||||
|
|
|
@ -9762,9 +9762,8 @@ static int __devinit niu_pci_init_one(struct pci_dev *pdev,
|
|||
union niu_parent_id parent_id;
|
||||
struct net_device *dev;
|
||||
struct niu *np;
|
||||
int err, pos;
|
||||
int err;
|
||||
u64 dma_mask;
|
||||
u16 val16;
|
||||
|
||||
niu_driver_version();
|
||||
|
||||
|
@ -9787,8 +9786,7 @@ static int __devinit niu_pci_init_one(struct pci_dev *pdev,
|
|||
goto err_out_disable_pdev;
|
||||
}
|
||||
|
||||
pos = pci_pcie_cap(pdev);
|
||||
if (pos <= 0) {
|
||||
if (!pci_is_pcie(pdev)) {
|
||||
dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
|
||||
goto err_out_free_res;
|
||||
}
|
||||
|
@ -9813,14 +9811,11 @@ static int __devinit niu_pci_init_one(struct pci_dev *pdev,
|
|||
goto err_out_free_dev;
|
||||
}
|
||||
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
|
||||
val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
|
||||
val16 |= (PCI_EXP_DEVCTL_CERE |
|
||||
PCI_EXP_DEVCTL_NFERE |
|
||||
PCI_EXP_DEVCTL_FERE |
|
||||
PCI_EXP_DEVCTL_URRE |
|
||||
PCI_EXP_DEVCTL_RELAX_EN);
|
||||
pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
|
||||
pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_NOSNOOP_EN,
|
||||
PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
|
||||
PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE |
|
||||
PCI_EXP_DEVCTL_RELAX_EN);
|
||||
|
||||
dma_mask = DMA_BIT_MASK(44);
|
||||
err = pci_set_dma_mask(pdev, dma_mask);
|
||||
|
|
|
@ -113,41 +113,32 @@ static void ath_pci_aspm_init(struct ath_common *common)
|
|||
struct ath_hw *ah = sc->sc_ah;
|
||||
struct pci_dev *pdev = to_pci_dev(sc->dev);
|
||||
struct pci_dev *parent;
|
||||
int pos;
|
||||
u8 aspm;
|
||||
u16 aspm;
|
||||
|
||||
if (!ah->is_pciexpress)
|
||||
return;
|
||||
|
||||
pos = pci_pcie_cap(pdev);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
parent = pdev->bus->self;
|
||||
if (!parent)
|
||||
return;
|
||||
|
||||
if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
|
||||
/* Bluetooth coexistance requires disabling ASPM. */
|
||||
pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
|
||||
aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
|
||||
pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
|
||||
pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
|
||||
PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
|
||||
|
||||
/*
|
||||
* Both upstream and downstream PCIe components should
|
||||
* have the same ASPM settings.
|
||||
*/
|
||||
pos = pci_pcie_cap(parent);
|
||||
pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
|
||||
aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
|
||||
pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
|
||||
pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
|
||||
PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
|
||||
|
||||
ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pos = pci_pcie_cap(parent);
|
||||
pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
|
||||
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
|
||||
if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
|
||||
ah->aspm_enabled = true;
|
||||
/* Initialize PCIe PM and SERDES registers. */
|
||||
|
|
|
@ -1832,10 +1832,8 @@ int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
|
|||
static inline u16
|
||||
il_pcie_link_ctl(struct il_priv *il)
|
||||
{
|
||||
int pos;
|
||||
u16 pci_lnk_ctl;
|
||||
pos = pci_pcie_cap(il->pci_dev);
|
||||
pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
|
||||
pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &pci_lnk_ctl);
|
||||
return pci_lnk_ctl;
|
||||
}
|
||||
|
||||
|
|
|
@ -675,13 +675,10 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
|
|||
static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
int pos;
|
||||
u16 pci_lnk_ctl;
|
||||
|
||||
struct pci_dev *pci_dev = trans_pcie->pci_dev;
|
||||
|
||||
pos = pci_pcie_cap(pci_dev);
|
||||
pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
|
||||
pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
|
||||
&pci_lnk_ctl);
|
||||
return pci_lnk_ctl;
|
||||
}
|
||||
|
||||
|
|
|
@ -372,13 +372,11 @@ static void rtl_pci_parse_configuration(struct pci_dev *pdev,
|
|||
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
|
||||
|
||||
u8 tmp;
|
||||
int pos;
|
||||
u8 linkctrl_reg;
|
||||
u16 linkctrl_reg;
|
||||
|
||||
/*Link Control Register */
|
||||
pos = pci_pcie_cap(pdev);
|
||||
pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
|
||||
pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
|
||||
pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
|
||||
pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
|
||||
|
||||
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
|
||||
pcipriv->ndis_adapter.linkctrl_reg);
|
||||
|
|
|
@ -469,3 +469,205 @@ void pci_cfg_access_unlock(struct pci_dev *dev)
|
|||
raw_spin_unlock_irqrestore(&pci_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
|
||||
|
||||
static inline int pcie_cap_version(const struct pci_dev *dev)
|
||||
{
|
||||
return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
|
||||
}
|
||||
|
||||
static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
|
||||
{
|
||||
int type = pci_pcie_type(dev);
|
||||
|
||||
return pcie_cap_version(dev) > 1 ||
|
||||
type == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
type == PCI_EXP_TYPE_ENDPOINT ||
|
||||
type == PCI_EXP_TYPE_LEG_END;
|
||||
}
|
||||
|
||||
static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
|
||||
{
|
||||
int type = pci_pcie_type(dev);
|
||||
|
||||
return pcie_cap_version(dev) > 1 ||
|
||||
type == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
(type == PCI_EXP_TYPE_DOWNSTREAM &&
|
||||
dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
|
||||
}
|
||||
|
||||
static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
|
||||
{
|
||||
int type = pci_pcie_type(dev);
|
||||
|
||||
return pcie_cap_version(dev) > 1 ||
|
||||
type == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
type == PCI_EXP_TYPE_RC_EC;
|
||||
}
|
||||
|
||||
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
|
||||
{
|
||||
if (!pci_is_pcie(dev))
|
||||
return false;
|
||||
|
||||
switch (pos) {
|
||||
case PCI_EXP_FLAGS_TYPE:
|
||||
return true;
|
||||
case PCI_EXP_DEVCAP:
|
||||
case PCI_EXP_DEVCTL:
|
||||
case PCI_EXP_DEVSTA:
|
||||
return pcie_cap_has_devctl(dev);
|
||||
case PCI_EXP_LNKCAP:
|
||||
case PCI_EXP_LNKCTL:
|
||||
case PCI_EXP_LNKSTA:
|
||||
return pcie_cap_has_lnkctl(dev);
|
||||
case PCI_EXP_SLTCAP:
|
||||
case PCI_EXP_SLTCTL:
|
||||
case PCI_EXP_SLTSTA:
|
||||
return pcie_cap_has_sltctl(dev);
|
||||
case PCI_EXP_RTCTL:
|
||||
case PCI_EXP_RTCAP:
|
||||
case PCI_EXP_RTSTA:
|
||||
return pcie_cap_has_rtctl(dev);
|
||||
case PCI_EXP_DEVCAP2:
|
||||
case PCI_EXP_DEVCTL2:
|
||||
case PCI_EXP_LNKCAP2:
|
||||
case PCI_EXP_LNKCTL2:
|
||||
case PCI_EXP_LNKSTA2:
|
||||
return pcie_cap_version(dev) > 1;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Note that these accessor functions are only for the "PCI Express
|
||||
* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
|
||||
* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
|
||||
*/
|
||||
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
|
||||
{
|
||||
int ret;
|
||||
|
||||
*val = 0;
|
||||
if (pos & 1)
|
||||
return -EINVAL;
|
||||
|
||||
if (pcie_capability_reg_implemented(dev, pos)) {
|
||||
ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
||||
/*
|
||||
* Reset *val to 0 if pci_read_config_word() fails, it may
|
||||
* have been written as 0xFFFF if hardware error happens
|
||||
* during pci_read_config_word().
|
||||
*/
|
||||
if (ret)
|
||||
*val = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* For Functions that do not implement the Slot Capabilities,
|
||||
* Slot Status, and Slot Control registers, these spaces must
|
||||
* be hardwired to 0b, with the exception of the Presence Detect
|
||||
* State bit in the Slot Status register of Downstream Ports,
|
||||
* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
|
||||
*/
|
||||
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
|
||||
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
||||
*val = PCI_EXP_SLTSTA_PDS;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_capability_read_word);
|
||||
|
||||
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
|
||||
{
|
||||
int ret;
|
||||
|
||||
*val = 0;
|
||||
if (pos & 3)
|
||||
return -EINVAL;
|
||||
|
||||
if (pcie_capability_reg_implemented(dev, pos)) {
|
||||
ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
||||
/*
|
||||
* Reset *val to 0 if pci_read_config_dword() fails, it may
|
||||
* have been written as 0xFFFFFFFF if hardware error happens
|
||||
* during pci_read_config_dword().
|
||||
*/
|
||||
if (ret)
|
||||
*val = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
|
||||
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
||||
*val = PCI_EXP_SLTSTA_PDS;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_capability_read_dword);
|
||||
|
||||
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
|
||||
{
|
||||
if (pos & 1)
|
||||
return -EINVAL;
|
||||
|
||||
if (!pcie_capability_reg_implemented(dev, pos))
|
||||
return 0;
|
||||
|
||||
return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_capability_write_word);
|
||||
|
||||
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
|
||||
{
|
||||
if (pos & 3)
|
||||
return -EINVAL;
|
||||
|
||||
if (!pcie_capability_reg_implemented(dev, pos))
|
||||
return 0;
|
||||
|
||||
return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_capability_write_dword);
|
||||
|
||||
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
|
||||
u16 clear, u16 set)
|
||||
{
|
||||
int ret;
|
||||
u16 val;
|
||||
|
||||
ret = pcie_capability_read_word(dev, pos, &val);
|
||||
if (!ret) {
|
||||
val &= ~clear;
|
||||
val |= set;
|
||||
ret = pcie_capability_write_word(dev, pos, val);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
|
||||
|
||||
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
|
||||
u32 clear, u32 set)
|
||||
{
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ret = pcie_capability_read_dword(dev, pos, &val);
|
||||
if (!ret) {
|
||||
val &= ~clear;
|
||||
val |= set;
|
||||
ret = pcie_capability_write_dword(dev, pos, val);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
|
||||
|
|
|
@ -81,16 +81,12 @@ static struct list_head __initdata dummy_slots = LIST_HEAD_INIT(dummy_slots);
|
|||
/* Dummy driver for dumplicate name detection */
|
||||
static int __init dummy_probe(struct pcie_device *dev)
|
||||
{
|
||||
int pos;
|
||||
u32 slot_cap;
|
||||
acpi_handle handle;
|
||||
struct dummy_slot *slot, *tmp;
|
||||
struct pci_dev *pdev = dev->port;
|
||||
|
||||
pos = pci_pcie_cap(pdev);
|
||||
if (!pos)
|
||||
return -ENODEV;
|
||||
pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &slot_cap);
|
||||
pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
|
||||
slot = kzalloc(sizeof(*slot), GFP_KERNEL);
|
||||
if (!slot)
|
||||
return -ENOMEM;
|
||||
|
|
|
@ -44,25 +44,25 @@
|
|||
static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
|
||||
{
|
||||
struct pci_dev *dev = ctrl->pcie->port;
|
||||
return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
|
||||
return pcie_capability_read_word(dev, reg, value);
|
||||
}
|
||||
|
||||
static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
|
||||
{
|
||||
struct pci_dev *dev = ctrl->pcie->port;
|
||||
return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
|
||||
return pcie_capability_read_dword(dev, reg, value);
|
||||
}
|
||||
|
||||
static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
|
||||
{
|
||||
struct pci_dev *dev = ctrl->pcie->port;
|
||||
return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
|
||||
return pcie_capability_write_word(dev, reg, value);
|
||||
}
|
||||
|
||||
static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
|
||||
{
|
||||
struct pci_dev *dev = ctrl->pcie->port;
|
||||
return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
|
||||
return pcie_capability_write_dword(dev, reg, value);
|
||||
}
|
||||
|
||||
/* Power Control Command */
|
||||
|
@ -855,10 +855,6 @@ struct controller *pcie_init(struct pcie_device *dev)
|
|||
goto abort;
|
||||
}
|
||||
ctrl->pcie = dev;
|
||||
if (!pci_pcie_cap(pdev)) {
|
||||
ctrl_err(ctrl, "Cannot find PCI Express capability\n");
|
||||
goto abort_ctrl;
|
||||
}
|
||||
if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
|
||||
ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
|
||||
goto abort_ctrl;
|
||||
|
|
|
@ -96,17 +96,11 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
|
|||
static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
|
||||
{
|
||||
int pos;
|
||||
u16 reg16;
|
||||
u32 reg32;
|
||||
|
||||
if (!hpp)
|
||||
return;
|
||||
|
||||
/* Find PCI Express capability */
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
if (hpp->revision > 1) {
|
||||
dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
|
||||
hpp->revision);
|
||||
|
@ -114,17 +108,13 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
|
|||
}
|
||||
|
||||
/* Initialize Device Control Register */
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16);
|
||||
reg16 = (reg16 & hpp->pci_exp_devctl_and) | hpp->pci_exp_devctl_or;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
|
||||
pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
|
||||
~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
|
||||
|
||||
/* Initialize Link Control Register */
|
||||
if (dev->subordinate) {
|
||||
pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, ®16);
|
||||
reg16 = (reg16 & hpp->pci_exp_lnkctl_and)
|
||||
| hpp->pci_exp_lnkctl_or;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16);
|
||||
}
|
||||
if (dev->subordinate)
|
||||
pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
|
||||
~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
|
||||
|
||||
/* Find Advanced Error Reporting Enhanced Capability */
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
|
||||
|
|
|
@ -433,8 +433,8 @@ static int sriov_init(struct pci_dev *dev, int pos)
|
|||
struct resource *res;
|
||||
struct pci_dev *pdev;
|
||||
|
||||
if (dev->pcie_type != PCI_EXP_TYPE_RC_END &&
|
||||
dev->pcie_type != PCI_EXP_TYPE_ENDPOINT)
|
||||
if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END &&
|
||||
pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT)
|
||||
return -ENODEV;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
|
||||
|
@ -503,7 +503,7 @@ found:
|
|||
iov->self = dev;
|
||||
pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
|
||||
pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
|
||||
if (dev->pcie_type == PCI_EXP_TYPE_RC_END)
|
||||
if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)
|
||||
iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link);
|
||||
|
||||
if (pdev)
|
||||
|
|
|
@ -280,8 +280,12 @@ static long local_pci_probe(void *_ddi)
|
|||
{
|
||||
struct drv_dev_and_id *ddi = _ddi;
|
||||
struct device *dev = &ddi->dev->dev;
|
||||
struct device *parent = dev->parent;
|
||||
int rc;
|
||||
|
||||
/* The parent bridge must be in active state when probing */
|
||||
if (parent)
|
||||
pm_runtime_get_sync(parent);
|
||||
/* Unbound PCI devices are always set to disabled and suspended.
|
||||
* During probe, the device is set to enabled and active and the
|
||||
* usage count is incremented. If the driver supports runtime PM,
|
||||
|
@ -298,6 +302,8 @@ static long local_pci_probe(void *_ddi)
|
|||
pm_runtime_set_suspended(dev);
|
||||
pm_runtime_put_noidle(dev);
|
||||
}
|
||||
if (parent)
|
||||
pm_runtime_put(parent);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
|
@ -458,6 +458,40 @@ boot_vga_show(struct device *dev, struct device_attribute *attr, char *buf)
|
|||
}
|
||||
struct device_attribute vga_attr = __ATTR_RO(boot_vga);
|
||||
|
||||
static void
|
||||
pci_config_pm_runtime_get(struct pci_dev *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device *parent = dev->parent;
|
||||
|
||||
if (parent)
|
||||
pm_runtime_get_sync(parent);
|
||||
pm_runtime_get_noresume(dev);
|
||||
/*
|
||||
* pdev->current_state is set to PCI_D3cold during suspending,
|
||||
* so wait until suspending completes
|
||||
*/
|
||||
pm_runtime_barrier(dev);
|
||||
/*
|
||||
* Only need to resume devices in D3cold, because config
|
||||
* registers are still accessible for devices suspended but
|
||||
* not in D3cold.
|
||||
*/
|
||||
if (pdev->current_state == PCI_D3cold)
|
||||
pm_runtime_resume(dev);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_config_pm_runtime_put(struct pci_dev *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device *parent = dev->parent;
|
||||
|
||||
pm_runtime_put(dev);
|
||||
if (parent)
|
||||
pm_runtime_put_sync(parent);
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
pci_read_config(struct file *filp, struct kobject *kobj,
|
||||
struct bin_attribute *bin_attr,
|
||||
|
@ -484,6 +518,8 @@ pci_read_config(struct file *filp, struct kobject *kobj,
|
|||
size = count;
|
||||
}
|
||||
|
||||
pci_config_pm_runtime_get(dev);
|
||||
|
||||
if ((off & 1) && size) {
|
||||
u8 val;
|
||||
pci_user_read_config_byte(dev, off, &val);
|
||||
|
@ -529,6 +565,8 @@ pci_read_config(struct file *filp, struct kobject *kobj,
|
|||
--size;
|
||||
}
|
||||
|
||||
pci_config_pm_runtime_put(dev);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
|
@ -549,6 +587,8 @@ pci_write_config(struct file* filp, struct kobject *kobj,
|
|||
count = size;
|
||||
}
|
||||
|
||||
pci_config_pm_runtime_get(dev);
|
||||
|
||||
if ((off & 1) && size) {
|
||||
pci_user_write_config_byte(dev, off, data[off - init_off]);
|
||||
off++;
|
||||
|
@ -587,6 +627,8 @@ pci_write_config(struct file* filp, struct kobject *kobj,
|
|||
--size;
|
||||
}
|
||||
|
||||
pci_config_pm_runtime_put(dev);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
|
|
|
@ -253,38 +253,6 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
|
|||
return pos;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
|
||||
* @dev: PCI device to check
|
||||
*
|
||||
* Like pci_pcie_cap() but also checks that the PCIe capability version is
|
||||
* >= 2. Note that v1 capability structures could be sparse in that not
|
||||
* all register fields were required. v2 requires the entire structure to
|
||||
* be present size wise, while still allowing for non-implemented registers
|
||||
* to exist but they must be hardwired to 0.
|
||||
*
|
||||
* Due to the differences in the versions of capability structures, one
|
||||
* must be careful not to try and access non-existant registers that may
|
||||
* exist in early versions - v1 - of Express devices.
|
||||
*
|
||||
* Returns the offset of the PCIe capability structure as long as the
|
||||
* capability version is >= 2; otherwise 0 is returned.
|
||||
*/
|
||||
static int pci_pcie_cap2(struct pci_dev *dev)
|
||||
{
|
||||
u16 flags;
|
||||
int pos;
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (pos) {
|
||||
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
|
||||
if ((flags & PCI_EXP_FLAGS_VERS) < 2)
|
||||
pos = 0;
|
||||
}
|
||||
|
||||
return pos;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_find_ext_capability - Find an extended capability
|
||||
* @dev: PCI device to query
|
||||
|
@ -854,21 +822,6 @@ EXPORT_SYMBOL(pci_choose_state);
|
|||
|
||||
#define PCI_EXP_SAVE_REGS 7
|
||||
|
||||
#define pcie_cap_has_devctl(type, flags) 1
|
||||
#define pcie_cap_has_lnkctl(type, flags) \
|
||||
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
|
||||
(type == PCI_EXP_TYPE_ROOT_PORT || \
|
||||
type == PCI_EXP_TYPE_ENDPOINT || \
|
||||
type == PCI_EXP_TYPE_LEG_END))
|
||||
#define pcie_cap_has_sltctl(type, flags) \
|
||||
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
|
||||
((type == PCI_EXP_TYPE_ROOT_PORT) || \
|
||||
(type == PCI_EXP_TYPE_DOWNSTREAM && \
|
||||
(flags & PCI_EXP_FLAGS_SLOT))))
|
||||
#define pcie_cap_has_rtctl(type, flags) \
|
||||
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
|
||||
(type == PCI_EXP_TYPE_ROOT_PORT || \
|
||||
type == PCI_EXP_TYPE_RC_EC))
|
||||
|
||||
static struct pci_cap_saved_state *pci_find_saved_cap(
|
||||
struct pci_dev *pci_dev, char cap)
|
||||
|
@ -885,13 +838,11 @@ static struct pci_cap_saved_state *pci_find_saved_cap(
|
|||
|
||||
static int pci_save_pcie_state(struct pci_dev *dev)
|
||||
{
|
||||
int pos, i = 0;
|
||||
int i = 0;
|
||||
struct pci_cap_saved_state *save_state;
|
||||
u16 *cap;
|
||||
u16 flags;
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos)
|
||||
if (!pci_is_pcie(dev))
|
||||
return 0;
|
||||
|
||||
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
|
||||
|
@ -899,60 +850,37 @@ static int pci_save_pcie_state(struct pci_dev *dev)
|
|||
dev_err(&dev->dev, "buffer not found in %s\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
cap = (u16 *)&save_state->cap.data[0];
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
|
||||
pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
|
||||
pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
|
||||
pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
|
||||
pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
|
||||
pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
|
||||
|
||||
if (pcie_cap_has_devctl(dev->pcie_type, flags))
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
|
||||
if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
|
||||
pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
|
||||
if (pcie_cap_has_sltctl(dev->pcie_type, flags))
|
||||
pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
|
||||
if (pcie_cap_has_rtctl(dev->pcie_type, flags))
|
||||
pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
|
||||
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return 0;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
|
||||
pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
|
||||
pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pci_restore_pcie_state(struct pci_dev *dev)
|
||||
{
|
||||
int i = 0, pos;
|
||||
int i = 0;
|
||||
struct pci_cap_saved_state *save_state;
|
||||
u16 *cap;
|
||||
u16 flags;
|
||||
|
||||
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
|
||||
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
||||
if (!save_state || pos <= 0)
|
||||
if (!save_state)
|
||||
return;
|
||||
|
||||
cap = (u16 *)&save_state->cap.data[0];
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
|
||||
|
||||
if (pcie_cap_has_devctl(dev->pcie_type, flags))
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
|
||||
if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
|
||||
pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
|
||||
if (pcie_cap_has_sltctl(dev->pcie_type, flags))
|
||||
pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
|
||||
if (pcie_cap_has_rtctl(dev->pcie_type, flags))
|
||||
pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
|
||||
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
|
||||
pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
|
||||
pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
|
||||
pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
|
||||
pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
|
||||
pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
|
||||
pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
|
||||
pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
|
||||
pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
|
||||
pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
|
||||
}
|
||||
|
||||
|
||||
|
@ -1941,6 +1869,7 @@ void pci_pm_init(struct pci_dev *dev)
|
|||
dev->pm_cap = pm;
|
||||
dev->d3_delay = PCI_PM_D3_WAIT;
|
||||
dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
|
||||
dev->d3cold_allowed = true;
|
||||
|
||||
dev->d1_support = false;
|
||||
dev->d2_support = false;
|
||||
|
@ -2066,35 +1995,24 @@ void pci_free_cap_save_buffers(struct pci_dev *dev)
|
|||
*/
|
||||
void pci_enable_ari(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u32 cap;
|
||||
u16 ctrl;
|
||||
struct pci_dev *bridge;
|
||||
|
||||
if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
|
||||
return;
|
||||
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
|
||||
if (!pos)
|
||||
if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
|
||||
return;
|
||||
|
||||
bridge = dev->bus->self;
|
||||
if (!bridge)
|
||||
return;
|
||||
|
||||
/* ARI is a PCIe cap v2 feature */
|
||||
pos = pci_pcie_cap2(bridge);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
|
||||
pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
|
||||
if (!(cap & PCI_EXP_DEVCAP2_ARI))
|
||||
return;
|
||||
|
||||
pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
|
||||
ctrl |= PCI_EXP_DEVCTL2_ARI;
|
||||
pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
|
||||
|
||||
pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
|
||||
bridge->ari_enabled = 1;
|
||||
}
|
||||
|
||||
|
@ -2109,20 +2027,14 @@ void pci_enable_ari(struct pci_dev *dev)
|
|||
*/
|
||||
void pci_enable_ido(struct pci_dev *dev, unsigned long type)
|
||||
{
|
||||
int pos;
|
||||
u16 ctrl;
|
||||
u16 ctrl = 0;
|
||||
|
||||
/* ID-based Ordering is a PCIe cap v2 feature */
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
||||
if (type & PCI_EXP_IDO_REQUEST)
|
||||
ctrl |= PCI_EXP_IDO_REQ_EN;
|
||||
if (type & PCI_EXP_IDO_COMPLETION)
|
||||
ctrl |= PCI_EXP_IDO_CMP_EN;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
||||
if (ctrl)
|
||||
pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_enable_ido);
|
||||
|
||||
|
@ -2133,20 +2045,14 @@ EXPORT_SYMBOL(pci_enable_ido);
|
|||
*/
|
||||
void pci_disable_ido(struct pci_dev *dev, unsigned long type)
|
||||
{
|
||||
int pos;
|
||||
u16 ctrl;
|
||||
u16 ctrl = 0;
|
||||
|
||||
/* ID-based Ordering is a PCIe cap v2 feature */
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
||||
if (type & PCI_EXP_IDO_REQUEST)
|
||||
ctrl &= ~PCI_EXP_IDO_REQ_EN;
|
||||
ctrl |= PCI_EXP_IDO_REQ_EN;
|
||||
if (type & PCI_EXP_IDO_COMPLETION)
|
||||
ctrl &= ~PCI_EXP_IDO_CMP_EN;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
||||
ctrl |= PCI_EXP_IDO_CMP_EN;
|
||||
if (ctrl)
|
||||
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_disable_ido);
|
||||
|
||||
|
@ -2171,17 +2077,11 @@ EXPORT_SYMBOL(pci_disable_ido);
|
|||
*/
|
||||
int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
|
||||
{
|
||||
int pos;
|
||||
u32 cap;
|
||||
u16 ctrl;
|
||||
int ret;
|
||||
|
||||
/* OBFF is a PCIe cap v2 feature */
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return -ENOTSUPP;
|
||||
|
||||
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
|
||||
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
|
||||
if (!(cap & PCI_EXP_OBFF_MASK))
|
||||
return -ENOTSUPP; /* no OBFF support at all */
|
||||
|
||||
|
@ -2192,7 +2092,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
|
|||
return ret;
|
||||
}
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
|
||||
if (cap & PCI_EXP_OBFF_WAKE)
|
||||
ctrl |= PCI_EXP_OBFF_WAKE_EN;
|
||||
else {
|
||||
|
@ -2210,7 +2110,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
|
|||
return -ENOTSUPP;
|
||||
}
|
||||
}
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
||||
pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -2224,17 +2124,7 @@ EXPORT_SYMBOL(pci_enable_obff);
|
|||
*/
|
||||
void pci_disable_obff(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u16 ctrl;
|
||||
|
||||
/* OBFF is a PCIe cap v2 feature */
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
||||
ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
||||
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_disable_obff);
|
||||
|
||||
|
@ -2247,15 +2137,9 @@ EXPORT_SYMBOL(pci_disable_obff);
|
|||
*/
|
||||
static bool pci_ltr_supported(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u32 cap;
|
||||
|
||||
/* LTR is a PCIe cap v2 feature */
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return false;
|
||||
|
||||
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
|
||||
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
|
||||
|
||||
return cap & PCI_EXP_DEVCAP2_LTR;
|
||||
}
|
||||
|
@ -2272,22 +2156,15 @@ static bool pci_ltr_supported(struct pci_dev *dev)
|
|||
*/
|
||||
int pci_enable_ltr(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u16 ctrl;
|
||||
int ret;
|
||||
|
||||
if (!pci_ltr_supported(dev))
|
||||
return -ENOTSUPP;
|
||||
|
||||
/* LTR is a PCIe cap v2 feature */
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return -ENOTSUPP;
|
||||
|
||||
/* Only primary function can enable/disable LTR */
|
||||
if (PCI_FUNC(dev->devfn) != 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (!pci_ltr_supported(dev))
|
||||
return -ENOTSUPP;
|
||||
|
||||
/* Enable upstream ports first */
|
||||
if (dev->bus->self) {
|
||||
ret = pci_enable_ltr(dev->bus->self);
|
||||
|
@ -2295,11 +2172,7 @@ int pci_enable_ltr(struct pci_dev *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
||||
ctrl |= PCI_EXP_LTR_EN;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
||||
|
||||
return 0;
|
||||
return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_enable_ltr);
|
||||
|
||||
|
@ -2309,24 +2182,14 @@ EXPORT_SYMBOL(pci_enable_ltr);
|
|||
*/
|
||||
void pci_disable_ltr(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u16 ctrl;
|
||||
|
||||
if (!pci_ltr_supported(dev))
|
||||
return;
|
||||
|
||||
/* LTR is a PCIe cap v2 feature */
|
||||
pos = pci_pcie_cap2(dev);
|
||||
if (!pos)
|
||||
return;
|
||||
|
||||
/* Only primary function can enable/disable LTR */
|
||||
if (PCI_FUNC(dev->devfn) != 0)
|
||||
return;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
|
||||
ctrl &= ~PCI_EXP_LTR_EN;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
|
||||
if (!pci_ltr_supported(dev))
|
||||
return;
|
||||
|
||||
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_disable_ltr);
|
||||
|
||||
|
@ -2409,9 +2272,6 @@ void pci_enable_acs(struct pci_dev *dev)
|
|||
if (!pci_acs_enable)
|
||||
return;
|
||||
|
||||
if (!pci_is_pcie(dev))
|
||||
return;
|
||||
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
|
||||
if (!pos)
|
||||
return;
|
||||
|
@ -2459,8 +2319,8 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
|
|||
acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
|
||||
PCI_ACS_EC | PCI_ACS_DT);
|
||||
|
||||
if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM ||
|
||||
pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
|
||||
pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
pdev->multifunction) {
|
||||
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
|
||||
if (!pos)
|
||||
|
@ -3176,15 +3036,10 @@ EXPORT_SYMBOL(pci_set_dma_seg_boundary);
|
|||
static int pcie_flr(struct pci_dev *dev, int probe)
|
||||
{
|
||||
int i;
|
||||
int pos;
|
||||
u32 cap;
|
||||
u16 status, control;
|
||||
u16 status;
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos)
|
||||
return -ENOTTY;
|
||||
|
||||
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
|
||||
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
|
||||
if (!(cap & PCI_EXP_DEVCAP_FLR))
|
||||
return -ENOTTY;
|
||||
|
||||
|
@ -3196,7 +3051,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
|
|||
if (i)
|
||||
msleep((1 << (i - 1)) * 100);
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
|
||||
if (!(status & PCI_EXP_DEVSTA_TRPND))
|
||||
goto clear;
|
||||
}
|
||||
|
@ -3205,9 +3060,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
|
|||
"proceeding with reset anyway\n");
|
||||
|
||||
clear:
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
|
||||
control |= PCI_EXP_DEVCTL_BCR_FLR;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
|
||||
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
|
||||
|
||||
msleep(100);
|
||||
|
||||
|
@ -3575,18 +3428,11 @@ EXPORT_SYMBOL(pcix_set_mmrbc);
|
|||
*/
|
||||
int pcie_get_readrq(struct pci_dev *dev)
|
||||
{
|
||||
int ret, cap;
|
||||
u16 ctl;
|
||||
|
||||
cap = pci_pcie_cap(dev);
|
||||
if (!cap)
|
||||
return -EINVAL;
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
|
||||
|
||||
ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
||||
if (!ret)
|
||||
ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
|
||||
|
||||
return ret;
|
||||
return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_get_readrq);
|
||||
|
||||
|
@ -3600,19 +3446,11 @@ EXPORT_SYMBOL(pcie_get_readrq);
|
|||
*/
|
||||
int pcie_set_readrq(struct pci_dev *dev, int rq)
|
||||
{
|
||||
int cap, err = -EINVAL;
|
||||
u16 ctl, v;
|
||||
u16 v;
|
||||
|
||||
if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
|
||||
goto out;
|
||||
return -EINVAL;
|
||||
|
||||
cap = pci_pcie_cap(dev);
|
||||
if (!cap)
|
||||
goto out;
|
||||
|
||||
err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
||||
if (err)
|
||||
goto out;
|
||||
/*
|
||||
* If using the "performance" PCIe config, we clamp the
|
||||
* read rq size to the max packet size to prevent the
|
||||
|
@ -3630,14 +3468,8 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
|
|||
|
||||
v = (ffs(rq) - 8) << 12;
|
||||
|
||||
if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
|
||||
ctl &= ~PCI_EXP_DEVCTL_READRQ;
|
||||
ctl |= v;
|
||||
err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
|
||||
}
|
||||
|
||||
out:
|
||||
return err;
|
||||
return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_READRQ, v);
|
||||
}
|
||||
EXPORT_SYMBOL(pcie_set_readrq);
|
||||
|
||||
|
@ -3650,18 +3482,11 @@ EXPORT_SYMBOL(pcie_set_readrq);
|
|||
*/
|
||||
int pcie_get_mps(struct pci_dev *dev)
|
||||
{
|
||||
int ret, cap;
|
||||
u16 ctl;
|
||||
|
||||
cap = pci_pcie_cap(dev);
|
||||
if (!cap)
|
||||
return -EINVAL;
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
|
||||
|
||||
ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
||||
if (!ret)
|
||||
ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
|
||||
|
||||
return ret;
|
||||
return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -3674,32 +3499,18 @@ int pcie_get_mps(struct pci_dev *dev)
|
|||
*/
|
||||
int pcie_set_mps(struct pci_dev *dev, int mps)
|
||||
{
|
||||
int cap, err = -EINVAL;
|
||||
u16 ctl, v;
|
||||
u16 v;
|
||||
|
||||
if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
|
||||
goto out;
|
||||
return -EINVAL;
|
||||
|
||||
v = ffs(mps) - 8;
|
||||
if (v > dev->pcie_mpss)
|
||||
goto out;
|
||||
return -EINVAL;
|
||||
v <<= 5;
|
||||
|
||||
cap = pci_pcie_cap(dev);
|
||||
if (!cap)
|
||||
goto out;
|
||||
|
||||
err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
|
||||
ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
|
||||
ctl |= v;
|
||||
err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
|
||||
}
|
||||
out:
|
||||
return err;
|
||||
return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_PAYLOAD, v);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -288,7 +288,7 @@ static struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
|
|||
while (1) {
|
||||
if (!pci_is_pcie(dev))
|
||||
break;
|
||||
if (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
|
||||
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
|
||||
return dev;
|
||||
if (!dev->bus->self)
|
||||
break;
|
||||
|
|
|
@ -81,10 +81,11 @@ bool pci_aer_available(void)
|
|||
static int set_device_error_reporting(struct pci_dev *dev, void *data)
|
||||
{
|
||||
bool enable = *((bool *)data);
|
||||
int type = pci_pcie_type(dev);
|
||||
|
||||
if ((dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) ||
|
||||
(dev->pcie_type == PCI_EXP_TYPE_UPSTREAM) ||
|
||||
(dev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)) {
|
||||
if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
|
||||
(type == PCI_EXP_TYPE_UPSTREAM) ||
|
||||
(type == PCI_EXP_TYPE_DOWNSTREAM)) {
|
||||
if (enable)
|
||||
pci_enable_pcie_error_reporting(dev);
|
||||
else
|
||||
|
@ -121,19 +122,17 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev,
|
|||
static void aer_enable_rootport(struct aer_rpc *rpc)
|
||||
{
|
||||
struct pci_dev *pdev = rpc->rpd->port;
|
||||
int pos, aer_pos;
|
||||
int aer_pos;
|
||||
u16 reg16;
|
||||
u32 reg32;
|
||||
|
||||
pos = pci_pcie_cap(pdev);
|
||||
/* Clear PCIe Capability's Device Status */
|
||||
pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, ®16);
|
||||
pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16);
|
||||
pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16);
|
||||
pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
|
||||
|
||||
/* Disable system error generation in response to error messages */
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_RTCTL, ®16);
|
||||
reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK);
|
||||
pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16);
|
||||
pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
|
||||
SYSTEM_ERROR_INTR_ON_MESG_MASK);
|
||||
|
||||
aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
|
||||
/* Clear error status */
|
||||
|
@ -395,9 +394,8 @@ static void aer_error_resume(struct pci_dev *dev)
|
|||
u16 reg16;
|
||||
|
||||
/* Clean up Root device status */
|
||||
pos = pci_pcie_cap(dev);
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, ®16);
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16);
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVSTA, ®16);
|
||||
pcie_capability_write_word(dev, PCI_EXP_DEVSTA, reg16);
|
||||
|
||||
/* Clean AER Root Error Status */
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
|
||||
|
|
|
@ -60,7 +60,7 @@ static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
|
|||
p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
|
||||
if (p->flags & ACPI_HEST_GLOBAL) {
|
||||
if ((pci_is_pcie(info->pci_dev) &&
|
||||
info->pci_dev->pcie_type == pcie_type) || bridge)
|
||||
pci_pcie_type(info->pci_dev) == pcie_type) || bridge)
|
||||
ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
|
||||
} else
|
||||
if (hest_match_pci(p, info->pci_dev))
|
||||
|
|
|
@ -32,53 +32,28 @@ static bool nosourceid;
|
|||
module_param(forceload, bool, 0);
|
||||
module_param(nosourceid, bool, 0);
|
||||
|
||||
#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
|
||||
PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
|
||||
|
||||
int pci_enable_pcie_error_reporting(struct pci_dev *dev)
|
||||
{
|
||||
u16 reg16 = 0;
|
||||
int pos;
|
||||
|
||||
if (pcie_aer_get_firmware_first(dev))
|
||||
return -EIO;
|
||||
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
|
||||
if (!pos)
|
||||
if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))
|
||||
return -EIO;
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos)
|
||||
return -EIO;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16);
|
||||
reg16 |= (PCI_EXP_DEVCTL_CERE |
|
||||
PCI_EXP_DEVCTL_NFERE |
|
||||
PCI_EXP_DEVCTL_FERE |
|
||||
PCI_EXP_DEVCTL_URRE);
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
|
||||
|
||||
return 0;
|
||||
return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
|
||||
|
||||
int pci_disable_pcie_error_reporting(struct pci_dev *dev)
|
||||
{
|
||||
u16 reg16 = 0;
|
||||
int pos;
|
||||
|
||||
if (pcie_aer_get_firmware_first(dev))
|
||||
return -EIO;
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos)
|
||||
return -EIO;
|
||||
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16);
|
||||
reg16 &= ~(PCI_EXP_DEVCTL_CERE |
|
||||
PCI_EXP_DEVCTL_NFERE |
|
||||
PCI_EXP_DEVCTL_FERE |
|
||||
PCI_EXP_DEVCTL_URRE);
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
|
||||
|
||||
return 0;
|
||||
return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_AER_FLAGS);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
|
||||
|
||||
|
@ -151,18 +126,12 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
|
|||
*/
|
||||
if (atomic_read(&dev->enable_cnt) == 0)
|
||||
return false;
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos)
|
||||
return false;
|
||||
|
||||
/* Check if AER is enabled */
|
||||
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16);
|
||||
if (!(reg16 & (
|
||||
PCI_EXP_DEVCTL_CERE |
|
||||
PCI_EXP_DEVCTL_NFERE |
|
||||
PCI_EXP_DEVCTL_FERE |
|
||||
PCI_EXP_DEVCTL_URRE)))
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
|
||||
if (!(reg16 & PCI_EXP_AER_FLAGS))
|
||||
return false;
|
||||
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
|
||||
if (!pos)
|
||||
return false;
|
||||
|
@ -465,7 +434,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
|
|||
|
||||
if (driver && driver->reset_link) {
|
||||
status = driver->reset_link(udev);
|
||||
} else if (udev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
|
||||
} else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
||||
status = default_downstream_reset_link(udev);
|
||||
} else {
|
||||
dev_printk(KERN_DEBUG, &dev->dev,
|
||||
|
|
|
@ -125,21 +125,16 @@ static int policy_to_clkpm_state(struct pcie_link_state *link)
|
|||
|
||||
static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
|
||||
{
|
||||
int pos;
|
||||
u16 reg16;
|
||||
struct pci_dev *child;
|
||||
struct pci_bus *linkbus = link->pdev->subordinate;
|
||||
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
||||
pos = pci_pcie_cap(child);
|
||||
if (!pos)
|
||||
return;
|
||||
pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
|
||||
if (enable)
|
||||
reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
|
||||
pcie_capability_set_word(child, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
else
|
||||
reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
|
||||
pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16);
|
||||
pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
}
|
||||
link->clkpm_enabled = !!enable;
|
||||
}
|
||||
|
@ -157,7 +152,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
|
|||
|
||||
static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
|
||||
{
|
||||
int pos, capable = 1, enabled = 1;
|
||||
int capable = 1, enabled = 1;
|
||||
u32 reg32;
|
||||
u16 reg16;
|
||||
struct pci_dev *child;
|
||||
|
@ -165,16 +160,13 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
|
|||
|
||||
/* All functions should have the same cap and state, take the worst */
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
||||
pos = pci_pcie_cap(child);
|
||||
if (!pos)
|
||||
return;
|
||||
pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32);
|
||||
pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
|
||||
if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
|
||||
capable = 0;
|
||||
enabled = 0;
|
||||
break;
|
||||
}
|
||||
pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
|
||||
pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
|
||||
if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
|
||||
enabled = 0;
|
||||
}
|
||||
|
@ -190,7 +182,7 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
|
|||
*/
|
||||
static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
|
||||
{
|
||||
int ppos, cpos, same_clock = 1;
|
||||
int same_clock = 1;
|
||||
u16 reg16, parent_reg, child_reg[8];
|
||||
unsigned long start_jiffies;
|
||||
struct pci_dev *child, *parent = link->pdev;
|
||||
|
@ -203,46 +195,43 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
|
|||
BUG_ON(!pci_is_pcie(child));
|
||||
|
||||
/* Check downstream component if bit Slot Clock Configuration is 1 */
|
||||
cpos = pci_pcie_cap(child);
|
||||
pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16);
|
||||
pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
|
||||
if (!(reg16 & PCI_EXP_LNKSTA_SLC))
|
||||
same_clock = 0;
|
||||
|
||||
/* Check upstream component if bit Slot Clock Configuration is 1 */
|
||||
ppos = pci_pcie_cap(parent);
|
||||
pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
|
||||
pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
|
||||
if (!(reg16 & PCI_EXP_LNKSTA_SLC))
|
||||
same_clock = 0;
|
||||
|
||||
/* Configure downstream component, all functions */
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
||||
cpos = pci_pcie_cap(child);
|
||||
pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16);
|
||||
pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
|
||||
child_reg[PCI_FUNC(child->devfn)] = reg16;
|
||||
if (same_clock)
|
||||
reg16 |= PCI_EXP_LNKCTL_CCC;
|
||||
else
|
||||
reg16 &= ~PCI_EXP_LNKCTL_CCC;
|
||||
pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
|
||||
pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
|
||||
}
|
||||
|
||||
/* Configure upstream component */
|
||||
pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16);
|
||||
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
|
||||
parent_reg = reg16;
|
||||
if (same_clock)
|
||||
reg16 |= PCI_EXP_LNKCTL_CCC;
|
||||
else
|
||||
reg16 &= ~PCI_EXP_LNKCTL_CCC;
|
||||
pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
|
||||
pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
|
||||
|
||||
/* Retrain link */
|
||||
reg16 |= PCI_EXP_LNKCTL_RL;
|
||||
pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
|
||||
pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
|
||||
|
||||
/* Wait for link training end. Break out after waiting for timeout */
|
||||
start_jiffies = jiffies;
|
||||
for (;;) {
|
||||
pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
|
||||
pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
|
||||
if (!(reg16 & PCI_EXP_LNKSTA_LT))
|
||||
break;
|
||||
if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
|
||||
|
@ -255,12 +244,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
|
|||
/* Training failed. Restore common clock configurations */
|
||||
dev_printk(KERN_ERR, &parent->dev,
|
||||
"ASPM: Could not configure common clock\n");
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
||||
cpos = pci_pcie_cap(child);
|
||||
pci_write_config_word(child, cpos + PCI_EXP_LNKCTL,
|
||||
child_reg[PCI_FUNC(child->devfn)]);
|
||||
}
|
||||
pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list)
|
||||
pcie_capability_write_word(child, PCI_EXP_LNKCTL,
|
||||
child_reg[PCI_FUNC(child->devfn)]);
|
||||
pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
|
||||
}
|
||||
|
||||
/* Convert L0s latency encoding to ns */
|
||||
|
@ -305,16 +292,14 @@ struct aspm_register_info {
|
|||
static void pcie_get_aspm_reg(struct pci_dev *pdev,
|
||||
struct aspm_register_info *info)
|
||||
{
|
||||
int pos;
|
||||
u16 reg16;
|
||||
u32 reg32;
|
||||
|
||||
pos = pci_pcie_cap(pdev);
|
||||
pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32);
|
||||
pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
|
||||
info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
|
||||
info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
|
||||
info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
|
||||
pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
|
||||
info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
|
||||
}
|
||||
|
||||
|
@ -412,7 +397,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
|
|||
* do ASPM for now.
|
||||
*/
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
||||
if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||
if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||
link->aspm_disable = ASPM_STATE_ALL;
|
||||
break;
|
||||
}
|
||||
|
@ -420,17 +405,15 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
|
|||
|
||||
/* Get and check endpoint acceptable latencies */
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
||||
int pos;
|
||||
u32 reg32, encoding;
|
||||
struct aspm_latency *acceptable =
|
||||
&link->acceptable[PCI_FUNC(child->devfn)];
|
||||
|
||||
if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
|
||||
child->pcie_type != PCI_EXP_TYPE_LEG_END)
|
||||
if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
|
||||
pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
|
||||
continue;
|
||||
|
||||
pos = pci_pcie_cap(child);
|
||||
pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
|
||||
pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
|
||||
/* Calculate endpoint L0s acceptable latency */
|
||||
encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
|
||||
acceptable->l0s = calc_l0s_acceptable(encoding);
|
||||
|
@ -444,13 +427,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
|
|||
|
||||
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
|
||||
{
|
||||
u16 reg16;
|
||||
int pos = pci_pcie_cap(pdev);
|
||||
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
|
||||
reg16 &= ~0x3;
|
||||
reg16 |= val;
|
||||
pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
|
||||
pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val);
|
||||
}
|
||||
|
||||
static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
|
||||
|
@ -505,7 +482,6 @@ static void free_link_state(struct pcie_link_state *link)
|
|||
static int pcie_aspm_sanity_check(struct pci_dev *pdev)
|
||||
{
|
||||
struct pci_dev *child;
|
||||
int pos;
|
||||
u32 reg32;
|
||||
|
||||
/*
|
||||
|
@ -513,8 +489,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
|
|||
* very strange. Disable ASPM for the whole slot
|
||||
*/
|
||||
list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
|
||||
pos = pci_pcie_cap(child);
|
||||
if (!pos)
|
||||
if (!pci_is_pcie(child))
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
|
@ -530,7 +505,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
|
|||
* Disable ASPM for pre-1.1 PCIe device, we follow MS to use
|
||||
* RBER bit to determine if a function is 1.1 version device
|
||||
*/
|
||||
pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
|
||||
pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
|
||||
if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
|
||||
dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
|
||||
" on pre-1.1 PCIe device. You can enable it"
|
||||
|
@ -552,7 +527,7 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
|
|||
INIT_LIST_HEAD(&link->children);
|
||||
INIT_LIST_HEAD(&link->link);
|
||||
link->pdev = pdev;
|
||||
if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
|
||||
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
||||
struct pcie_link_state *parent;
|
||||
parent = pdev->bus->parent->self->link_state;
|
||||
if (!parent) {
|
||||
|
@ -585,12 +560,12 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
|
|||
|
||||
if (!pci_is_pcie(pdev) || pdev->link_state)
|
||||
return;
|
||||
if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
|
||||
if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
|
||||
return;
|
||||
|
||||
/* VIA has a strange chipset, root port is under a bridge */
|
||||
if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT &&
|
||||
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pdev->bus->self)
|
||||
return;
|
||||
|
||||
|
@ -647,8 +622,8 @@ static void pcie_update_aspm_capable(struct pcie_link_state *root)
|
|||
if (link->root != root)
|
||||
continue;
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
||||
if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) &&
|
||||
(child->pcie_type != PCI_EXP_TYPE_LEG_END))
|
||||
if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
|
||||
(pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
|
||||
continue;
|
||||
pcie_aspm_check_latency(child);
|
||||
}
|
||||
|
@ -663,8 +638,8 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
|
|||
|
||||
if (!pci_is_pcie(pdev) || !parent || !parent->link_state)
|
||||
return;
|
||||
if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
if ((pci_pcie_type(parent) != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(pci_pcie_type(parent) != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
return;
|
||||
|
||||
down_read(&pci_bus_sem);
|
||||
|
@ -704,8 +679,8 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev)
|
|||
|
||||
if (aspm_disabled || !pci_is_pcie(pdev) || !link)
|
||||
return;
|
||||
if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
return;
|
||||
/*
|
||||
* Devices changed PM state, we should recheck if latency
|
||||
|
@ -729,8 +704,8 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
|
|||
if (aspm_policy != POLICY_POWERSAVE)
|
||||
return;
|
||||
|
||||
if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
return;
|
||||
|
||||
down_read(&pci_bus_sem);
|
||||
|
@ -757,8 +732,8 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem,
|
|||
if (!pci_is_pcie(pdev))
|
||||
return;
|
||||
|
||||
if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
|
||||
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)
|
||||
parent = pdev;
|
||||
if (!parent || !parent->link_state)
|
||||
return;
|
||||
|
@ -933,8 +908,8 @@ void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
|
|||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
if (!pci_is_pcie(pdev) ||
|
||||
(pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
|
||||
(pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
|
||||
return;
|
||||
|
||||
if (link_state->aspm_support)
|
||||
|
@ -950,8 +925,8 @@ void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
|
|||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
if (!pci_is_pcie(pdev) ||
|
||||
(pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
|
||||
(pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
|
||||
return;
|
||||
|
||||
if (link_state->aspm_support)
|
||||
|
|
|
@ -57,17 +57,12 @@ struct pcie_pme_service_data {
|
|||
*/
|
||||
void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
|
||||
{
|
||||
int rtctl_pos;
|
||||
u16 rtctl;
|
||||
|
||||
rtctl_pos = pci_pcie_cap(dev) + PCI_EXP_RTCTL;
|
||||
|
||||
pci_read_config_word(dev, rtctl_pos, &rtctl);
|
||||
if (enable)
|
||||
rtctl |= PCI_EXP_RTCTL_PMEIE;
|
||||
pcie_capability_set_word(dev, PCI_EXP_RTCTL,
|
||||
PCI_EXP_RTCTL_PMEIE);
|
||||
else
|
||||
rtctl &= ~PCI_EXP_RTCTL_PMEIE;
|
||||
pci_write_config_word(dev, rtctl_pos, rtctl);
|
||||
pcie_capability_clear_word(dev, PCI_EXP_RTCTL,
|
||||
PCI_EXP_RTCTL_PMEIE);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -120,7 +115,7 @@ static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
|
|||
if (!dev)
|
||||
return false;
|
||||
|
||||
if (pci_is_pcie(dev) && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||
if (pci_is_pcie(dev) && pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||
down_read(&pci_bus_sem);
|
||||
if (pcie_pme_walk_bus(bus))
|
||||
found = true;
|
||||
|
@ -226,18 +221,15 @@ static void pcie_pme_work_fn(struct work_struct *work)
|
|||
struct pcie_pme_service_data *data =
|
||||
container_of(work, struct pcie_pme_service_data, work);
|
||||
struct pci_dev *port = data->srv->port;
|
||||
int rtsta_pos;
|
||||
u32 rtsta;
|
||||
|
||||
rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
|
||||
|
||||
spin_lock_irq(&data->lock);
|
||||
|
||||
for (;;) {
|
||||
if (data->noirq)
|
||||
break;
|
||||
|
||||
pci_read_config_dword(port, rtsta_pos, &rtsta);
|
||||
pcie_capability_read_dword(port, PCI_EXP_RTSTA, &rtsta);
|
||||
if (rtsta & PCI_EXP_RTSTA_PME) {
|
||||
/*
|
||||
* Clear PME status of the port. If there are other
|
||||
|
@ -276,17 +268,14 @@ static irqreturn_t pcie_pme_irq(int irq, void *context)
|
|||
{
|
||||
struct pci_dev *port;
|
||||
struct pcie_pme_service_data *data;
|
||||
int rtsta_pos;
|
||||
u32 rtsta;
|
||||
unsigned long flags;
|
||||
|
||||
port = ((struct pcie_device *)context)->port;
|
||||
data = get_service_data((struct pcie_device *)context);
|
||||
|
||||
rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
pci_read_config_dword(port, rtsta_pos, &rtsta);
|
||||
pcie_capability_read_dword(port, PCI_EXP_RTSTA, &rtsta);
|
||||
|
||||
if (!(rtsta & PCI_EXP_RTSTA_PME)) {
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
@ -335,13 +324,13 @@ static void pcie_pme_mark_devices(struct pci_dev *port)
|
|||
struct pci_dev *dev;
|
||||
|
||||
/* Check if this is a root port event collector. */
|
||||
if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus)
|
||||
if (pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC || !bus)
|
||||
return;
|
||||
|
||||
down_read(&pci_bus_sem);
|
||||
list_for_each_entry(dev, &bus->devices, bus_list)
|
||||
if (pci_is_pcie(dev)
|
||||
&& dev->pcie_type == PCI_EXP_TYPE_RC_END)
|
||||
&& pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)
|
||||
pcie_pme_set_native(dev, NULL);
|
||||
up_read(&pci_bus_sem);
|
||||
}
|
||||
|
|
|
@ -38,7 +38,7 @@ static int pcie_port_bus_match(struct device *dev, struct device_driver *drv)
|
|||
return 0;
|
||||
|
||||
if ((driver->port_type != PCIE_ANY_PORT) &&
|
||||
(driver->port_type != pciedev->port->pcie_type))
|
||||
(driver->port_type != pci_pcie_type(pciedev->port)))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
|
|
|
@ -246,8 +246,7 @@ static void cleanup_service_irqs(struct pci_dev *dev)
|
|||
*/
|
||||
static int get_port_device_capability(struct pci_dev *dev)
|
||||
{
|
||||
int services = 0, pos;
|
||||
u16 reg16;
|
||||
int services = 0;
|
||||
u32 reg32;
|
||||
int cap_mask = 0;
|
||||
int err;
|
||||
|
@ -265,11 +264,9 @@ static int get_port_device_capability(struct pci_dev *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
|
||||
/* Hot-Plug Capable */
|
||||
if ((cap_mask & PCIE_PORT_SERVICE_HP) && (reg16 & PCI_EXP_FLAGS_SLOT)) {
|
||||
pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, ®32);
|
||||
if (cap_mask & PCIE_PORT_SERVICE_HP) {
|
||||
pcie_capability_read_dword(dev, PCI_EXP_SLTCAP, ®32);
|
||||
if (reg32 & PCI_EXP_SLTCAP_HPC) {
|
||||
services |= PCIE_PORT_SERVICE_HP;
|
||||
/*
|
||||
|
@ -277,10 +274,8 @@ static int get_port_device_capability(struct pci_dev *dev)
|
|||
* enabled by the BIOS and the hot-plug service driver
|
||||
* is not loaded.
|
||||
*/
|
||||
pos += PCI_EXP_SLTCTL;
|
||||
pci_read_config_word(dev, pos, ®16);
|
||||
reg16 &= ~(PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
|
||||
pci_write_config_word(dev, pos, reg16);
|
||||
pcie_capability_clear_word(dev, PCI_EXP_SLTCTL,
|
||||
PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
|
||||
}
|
||||
}
|
||||
/* AER capable */
|
||||
|
@ -298,7 +293,7 @@ static int get_port_device_capability(struct pci_dev *dev)
|
|||
services |= PCIE_PORT_SERVICE_VC;
|
||||
/* Root ports are capable of generating PME too */
|
||||
if ((cap_mask & PCIE_PORT_SERVICE_PME)
|
||||
&& dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
|
||||
&& pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
|
||||
services |= PCIE_PORT_SERVICE_PME;
|
||||
/*
|
||||
* Disable PME interrupt on this port in case it's been enabled
|
||||
|
@ -336,7 +331,7 @@ static int pcie_device_init(struct pci_dev *pdev, int service, int irq)
|
|||
device->release = release_pcie_device; /* callback to free pcie dev */
|
||||
dev_set_name(device, "%s:pcie%02x",
|
||||
pci_name(pdev),
|
||||
get_descriptor_id(pdev->pcie_type, service));
|
||||
get_descriptor_id(pci_pcie_type(pdev), service));
|
||||
device->parent = &pdev->dev;
|
||||
device_enable_async_suspend(device);
|
||||
|
||||
|
|
|
@ -64,14 +64,7 @@ __setup("pcie_ports=", pcie_port_setup);
|
|||
*/
|
||||
void pcie_clear_root_pme_status(struct pci_dev *dev)
|
||||
{
|
||||
int rtsta_pos;
|
||||
u32 rtsta;
|
||||
|
||||
rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
|
||||
|
||||
pci_read_config_dword(dev, rtsta_pos, &rtsta);
|
||||
rtsta |= PCI_EXP_RTSTA_PME;
|
||||
pci_write_config_dword(dev, rtsta_pos, rtsta);
|
||||
pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
|
||||
}
|
||||
|
||||
static int pcie_portdrv_restore_config(struct pci_dev *dev)
|
||||
|
@ -95,7 +88,7 @@ static int pcie_port_resume_noirq(struct device *dev)
|
|||
* which breaks ACPI-based runtime wakeup on PCI Express, so clear those
|
||||
* bits now just in case (shouldn't hurt).
|
||||
*/
|
||||
if(pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
|
||||
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
|
||||
pcie_clear_root_pme_status(pdev);
|
||||
return 0;
|
||||
}
|
||||
|
@ -140,9 +133,17 @@ static int pcie_port_runtime_resume(struct device *dev)
|
|||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pcie_port_runtime_idle(struct device *dev)
|
||||
{
|
||||
/* Delay for a short while to prevent too frequent suspend/resume */
|
||||
pm_schedule_suspend(dev, 10);
|
||||
return -EBUSY;
|
||||
}
|
||||
#else
|
||||
#define pcie_port_runtime_suspend NULL
|
||||
#define pcie_port_runtime_resume NULL
|
||||
#define pcie_port_runtime_idle NULL
|
||||
#endif
|
||||
|
||||
static const struct dev_pm_ops pcie_portdrv_pm_ops = {
|
||||
|
@ -155,6 +156,7 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
|
|||
.resume_noirq = pcie_port_resume_noirq,
|
||||
.runtime_suspend = pcie_port_runtime_suspend,
|
||||
.runtime_resume = pcie_port_runtime_resume,
|
||||
.runtime_idle = pcie_port_runtime_idle,
|
||||
};
|
||||
|
||||
#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
|
||||
|
@ -186,9 +188,9 @@ static int __devinit pcie_portdrv_probe(struct pci_dev *dev,
|
|||
int status;
|
||||
|
||||
if (!pci_is_pcie(dev) ||
|
||||
((dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(dev->pcie_type != PCI_EXP_TYPE_UPSTREAM) &&
|
||||
(dev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)))
|
||||
((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
|
||||
(pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
|
||||
return -ENODEV;
|
||||
|
||||
if (!dev->irq && dev->pin) {
|
||||
|
@ -200,6 +202,11 @@ static int __devinit pcie_portdrv_probe(struct pci_dev *dev,
|
|||
return status;
|
||||
|
||||
pci_save_state(dev);
|
||||
/*
|
||||
* D3cold may not work properly on some PCIe port, so disable
|
||||
* it by default.
|
||||
*/
|
||||
dev->d3cold_allowed = false;
|
||||
if (!pci_match_id(port_runtime_pm_black_list, dev))
|
||||
pm_runtime_put_noidle(&dev->dev);
|
||||
|
||||
|
|
|
@ -144,15 +144,13 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
|
|||
case PCI_BASE_ADDRESS_MEM_TYPE_32:
|
||||
break;
|
||||
case PCI_BASE_ADDRESS_MEM_TYPE_1M:
|
||||
dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
|
||||
/* 1M mem BAR treated as 32-bit BAR */
|
||||
break;
|
||||
case PCI_BASE_ADDRESS_MEM_TYPE_64:
|
||||
flags |= IORESOURCE_MEM_64;
|
||||
break;
|
||||
default:
|
||||
dev_warn(&dev->dev,
|
||||
"mem unknown type %x treated as 32-bit BAR\n",
|
||||
mem_type);
|
||||
/* mem unknown type treated as 32-bit BAR */
|
||||
break;
|
||||
}
|
||||
return flags;
|
||||
|
@ -173,9 +171,11 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
|
|||
u32 l, sz, mask;
|
||||
u16 orig_cmd;
|
||||
struct pci_bus_region region;
|
||||
bool bar_too_big = false, bar_disabled = false;
|
||||
|
||||
mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
|
||||
|
||||
/* No printks while decoding is disabled! */
|
||||
if (!dev->mmio_always_on) {
|
||||
pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
|
||||
pci_write_config_word(dev, PCI_COMMAND,
|
||||
|
@ -240,8 +240,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
|
|||
goto fail;
|
||||
|
||||
if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
|
||||
dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
|
||||
pos);
|
||||
bar_too_big = true;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
|
@ -252,12 +251,11 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
|
|||
region.start = 0;
|
||||
region.end = sz64;
|
||||
pcibios_bus_to_resource(dev, res, ®ion);
|
||||
bar_disabled = true;
|
||||
} else {
|
||||
region.start = l64;
|
||||
region.end = l64 + sz64;
|
||||
pcibios_bus_to_resource(dev, res, ®ion);
|
||||
dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
|
||||
pos, res);
|
||||
}
|
||||
} else {
|
||||
sz = pci_size(l, sz, mask);
|
||||
|
@ -268,18 +266,23 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
|
|||
region.start = l;
|
||||
region.end = l + sz;
|
||||
pcibios_bus_to_resource(dev, res, ®ion);
|
||||
|
||||
dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
|
||||
}
|
||||
|
||||
out:
|
||||
goto out;
|
||||
|
||||
|
||||
fail:
|
||||
res->flags = 0;
|
||||
out:
|
||||
if (!dev->mmio_always_on)
|
||||
pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
|
||||
|
||||
if (bar_too_big)
|
||||
dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", pos);
|
||||
if (res->flags && !bar_disabled)
|
||||
dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
|
||||
|
||||
return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
|
||||
fail:
|
||||
res->flags = 0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
|
||||
|
@ -603,10 +606,10 @@ static void pci_set_bus_speed(struct pci_bus *bus)
|
|||
u32 linkcap;
|
||||
u16 linksta;
|
||||
|
||||
pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
|
||||
pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
|
||||
bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
|
||||
|
||||
pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
|
||||
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
|
||||
pcie_update_link_speed(bus, linksta);
|
||||
}
|
||||
}
|
||||
|
@ -929,24 +932,16 @@ void set_pcie_port_type(struct pci_dev *pdev)
|
|||
pdev->is_pcie = 1;
|
||||
pdev->pcie_cap = pos;
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
|
||||
pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
|
||||
pdev->pcie_flags_reg = reg16;
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
|
||||
pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
|
||||
}
|
||||
|
||||
void set_pcie_hotplug_bridge(struct pci_dev *pdev)
|
||||
{
|
||||
int pos;
|
||||
u16 reg16;
|
||||
u32 reg32;
|
||||
|
||||
pos = pci_pcie_cap(pdev);
|
||||
if (!pos)
|
||||
return;
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
|
||||
if (!(reg16 & PCI_EXP_FLAGS_SLOT))
|
||||
return;
|
||||
pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
|
||||
pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
|
||||
if (reg32 & PCI_EXP_SLTCAP_HPC)
|
||||
pdev->is_hotplug_bridge = 1;
|
||||
}
|
||||
|
@ -1160,8 +1155,7 @@ int pci_cfg_space_size(struct pci_dev *dev)
|
|||
if (class == PCI_CLASS_BRIDGE_HOST)
|
||||
return pci_cfg_space_size_ext(dev);
|
||||
|
||||
pos = pci_pcie_cap(dev);
|
||||
if (!pos) {
|
||||
if (!pci_is_pcie(dev)) {
|
||||
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
||||
if (!pos)
|
||||
goto fail;
|
||||
|
@ -1383,9 +1377,9 @@ static int only_one_child(struct pci_bus *bus)
|
|||
|
||||
if (!parent || !pci_is_pcie(parent))
|
||||
return 0;
|
||||
if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
|
||||
if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
|
||||
return 1;
|
||||
if (parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM &&
|
||||
if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
|
||||
!pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
|
||||
return 1;
|
||||
return 0;
|
||||
|
@ -1462,7 +1456,7 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data)
|
|||
*/
|
||||
if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
|
||||
(dev->bus->self &&
|
||||
dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
|
||||
pci_pcie_type(dev->bus->self) != PCI_EXP_TYPE_ROOT_PORT)))
|
||||
*smpss = 0;
|
||||
|
||||
if (*smpss > dev->pcie_mpss)
|
||||
|
@ -1478,7 +1472,8 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
|
|||
if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
|
||||
mps = 128 << dev->pcie_mpss;
|
||||
|
||||
if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
|
||||
if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
dev->bus->self)
|
||||
/* For "Performance", the assumption is made that
|
||||
* downstream communication will never be larger than
|
||||
* the MRRS. So, the MPS only needs to be configured
|
||||
|
|
|
@ -3081,17 +3081,36 @@ static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
|
|||
|
||||
static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
|
||||
{
|
||||
int pos;
|
||||
int i;
|
||||
u16 status;
|
||||
|
||||
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
||||
if (!pos)
|
||||
return -ENOTTY;
|
||||
/*
|
||||
* http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
|
||||
*
|
||||
* The 82599 supports FLR on VFs, but FLR support is reported only
|
||||
* in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
|
||||
* Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
|
||||
*/
|
||||
|
||||
if (probe)
|
||||
return 0;
|
||||
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_BCR_FLR);
|
||||
/* Wait for Transaction Pending bit clean */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (i)
|
||||
msleep((1 << (i - 1)) * 100);
|
||||
|
||||
pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
|
||||
if (!(status & PCI_EXP_DEVSTA_TRPND))
|
||||
goto clear;
|
||||
}
|
||||
|
||||
dev_err(&dev->dev, "transaction is not cleared; "
|
||||
"proceeding with reset anyway\n");
|
||||
|
||||
clear:
|
||||
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
|
||||
|
||||
msleep(100);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -41,7 +41,7 @@ pci_find_upstream_pcie_bridge(struct pci_dev *pdev)
|
|||
continue;
|
||||
}
|
||||
/* PCI device should connect to a PCIe bridge */
|
||||
if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||
if (pci_pcie_type(pdev) != PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||
/* Busted hardware? */
|
||||
WARN_ON_ONCE(1);
|
||||
return NULL;
|
||||
|
|
|
@ -697,6 +697,38 @@ static resource_size_t calculate_memsize(resource_size_t size,
|
|||
return size;
|
||||
}
|
||||
|
||||
resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
|
||||
unsigned long type)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
|
||||
#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
|
||||
#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
|
||||
|
||||
static resource_size_t window_alignment(struct pci_bus *bus,
|
||||
unsigned long type)
|
||||
{
|
||||
resource_size_t align = 1, arch_align;
|
||||
|
||||
if (type & IORESOURCE_MEM)
|
||||
align = PCI_P2P_DEFAULT_MEM_ALIGN;
|
||||
else if (type & IORESOURCE_IO) {
|
||||
/*
|
||||
* Per spec, I/O windows are 4K-aligned, but some
|
||||
* bridges have an extension to support 1K alignment.
|
||||
*/
|
||||
if (bus->self->io_window_1k)
|
||||
align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
|
||||
else
|
||||
align = PCI_P2P_DEFAULT_IO_ALIGN;
|
||||
}
|
||||
|
||||
arch_align = pcibios_window_alignment(bus, type);
|
||||
return max(align, arch_align);
|
||||
}
|
||||
|
||||
/**
|
||||
* pbus_size_io() - size the io window of a given bus
|
||||
*
|
||||
|
@ -717,17 +749,12 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
|||
struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
|
||||
unsigned long size = 0, size0 = 0, size1 = 0;
|
||||
resource_size_t children_add_size = 0;
|
||||
resource_size_t min_align = 4096, align;
|
||||
resource_size_t min_align, io_align, align;
|
||||
|
||||
if (!b_res)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Per spec, I/O windows are 4K-aligned, but some bridges have an
|
||||
* extension to support 1K alignment.
|
||||
*/
|
||||
if (bus->self->io_window_1k)
|
||||
min_align = 1024;
|
||||
io_align = min_align = window_alignment(bus, IORESOURCE_IO);
|
||||
list_for_each_entry(dev, &bus->devices, bus_list) {
|
||||
int i;
|
||||
|
||||
|
@ -754,8 +781,8 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
|||
}
|
||||
}
|
||||
|
||||
if (min_align > 4096)
|
||||
min_align = 4096;
|
||||
if (min_align > io_align)
|
||||
min_align = io_align;
|
||||
|
||||
size0 = calculate_iosize(size, min_size, size1,
|
||||
resource_size(b_res), min_align);
|
||||
|
@ -785,6 +812,28 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
|||
}
|
||||
}
|
||||
|
||||
static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
|
||||
int max_order)
|
||||
{
|
||||
resource_size_t align = 0;
|
||||
resource_size_t min_align = 0;
|
||||
int order;
|
||||
|
||||
for (order = 0; order <= max_order; order++) {
|
||||
resource_size_t align1 = 1;
|
||||
|
||||
align1 <<= (order + 20);
|
||||
|
||||
if (!align)
|
||||
min_align = align1;
|
||||
else if (ALIGN(align + min_align, min_align) < align1)
|
||||
min_align = align1 >> 1;
|
||||
align += aligns[order];
|
||||
}
|
||||
|
||||
return min_align;
|
||||
}
|
||||
|
||||
/**
|
||||
* pbus_size_mem() - size the memory window of a given bus
|
||||
*
|
||||
|
@ -864,19 +913,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
|||
children_add_size += get_res_add_size(realloc_head, r);
|
||||
}
|
||||
}
|
||||
align = 0;
|
||||
min_align = 0;
|
||||
for (order = 0; order <= max_order; order++) {
|
||||
resource_size_t align1 = 1;
|
||||
|
||||
align1 <<= (order + 20);
|
||||
|
||||
if (!align)
|
||||
min_align = align1;
|
||||
else if (ALIGN(align + min_align, min_align) < align1)
|
||||
min_align = align1 >> 1;
|
||||
align += aligns[order];
|
||||
}
|
||||
min_align = calculate_mem_align(aligns, max_order);
|
||||
min_align = max(min_align, window_alignment(bus, b_res->flags & mask));
|
||||
size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
|
||||
if (children_add_size > add_size)
|
||||
add_size = children_add_size;
|
||||
|
|
|
@ -2219,9 +2219,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
|
|||
const struct pci_device_id *id)
|
||||
{
|
||||
struct tsi721_device *priv;
|
||||
int cap;
|
||||
int err;
|
||||
u32 regval;
|
||||
|
||||
priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL);
|
||||
if (priv == NULL) {
|
||||
|
@ -2330,20 +2328,16 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
|
|||
dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
|
||||
}
|
||||
|
||||
cap = pci_pcie_cap(pdev);
|
||||
BUG_ON(cap == 0);
|
||||
BUG_ON(!pci_is_pcie(pdev));
|
||||
|
||||
/* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */
|
||||
pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, ®val);
|
||||
regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
|
||||
PCI_EXP_DEVCTL_NOSNOOP_EN);
|
||||
regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT;
|
||||
pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval);
|
||||
pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
|
||||
PCI_EXP_DEVCTL_NOSNOOP_EN,
|
||||
0x2 << MAX_READ_REQUEST_SZ_SHIFT);
|
||||
|
||||
/* Adjust PCIe completion timeout. */
|
||||
pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, ®val);
|
||||
regval &= ~(0x0f);
|
||||
pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2);
|
||||
pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2);
|
||||
|
||||
/*
|
||||
* FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
|
||||
|
|
|
@ -58,6 +58,7 @@ struct sam9_rtc {
|
|||
struct rtc_device *rtcdev;
|
||||
u32 imr;
|
||||
void __iomem *gpbr;
|
||||
int irq;
|
||||
};
|
||||
|
||||
#define rtt_readl(rtc, field) \
|
||||
|
@ -292,7 +293,7 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct resource *r, *r_gpbr;
|
||||
struct sam9_rtc *rtc;
|
||||
int ret;
|
||||
int ret, irq;
|
||||
u32 mr;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
@ -302,10 +303,18 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "failed to get interrupt resource\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
rtc = kzalloc(sizeof *rtc, GFP_KERNEL);
|
||||
if (!rtc)
|
||||
return -ENOMEM;
|
||||
|
||||
rtc->irq = irq;
|
||||
|
||||
/* platform setup code should have handled this; sigh */
|
||||
if (!device_can_wakeup(&pdev->dev))
|
||||
device_init_wakeup(&pdev->dev, 1);
|
||||
|
@ -345,11 +354,10 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* register irq handler after we know what name we'll use */
|
||||
ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
|
||||
IRQF_SHARED,
|
||||
ret = request_irq(rtc->irq, at91_rtc_interrupt, IRQF_SHARED,
|
||||
dev_name(&rtc->rtcdev->dev), rtc);
|
||||
if (ret) {
|
||||
dev_dbg(&pdev->dev, "can't share IRQ %d?\n", AT91_ID_SYS);
|
||||
dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
|
||||
rtc_device_unregister(rtc->rtcdev);
|
||||
goto fail_register;
|
||||
}
|
||||
|
@ -386,7 +394,7 @@ static int __devexit at91_rtc_remove(struct platform_device *pdev)
|
|||
|
||||
/* disable all interrupts */
|
||||
rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
|
||||
free_irq(AT91_ID_SYS, rtc);
|
||||
free_irq(rtc->irq, rtc);
|
||||
|
||||
rtc_device_unregister(rtc->rtcdev);
|
||||
|
||||
|
@ -423,7 +431,7 @@ static int at91_rtc_suspend(struct platform_device *pdev,
|
|||
rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
|
||||
if (rtc->imr) {
|
||||
if (device_may_wakeup(&pdev->dev) && (mr & AT91_RTT_ALMIEN)) {
|
||||
enable_irq_wake(AT91_ID_SYS);
|
||||
enable_irq_wake(rtc->irq);
|
||||
/* don't let RTTINC cause wakeups */
|
||||
if (mr & AT91_RTT_RTTINCIEN)
|
||||
rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
|
||||
|
@ -441,7 +449,7 @@ static int at91_rtc_resume(struct platform_device *pdev)
|
|||
|
||||
if (rtc->imr) {
|
||||
if (device_may_wakeup(&pdev->dev))
|
||||
disable_irq_wake(AT91_ID_SYS);
|
||||
disable_irq_wake(rtc->irq);
|
||||
mr = rtt_readl(rtc, MR);
|
||||
rtt_writel(rtc, MR, mr | rtc->imr);
|
||||
}
|
||||
|
|
|
@ -1615,13 +1615,11 @@ qla82xx_get_fw_offs(struct qla_hw_data *ha)
|
|||
char *
|
||||
qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str)
|
||||
{
|
||||
int pcie_reg;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
char lwstr[6];
|
||||
uint16_t lnk;
|
||||
|
||||
pcie_reg = pci_pcie_cap(ha->pdev);
|
||||
pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk);
|
||||
pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
|
||||
ha->link_width = (lnk >> 4) & 0x3f;
|
||||
|
||||
strcpy(str, "PCIe (");
|
||||
|
@ -2497,7 +2495,6 @@ fw_load_failed:
|
|||
int
|
||||
qla82xx_start_firmware(scsi_qla_host_t *vha)
|
||||
{
|
||||
int pcie_cap;
|
||||
uint16_t lnk;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
|
||||
|
@ -2528,8 +2525,7 @@ qla82xx_start_firmware(scsi_qla_host_t *vha)
|
|||
}
|
||||
|
||||
/* Negotiated Link width */
|
||||
pcie_cap = pci_pcie_cap(ha->pdev);
|
||||
pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
|
||||
pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
|
||||
ha->link_width = (lnk >> 4) & 0x3f;
|
||||
|
||||
/* Synchronize with Receive peg */
|
||||
|
|
|
@ -1566,7 +1566,6 @@ qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
|
|||
static int
|
||||
qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
|
||||
{
|
||||
int pcie_cap;
|
||||
uint16_t lnk;
|
||||
|
||||
/* scrub dma mask expansion register */
|
||||
|
@ -1590,8 +1589,7 @@ qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
|
|||
}
|
||||
|
||||
/* Negotiated Link width */
|
||||
pcie_cap = pci_pcie_cap(ha->pdev);
|
||||
pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
|
||||
pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
|
||||
ha->link_width = (lnk >> 4) & 0x3f;
|
||||
|
||||
/* Synchronize with Receive peg */
|
||||
|
|
|
@ -3995,16 +3995,14 @@ static void et131x_hwaddr_init(struct et131x_adapter *adapter)
|
|||
static int et131x_pci_init(struct et131x_adapter *adapter,
|
||||
struct pci_dev *pdev)
|
||||
{
|
||||
int cap = pci_pcie_cap(pdev);
|
||||
u16 max_payload;
|
||||
u16 ctl;
|
||||
int i, rc;
|
||||
|
||||
rc = et131x_init_eeprom(adapter);
|
||||
if (rc < 0)
|
||||
goto out;
|
||||
|
||||
if (!cap) {
|
||||
if (!pci_is_pcie(pdev)) {
|
||||
dev_err(&pdev->dev, "Missing PCIe capabilities\n");
|
||||
goto err_out;
|
||||
}
|
||||
|
@ -4012,7 +4010,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
|
|||
/* Let's set up the PORT LOGIC Register. First we need to know what
|
||||
* the max_payload_size is
|
||||
*/
|
||||
if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCAP, &max_payload)) {
|
||||
if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
|
||||
dev_err(&pdev->dev,
|
||||
"Could not read PCI config space for Max Payload Size\n");
|
||||
goto err_out;
|
||||
|
@ -4049,17 +4047,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
|
|||
}
|
||||
|
||||
/* Change the max read size to 2k */
|
||||
if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl)) {
|
||||
if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
|
||||
PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {
|
||||
dev_err(&pdev->dev,
|
||||
"Could not read PCI config space for Max read size\n");
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | (0x04 << 12);
|
||||
|
||||
if (pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl)) {
|
||||
dev_err(&pdev->dev,
|
||||
"Could not write PCI config space for Max read size\n");
|
||||
"Couldn't change PCI config space for Max read size\n");
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
|
|
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Reference in New Issue