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clk: zte: pd_bit is not 0 on zx296718

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The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field.  The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.

Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This commit is contained in:
Shawn Guo 2017-03-21 16:38:22 +08:00 committed by Michael Turquette
parent 5790d80176
commit ee249cbe42
2 changed files with 16 additions and 2 deletions
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12
drivers/clk/zte/clk.c
View File

@ -52,7 +52,10 @@ static int hw_to_idx(struct clk_zx_pll *zx_pll)
/* For matching the value in lookup table */
hw_cfg0 &= ~BIT(zx_pll->lock_bit);
hw_cfg0 |= BIT(zx_pll->pd_bit);
/* Check availability of pd_bit */
if (zx_pll->pd_bit < 32)
hw_cfg0 |= BIT(zx_pll->pd_bit);
for (i = 0; i < zx_pll->count; i++) {
if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
@ -108,6 +111,10 @@ static int zx_pll_enable(struct clk_hw *hw)
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
u32 reg;
/* If pd_bit is not available, simply return success. */
if (zx_pll->pd_bit > 31)
return 0;
reg = readl_relaxed(zx_pll->reg_base);
writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
@ -120,6 +127,9 @@ static void zx_pll_disable(struct clk_hw *hw)
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
u32 reg;
if (zx_pll->pd_bit > 31)
return;
reg = readl_relaxed(zx_pll->reg_base);
writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
}

6
drivers/clk/zte/clk.h
View File

@ -66,8 +66,12 @@ struct clk_zx_pll {
CLK_GET_RATE_NOCACHE), \
}
/*
* The pd_bit is not available on ZX296718, so let's pass something
* bigger than 31, e.g. 0xff, to indicate that.
*/
#define ZX296718_PLL(_name, _parent, _reg, _table) \
ZX_PLL(_name, _parent, _reg, _table, 0, 30)
ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
struct zx_clk_gate {
struct clk_gate gate;