Merge branch 'pci/misc'
- Remove unused Netronome NFP32xx Device IDs (Jakub Kicinski) - Use bitmap_zalloc() for dma_alias_mask (Andy Shevchenko) - Add switch fall-through annotations (Gustavo A. R. Silva) - Remove unused Switchtec quirk variable (Joshua Abraham) - Fix pci.c kernel-doc warning (Randy Dunlap) - Remove trivial PCI wrappers for DMA APIs (Christoph Hellwig) - Add Intel GPU device IDs to spurious interrupt quirk (Bin Meng) - Run Switchtec DMA aliasing quirk only on NTB endpoints to avoid useless dmesg errors (Logan Gunthorpe) - Update Switchtec NTB documentation (Wesley Yung) - Remove redundant "default n" from Kconfig (Bartlomiej Zolnierkiewicz) * pci/misc: PCI: pcie: Remove redundant 'default n' from Kconfig NTB: switchtec_ntb: Update switchtec documentation with prerequisites for NTB PCI: Fix Switchtec DMA aliasing quirk dmesg noise PCI: Add macro for Switchtec quirk declarations PCI: Add Device IDs for Intel GPU "spurious interrupt" quirk PCI: Remove pci_set_dma_max_seg_size() PCI: Remove pci_set_dma_seg_boundary() PCI: Remove pci_unmap_addr() wrappers for DMA API PCI / ACPI: Mark expected switch fall-through PCI: Remove set but unused variable PCI: Fix pci.c kernel-doc parameter warning PCI: Allocate dma_alias_mask with bitmap_zalloc() PCI: Remove unused NFP32xx IDs
This commit is contained in:
commit
ee8360fdaf
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@ -23,7 +23,7 @@ The primary means of communicating with the Switchtec management firmware is
|
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through the Memory-mapped Remote Procedure Call (MRPC) interface.
|
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Commands are submitted to the interface with a 4-byte command
|
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identifier and up to 1KB of command specific data. The firmware will
|
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respond with a 4 bytes return code and up to 1KB of command specific
|
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respond with a 4-byte return code and up to 1KB of command-specific
|
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data. The interface only processes a single command at a time.
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|
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|
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|
@ -36,8 +36,8 @@ device: /dev/switchtec#, one for each management endpoint in the system.
|
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The char device has the following semantics:
|
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|
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* A write must consist of at least 4 bytes and no more than 1028 bytes.
|
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The first four bytes will be interpreted as the command to run and
|
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the remainder will be used as the input data. A write will send the
|
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The first 4 bytes will be interpreted as the Command ID and the
|
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remainder will be used as the input data. A write will send the
|
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command to the firmware to begin processing.
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|
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* Each write must be followed by exactly one read. Any double write will
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@ -45,9 +45,9 @@ The char device has the following semantics:
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produce an error.
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|
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* A read will block until the firmware completes the command and return
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the four bytes of status plus up to 1024 bytes of output data. (The
|
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length will be specified by the size parameter of the read call --
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reading less than 4 bytes will produce an error.
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the 4-byte Command Return Value plus up to 1024 bytes of output
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data. (The length will be specified by the size parameter of the read
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call -- reading less than 4 bytes will produce an error.)
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* The poll call will also be supported for userspace applications that
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need to do other things while waiting for the command to complete.
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@ -83,10 +83,20 @@ The following IOCTLs are also supported by the device:
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Non-Transparent Bridge (NTB) Driver
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===================================
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An NTB driver is provided for the switchtec hardware in switchtec_ntb.
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Currently, it only supports switches configured with exactly 2
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partitions. It also requires the following configuration settings:
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An NTB hardware driver is provided for the Switchtec hardware in
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ntb_hw_switchtec. Currently, it only supports switches configured with
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exactly 2 NT partitions and zero or more non-NT partitions. It also requires
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the following configuration settings:
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* Both partitions must be able to access each other's GAS spaces.
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* Both NT partitions must be able to access each other's GAS spaces.
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Thus, the bits in the GAS Access Vector under Management Settings
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must be set to support this.
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* Kernel configuration MUST include support for NTB (CONFIG_NTB needs
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to be set)
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NT EP BAR 2 will be dynamically configured as a Direct Window, and
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the configuration file does not need to configure it explicitly.
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Please refer to Documentation/ntb.txt in Linux source tree for an overall
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understanding of the Linux NTB stack. ntb_hw_switchtec works as an NTB
|
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Hardware Driver in this stack.
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|
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@ -873,7 +873,7 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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* like others but it will lock up the whole machine HARD if
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* 65536 byte PRD entry is fed. Reduce maximum segment size.
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*/
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rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
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rc = dma_set_max_seg_size(&pdev->dev, 65536 - 512);
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if (rc) {
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dev_err(&pdev->dev, "failed to set the maximum segment size\n");
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return rc;
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@ -780,7 +780,7 @@ static int rsxx_pci_probe(struct pci_dev *dev,
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goto failed_enable;
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pci_set_master(dev);
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pci_set_dma_max_seg_size(dev, RSXX_HW_BLK_SIZE);
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dma_set_max_seg_size(&dev->dev, RSXX_HW_BLK_SIZE);
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st = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
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if (st) {
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@ -99,7 +99,7 @@ static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
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static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
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{
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dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
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pci_unmap_addr(sq, mapping));
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dma_unmap_addr(sq, mapping));
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}
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static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
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@ -132,7 +132,7 @@ static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
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if (!sq->queue)
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return -ENOMEM;
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sq->phys_addr = virt_to_phys(sq->queue);
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pci_unmap_addr_set(sq, mapping, sq->dma_addr);
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dma_unmap_addr_set(sq, mapping, sq->dma_addr);
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return 0;
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}
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@ -2521,7 +2521,7 @@ static void free_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
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dma_free_coherent(&rdev->lldi.pdev->dev,
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wq->memsize, wq->queue,
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pci_unmap_addr(wq, mapping));
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dma_unmap_addr(wq, mapping));
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c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);
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kfree(wq->sw_rq);
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c4iw_put_qpid(rdev, wq->qid, uctx);
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@ -2570,7 +2570,7 @@ static int alloc_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
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goto err_free_rqtpool;
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memset(wq->queue, 0, wq->memsize);
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pci_unmap_addr_set(wq, mapping, wq->dma_addr);
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dma_unmap_addr_set(wq, mapping, wq->dma_addr);
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wq->bar2_va = c4iw_bar2_addrs(rdev, wq->qid, T4_BAR2_QTYPE_EGRESS,
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&wq->bar2_qid,
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@ -2649,7 +2649,7 @@ static int alloc_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
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err_free_queue:
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dma_free_coherent(&rdev->lldi.pdev->dev,
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wq->memsize, wq->queue,
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pci_unmap_addr(wq, mapping));
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dma_unmap_addr(wq, mapping));
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err_free_rqtpool:
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c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);
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err_free_pending_wrs:
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@ -397,7 +397,7 @@ struct t4_srq_pending_wr {
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struct t4_srq {
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union t4_recv_wr *queue;
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dma_addr_t dma_addr;
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DECLARE_PCI_UNMAP_ADDR(mapping);
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DEFINE_DMA_UNMAP_ADDR(mapping);
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struct t4_swrqe *sw_rq;
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void __iomem *bar2_va;
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u64 bar2_pa;
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@ -588,6 +588,7 @@ static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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error = -EBUSY;
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break;
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}
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/* Fall through */
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case PCI_D0:
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case PCI_D1:
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case PCI_D2:
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@ -198,7 +198,7 @@ EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
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/**
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* pci_dev_str_match_path - test if a path string matches a device
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* @dev: the PCI device to test
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* @p: string to match the device against
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* @path: string to match the device against
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* @endptr: pointer to the string after the match
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*
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* Test if a string (typically from a kernel parameter) formatted as a
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@ -5773,8 +5773,7 @@ int pci_set_vga_state(struct pci_dev *dev, bool decode,
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void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
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{
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if (!dev->dma_alias_mask)
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dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
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sizeof(long), GFP_KERNEL);
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dev->dma_alias_mask = bitmap_zalloc(U8_MAX, GFP_KERNEL);
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if (!dev->dma_alias_mask) {
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pci_warn(dev, "Unable to allocate DMA alias mask\n");
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return;
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@ -36,7 +36,6 @@ config PCIEAER
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config PCIEAER_INJECT
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tristate "PCI Express error injection support"
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depends on PCIEAER
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default n
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help
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This enables PCI Express Root Port Advanced Error Reporting
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(AER) software error injector.
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@ -84,7 +83,6 @@ config PCIEASPM
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config PCIEASPM_DEBUG
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bool "Debug PCI Express ASPM"
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depends on PCIEASPM
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default n
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help
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This enables PCI Express ASPM debug support. It will add per-device
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interface to control ASPM.
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@ -129,7 +127,6 @@ config PCIE_PME
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config PCIE_DPC
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bool "PCI Express Downstream Port Containment support"
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depends on PCIEPORTBUS && PCIEAER
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default n
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help
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This enables PCI Express Downstream Port Containment (DPC)
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driver support. DPC events from Root and Downstream ports
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@ -139,7 +136,6 @@ config PCIE_DPC
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config PCIE_PTM
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bool "PCI Express Precision Time Measurement support"
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default n
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depends on PCIEPORTBUS
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help
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This enables PCI Express Precision Time Measurement (PTM)
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|
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@ -2144,7 +2144,7 @@ static void pci_release_dev(struct device *dev)
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pcibios_release_device(pci_dev);
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pci_bus_put(pci_dev->bus);
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kfree(pci_dev->driver_override);
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kfree(pci_dev->dma_alias_mask);
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bitmap_free(pci_dev->dma_alias_mask);
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kfree(pci_dev);
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}
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@ -2398,8 +2398,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
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dev->dev.dma_parms = &dev->dma_parms;
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dev->dev.coherent_dma_mask = 0xffffffffull;
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pci_set_dma_max_seg_size(dev, 65536);
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pci_set_dma_seg_boundary(dev, 0xffffffff);
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dma_set_max_seg_size(&dev->dev, 65536);
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dma_set_seg_boundary(&dev->dev, 0xffffffff);
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/* Fix up broken headers */
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pci_fixup_device(pci_fixup_header, dev);
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|
|
|
@ -3190,7 +3190,11 @@ static void disable_igfx_irq(struct pci_dev *dev)
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|||
|
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pci_iounmap(dev, regs);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
|
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|
||||
|
@ -4987,7 +4991,6 @@ static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
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|||
void __iomem *mmio;
|
||||
struct ntb_info_regs __iomem *mmio_ntb;
|
||||
struct ntb_ctrl_regs __iomem *mmio_ctrl;
|
||||
struct sys_info_regs __iomem *mmio_sys_info;
|
||||
u64 partition_map;
|
||||
u8 partition;
|
||||
int pp;
|
||||
|
@ -5008,7 +5011,6 @@ static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
|
|||
|
||||
mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
|
||||
mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
|
||||
mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
|
||||
|
||||
partition = ioread8(&mmio_ntb->partition_id);
|
||||
|
||||
|
@ -5057,59 +5059,37 @@ static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
|
|||
pci_iounmap(pdev, mmio);
|
||||
pci_disable_device(pdev);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8531,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8532,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8533,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8534,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8535,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8536,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8543,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8544,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8545,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8546,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8551,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8552,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8553,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8554,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8555,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8556,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8561,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8562,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8563,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8564,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8565,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8566,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8571,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8572,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8573,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8574,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8575,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8576,
|
||||
quirk_switchtec_ntb_dma_alias);
|
||||
#define SWITCHTEC_QUIRK(vid) \
|
||||
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
|
||||
PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
|
||||
|
||||
SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
|
||||
SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
|
||||
SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
|
||||
SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
|
||||
SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
|
||||
SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
|
||||
SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
|
||||
SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
|
||||
SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
|
||||
SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
|
||||
SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
|
||||
SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
|
||||
SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
|
||||
SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
|
||||
SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
|
||||
SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
|
||||
SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
|
||||
SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
|
||||
SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
|
||||
SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
|
||||
SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
|
||||
SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
|
||||
SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
|
||||
SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
|
||||
SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
|
||||
SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
|
||||
SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
|
||||
SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
|
||||
SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
|
||||
SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
|
||||
|
|
|
@ -515,8 +515,8 @@ static int ism_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
if (ret)
|
||||
goto err_unmap;
|
||||
|
||||
pci_set_dma_seg_boundary(pdev, SZ_1M - 1);
|
||||
pci_set_dma_max_seg_size(pdev, SZ_1M);
|
||||
dma_set_seg_boundary(&pdev->dev, SZ_1M - 1);
|
||||
dma_set_max_seg_size(&pdev->dev, SZ_1M);
|
||||
pci_set_master(pdev);
|
||||
|
||||
ism->smcd = smcd_alloc_dev(&pdev->dev, dev_name(&pdev->dev), &ism_ops,
|
||||
|
|
|
@ -1747,7 +1747,7 @@ static int aac_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
shost->max_sectors = (shost->sg_tablesize * 8) + 112;
|
||||
}
|
||||
|
||||
error = pci_set_dma_max_seg_size(pdev,
|
||||
error = dma_set_max_seg_size(&pdev->dev,
|
||||
(aac->adapter_info.options & AAC_OPT_NEW_COMM) ?
|
||||
(shost->max_sectors << 9) : 65536);
|
||||
if (error)
|
||||
|
|
|
@ -119,29 +119,11 @@ static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
|
|||
{
|
||||
return dma_set_coherent_mask(&dev->dev, mask);
|
||||
}
|
||||
|
||||
static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
|
||||
unsigned int size)
|
||||
{
|
||||
return dma_set_max_seg_size(&dev->dev, size);
|
||||
}
|
||||
|
||||
static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
|
||||
unsigned long mask)
|
||||
{
|
||||
return dma_set_seg_boundary(&dev->dev, mask);
|
||||
}
|
||||
#else
|
||||
static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
|
||||
{ return -EIO; }
|
||||
static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
|
||||
{ return -EIO; }
|
||||
static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
|
||||
unsigned int size)
|
||||
{ return -EIO; }
|
||||
static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
|
||||
unsigned long mask)
|
||||
{ return -EIO; }
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
@ -1,12 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _LINUX_PCI_DMA_H
|
||||
#define _LINUX_PCI_DMA_H
|
||||
|
||||
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) DEFINE_DMA_UNMAP_ADDR(ADDR_NAME);
|
||||
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) DEFINE_DMA_UNMAP_LEN(LEN_NAME);
|
||||
#define pci_unmap_addr dma_unmap_addr
|
||||
#define pci_unmap_addr_set dma_unmap_addr_set
|
||||
#define pci_unmap_len dma_unmap_len
|
||||
#define pci_unmap_len_set dma_unmap_len_set
|
||||
|
||||
#endif
|
|
@ -1344,7 +1344,6 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode,
|
|||
|
||||
/* kmem_cache style wrapper around pci_alloc_consistent() */
|
||||
|
||||
#include <linux/pci-dma.h>
|
||||
#include <linux/dmapool.h>
|
||||
|
||||
#define pci_pool dma_pool
|
||||
|
|
|
@ -2539,8 +2539,6 @@
|
|||
#define PCI_VENDOR_ID_HUAWEI 0x19e5
|
||||
|
||||
#define PCI_VENDOR_ID_NETRONOME 0x19ee
|
||||
#define PCI_DEVICE_ID_NETRONOME_NFP3200 0x3200
|
||||
#define PCI_DEVICE_ID_NETRONOME_NFP3240 0x3240
|
||||
#define PCI_DEVICE_ID_NETRONOME_NFP4000 0x4000
|
||||
#define PCI_DEVICE_ID_NETRONOME_NFP5000 0x5000
|
||||
#define PCI_DEVICE_ID_NETRONOME_NFP6000 0x6000
|
||||
|
|
Loading…
Reference in New Issue