drivers/video/mmp: remove legacy hw definitions
Removed legacy hw definitions in hw/mmp_ctrl.h. These definitions are for earlier soc versions and are not supported in this driver. Signed-off-by: Zhou Zhu <zzhu3@marvell.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Lisa Du <cldu@marvell.com> Cc: Guoqing Li <ligq@marvell.com> Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Zhou Zhu
Linus Torvalds
parent
bb5254d2f3
commit
ee8ad7261c
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@ -961,56 +961,7 @@ struct lcd_regs {
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LCD_TVG_CUTVLN : PN2_LCD_GRA_CUTVLN) : LCD_GRA_CUTVLN)
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/*
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* defined Video Memory Color format for DMA control 0 register
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* DMA0 bit[23:20]
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*/
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#define VMODE_RGB565 0x0
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#define VMODE_RGB1555 0x1
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#define VMODE_RGB888PACKED 0x2
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#define VMODE_RGB888UNPACKED 0x3
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#define VMODE_RGBA888 0x4
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#define VMODE_YUV422PACKED 0x5
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#define VMODE_YUV422PLANAR 0x6
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#define VMODE_YUV420PLANAR 0x7
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#define VMODE_SMPNCMD 0x8
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#define VMODE_PALETTE4BIT 0x9
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#define VMODE_PALETTE8BIT 0xa
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#define VMODE_RESERVED 0xb
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/*
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* defined Graphic Memory Color format for DMA control 0 register
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* DMA0 bit[19:16]
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*/
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#define GMODE_RGB565 0x0
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#define GMODE_RGB1555 0x1
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#define GMODE_RGB888PACKED 0x2
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#define GMODE_RGB888UNPACKED 0x3
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#define GMODE_RGBA888 0x4
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#define GMODE_YUV422PACKED 0x5
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#define GMODE_YUV422PLANAR 0x6
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#define GMODE_YUV420PLANAR 0x7
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#define GMODE_SMPNCMD 0x8
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#define GMODE_PALETTE4BIT 0x9
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#define GMODE_PALETTE8BIT 0xa
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#define GMODE_RESERVED 0xb
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/*
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* define for DMA control 1 register
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*/
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#define DMA1_FRAME_TRIG 31 /* bit location */
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#define DMA1_VSYNC_MODE 28
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#define DMA1_VSYNC_INV 27
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#define DMA1_CKEY 24
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#define DMA1_CARRY 23
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#define DMA1_LNBUF_ENA 22
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#define DMA1_GATED_ENA 21
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#define DMA1_PWRDN_ENA 20
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#define DMA1_DSCALE 18
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#define DMA1_ALPHA_MODE 16
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#define DMA1_ALPHA 08
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#define DMA1_PXLCMD 00
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/*
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* defined for Configure Dumb Mode
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* defined for Configure Dumb Mode
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* DUMB LCD Panel bit[31:28]
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*/
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@ -1050,18 +1001,6 @@ struct lcd_regs {
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#define CFG_CYC_BURST_LEN16 (1<<4)
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#define CFG_CYC_BURST_LEN8 (0<<4)
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/*
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* defined Dumb Panel Clock Divider register
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* SCLK_Source bit[31]
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*/
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/* 0: PLL clock select*/
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#define AXI_BUS_SEL 0x80000000
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#define CCD_CLK_SEL 0x40000000
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#define DCON_CLK_SEL 0x20000000
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#define ENA_CLK_INT_DIV CONFIG_FB_DOVE_CLCD_SCLK_DIV
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#define IDLE_CLK_INT_DIV 0x1 /* idle Integer Divider */
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#define DIS_CLK_INT_DIV 0x0 /* Disable Integer Divider */
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/* SRAM ID */
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#define SRAMID_GAMMA_YR 0x0
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#define SRAMID_GAMMA_UG 0x1
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@ -1471,422 +1410,6 @@ struct dsi_regs {
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#define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT (0x1 << 1)
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#define LVDS_FREQ_OFFSET_MODE_EN (0x1 << 0)
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/* VDMA */
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struct vdma_ch_regs {
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#define VDMA_DC_SADDR_1 0x320
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#define VDMA_DC_SADDR_2 0x3A0
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#define VDMA_DC_SZ_1 0x324
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#define VDMA_DC_SZ_2 0x3A4
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#define VDMA_CTRL_1 0x328
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#define VDMA_CTRL_2 0x3A8
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#define VDMA_SRC_SZ_1 0x32C
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#define VDMA_SRC_SZ_2 0x3AC
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#define VDMA_SA_1 0x330
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#define VDMA_SA_2 0x3B0
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#define VDMA_DA_1 0x334
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#define VDMA_DA_2 0x3B4
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#define VDMA_SZ_1 0x338
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#define VDMA_SZ_2 0x3B8
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u32 dc_saddr;
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u32 dc_size;
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u32 ctrl;
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u32 src_size;
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u32 src_addr;
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u32 dst_addr;
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u32 dst_size;
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#define VDMA_PITCH_1 0x33C
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#define VDMA_PITCH_2 0x3BC
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#define VDMA_ROT_CTRL_1 0x340
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#define VDMA_ROT_CTRL_2 0x3C0
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#define VDMA_RAM_CTRL0_1 0x344
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#define VDMA_RAM_CTRL0_2 0x3C4
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#define VDMA_RAM_CTRL1_1 0x348
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#define VDMA_RAM_CTRL1_2 0x3C8
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u32 pitch;
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u32 rot_ctrl;
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u32 ram_ctrl0;
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u32 ram_ctrl1;
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};
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struct vdma_regs {
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#define VDMA_ARBR_CTRL 0x300
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#define VDMA_IRQR 0x304
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#define VDMA_IRQM 0x308
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#define VDMA_IRQS 0x30C
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#define VDMA_MDMA_ARBR_CTRL 0x310
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u32 arbr_ctr;
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u32 irq_raw;
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u32 irq_mask;
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u32 irq_status;
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u32 mdma_arbr_ctrl;
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u32 reserved[3];
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struct vdma_ch_regs ch1;
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u32 reserved2[21];
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struct vdma_ch_regs ch2;
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};
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/* CMU */
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#define CMU_PIP_DE_H_CFG 0x0008
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#define CMU_PRI1_H_CFG 0x000C
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#define CMU_PRI2_H_CFG 0x0010
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#define CMU_ACE_MAIN_DE1_H_CFG 0x0014
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#define CMU_ACE_MAIN_DE2_H_CFG 0x0018
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#define CMU_ACE_PIP_DE1_H_CFG 0x001C
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#define CMU_ACE_PIP_DE2_H_CFG 0x0020
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#define CMU_PIP_DE_V_CFG 0x0024
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#define CMU_PRI_V_CFG 0x0028
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#define CMU_ACE_MAIN_DE_V_CFG 0x002C
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#define CMU_ACE_PIP_DE_V_CFG 0x0030
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#define CMU_BAR_0_CFG 0x0034
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#define CMU_BAR_1_CFG 0x0038
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#define CMU_BAR_2_CFG 0x003C
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#define CMU_BAR_3_CFG 0x0040
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#define CMU_BAR_4_CFG 0x0044
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#define CMU_BAR_5_CFG 0x0048
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#define CMU_BAR_6_CFG 0x004C
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#define CMU_BAR_7_CFG 0x0050
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#define CMU_BAR_8_CFG 0x0054
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#define CMU_BAR_9_CFG 0x0058
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#define CMU_BAR_10_CFG 0x005C
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#define CMU_BAR_11_CFG 0x0060
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#define CMU_BAR_12_CFG 0x0064
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#define CMU_BAR_13_CFG 0x0068
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#define CMU_BAR_14_CFG 0x006C
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#define CMU_BAR_15_CFG 0x0070
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#define CMU_BAR_CTRL 0x0074
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#define PATTERN_TOTAL 0x0078
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#define PATTERN_ACTIVE 0x007C
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#define PATTERN_FRONT_PORCH 0x0080
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#define PATTERN_BACK_PORCH 0x0084
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#define CMU_CLK_CTRL 0x0088
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#define CMU_ICSC_M_C0_L 0x0900
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#define CMU_ICSC_M_C0_H 0x0901
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#define CMU_ICSC_M_C1_L 0x0902
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#define CMU_ICSC_M_C1_H 0x0903
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#define CMU_ICSC_M_C2_L 0x0904
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#define CMU_ICSC_M_C2_H 0x0905
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#define CMU_ICSC_M_C3_L 0x0906
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#define CMU_ICSC_M_C3_H 0x0907
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#define CMU_ICSC_M_C4_L 0x0908
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#define CMU_ICSC_M_C4_H 0x0909
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#define CMU_ICSC_M_C5_L 0x090A
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#define CMU_ICSC_M_C5_H 0x090B
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#define CMU_ICSC_M_C6_L 0x090C
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#define CMU_ICSC_M_C6_H 0x090D
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#define CMU_ICSC_M_C7_L 0x090E
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#define CMU_ICSC_M_C7_H 0x090F
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#define CMU_ICSC_M_C8_L 0x0910
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#define CMU_ICSC_M_C8_H 0x0911
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#define CMU_ICSC_M_O1_0 0x0914
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#define CMU_ICSC_M_O1_1 0x0915
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#define CMU_ICSC_M_O1_2 0x0916
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#define CMU_ICSC_M_O2_0 0x0918
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#define CMU_ICSC_M_O2_1 0x0919
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#define CMU_ICSC_M_O2_2 0x091A
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#define CMU_ICSC_M_O3_0 0x091C
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#define CMU_ICSC_M_O3_1 0x091D
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#define CMU_ICSC_M_O3_2 0x091E
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#define CMU_ICSC_P_C0_L 0x0920
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#define CMU_ICSC_P_C0_H 0x0921
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#define CMU_ICSC_P_C1_L 0x0922
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#define CMU_ICSC_P_C1_H 0x0923
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#define CMU_ICSC_P_C2_L 0x0924
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#define CMU_ICSC_P_C2_H 0x0925
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#define CMU_ICSC_P_C3_L 0x0926
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#define CMU_ICSC_P_C3_H 0x0927
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#define CMU_ICSC_P_C4_L 0x0928
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#define CMU_ICSC_P_C4_H 0x0929
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#define CMU_ICSC_P_C5_L 0x092A
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#define CMU_ICSC_P_C5_H 0x092B
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#define CMU_ICSC_P_C6_L 0x092C
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#define CMU_ICSC_P_C6_H 0x092D
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#define CMU_ICSC_P_C7_L 0x092E
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#define CMU_ICSC_P_C7_H 0x092F
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#define CMU_ICSC_P_C8_L 0x0930
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#define CMU_ICSC_P_C8_H 0x0931
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#define CMU_ICSC_P_O1_0 0x0934
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#define CMU_ICSC_P_O1_1 0x0935
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#define CMU_ICSC_P_O1_2 0x0936
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#define CMU_ICSC_P_O2_0 0x0938
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#define CMU_ICSC_P_O2_1 0x0939
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#define CMU_ICSC_P_O2_2 0x093A
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#define CMU_ICSC_P_O3_0 0x093C
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#define CMU_ICSC_P_O3_1 0x093D
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#define CMU_ICSC_P_O3_2 0x093E
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#define CMU_BR_M_EN 0x0940
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#define CMU_BR_M_TH1_L 0x0942
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#define CMU_BR_M_TH1_H 0x0943
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#define CMU_BR_M_TH2_L 0x0944
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#define CMU_BR_M_TH2_H 0x0945
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#define CMU_ACE_M_EN 0x0950
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#define CMU_ACE_M_WFG1 0x0951
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#define CMU_ACE_M_WFG2 0x0952
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#define CMU_ACE_M_WFG3 0x0953
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#define CMU_ACE_M_TH0 0x0954
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#define CMU_ACE_M_TH1 0x0955
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#define CMU_ACE_M_TH2 0x0956
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#define CMU_ACE_M_TH3 0x0957
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#define CMU_ACE_M_TH4 0x0958
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#define CMU_ACE_M_TH5 0x0959
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#define CMU_ACE_M_OP0_L 0x095A
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#define CMU_ACE_M_OP0_H 0x095B
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#define CMU_ACE_M_OP5_L 0x095C
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#define CMU_ACE_M_OP5_H 0x095D
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#define CMU_ACE_M_GB2 0x095E
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#define CMU_ACE_M_GB3 0x095F
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#define CMU_ACE_M_MS1 0x0960
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#define CMU_ACE_M_MS2 0x0961
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#define CMU_ACE_M_MS3 0x0962
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#define CMU_BR_P_EN 0x0970
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#define CMU_BR_P_TH1_L 0x0972
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#define CMU_BR_P_TH1_H 0x0973
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#define CMU_BR_P_TH2_L 0x0974
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#define CMU_BR_P_TH2_H 0x0975
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#define CMU_ACE_P_EN 0x0980
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#define CMU_ACE_P_WFG1 0x0981
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#define CMU_ACE_P_WFG2 0x0982
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#define CMU_ACE_P_WFG3 0x0983
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#define CMU_ACE_P_TH0 0x0984
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#define CMU_ACE_P_TH1 0x0985
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#define CMU_ACE_P_TH2 0x0986
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#define CMU_ACE_P_TH3 0x0987
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#define CMU_ACE_P_TH4 0x0988
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#define CMU_ACE_P_TH5 0x0989
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#define CMU_ACE_P_OP0_L 0x098A
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#define CMU_ACE_P_OP0_H 0x098B
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#define CMU_ACE_P_OP5_L 0x098C
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#define CMU_ACE_P_OP5_H 0x098D
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#define CMU_ACE_P_GB2 0x098E
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#define CMU_ACE_P_GB3 0x098F
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#define CMU_ACE_P_MS1 0x0990
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#define CMU_ACE_P_MS2 0x0991
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#define CMU_ACE_P_MS3 0x0992
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#define CMU_FTDC_M_EN 0x09A0
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#define CMU_FTDC_P_EN 0x09A1
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#define CMU_FTDC_INLOW_L 0x09A2
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#define CMU_FTDC_INLOW_H 0x09A3
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#define CMU_FTDC_INHIGH_L 0x09A4
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#define CMU_FTDC_INHIGH_H 0x09A5
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#define CMU_FTDC_OUTLOW_L 0x09A6
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#define CMU_FTDC_OUTLOW_H 0x09A7
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#define CMU_FTDC_OUTHIGH_L 0x09A8
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#define CMU_FTDC_OUTHIGH_H 0x09A9
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#define CMU_FTDC_YLOW 0x09AA
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#define CMU_FTDC_YHIGH 0x09AB
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#define CMU_FTDC_CH1 0x09AC
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#define CMU_FTDC_CH2_L 0x09AE
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#define CMU_FTDC_CH2_H 0x09AF
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#define CMU_FTDC_CH3_L 0x09B0
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#define CMU_FTDC_CH3_H 0x09B1
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#define CMU_FTDC_1_C00_6 0x09B2
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#define CMU_FTDC_1_C01_6 0x09B8
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#define CMU_FTDC_1_C11_6 0x09BE
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#define CMU_FTDC_1_C10_6 0x09C4
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#define CMU_FTDC_1_OFF00_6 0x09CA
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#define CMU_FTDC_1_OFF10_6 0x09D0
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#define CMU_HS_M_EN 0x0A00
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#define CMU_HS_M_AX1_L 0x0A02
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#define CMU_HS_M_AX1_H 0x0A03
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#define CMU_HS_M_AX2_L 0x0A04
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#define CMU_HS_M_AX2_H 0x0A05
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#define CMU_HS_M_AX3_L 0x0A06
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#define CMU_HS_M_AX3_H 0x0A07
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#define CMU_HS_M_AX4_L 0x0A08
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#define CMU_HS_M_AX4_H 0x0A09
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#define CMU_HS_M_AX5_L 0x0A0A
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#define CMU_HS_M_AX5_H 0x0A0B
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#define CMU_HS_M_AX6_L 0x0A0C
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#define CMU_HS_M_AX6_H 0x0A0D
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#define CMU_HS_M_AX7_L 0x0A0E
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#define CMU_HS_M_AX7_H 0x0A0F
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#define CMU_HS_M_AX8_L 0x0A10
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#define CMU_HS_M_AX8_H 0x0A11
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#define CMU_HS_M_AX9_L 0x0A12
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#define CMU_HS_M_AX9_H 0x0A13
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#define CMU_HS_M_AX10_L 0x0A14
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#define CMU_HS_M_AX10_H 0x0A15
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#define CMU_HS_M_AX11_L 0x0A16
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#define CMU_HS_M_AX11_H 0x0A17
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#define CMU_HS_M_AX12_L 0x0A18
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#define CMU_HS_M_AX12_H 0x0A19
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#define CMU_HS_M_AX13_L 0x0A1A
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#define CMU_HS_M_AX13_H 0x0A1B
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#define CMU_HS_M_AX14_L 0x0A1C
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#define CMU_HS_M_AX14_H 0x0A1D
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#define CMU_HS_M_H1_H14 0x0A1E
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#define CMU_HS_M_S1_S14 0x0A2C
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#define CMU_HS_M_GL 0x0A3A
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#define CMU_HS_M_MAXSAT_RGB_Y_L 0x0A3C
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#define CMU_HS_M_MAXSAT_RGB_Y_H 0x0A3D
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#define CMU_HS_M_MAXSAT_RCR_L 0x0A3E
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#define CMU_HS_M_MAXSAT_RCR_H 0x0A3F
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#define CMU_HS_M_MAXSAT_RCB_L 0x0A40
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#define CMU_HS_M_MAXSAT_RCB_H 0x0A41
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#define CMU_HS_M_MAXSAT_GCR_L 0x0A42
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#define CMU_HS_M_MAXSAT_GCR_H 0x0A43
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#define CMU_HS_M_MAXSAT_GCB_L 0x0A44
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#define CMU_HS_M_MAXSAT_GCB_H 0x0A45
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#define CMU_HS_M_MAXSAT_BCR_L 0x0A46
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#define CMU_HS_M_MAXSAT_BCR_H 0x0A47
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#define CMU_HS_M_MAXSAT_BCB_L 0x0A48
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#define CMU_HS_M_MAXSAT_BCB_H 0x0A49
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#define CMU_HS_M_ROFF_L 0x0A4A
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#define CMU_HS_M_ROFF_H 0x0A4B
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#define CMU_HS_M_GOFF_L 0x0A4C
|
||||
#define CMU_HS_M_GOFF_H 0x0A4D
|
||||
#define CMU_HS_M_BOFF_L 0x0A4E
|
||||
#define CMU_HS_M_BOFF_H 0x0A4F
|
||||
#define CMU_HS_P_EN 0x0A50
|
||||
#define CMU_HS_P_AX1_L 0x0A52
|
||||
#define CMU_HS_P_AX1_H 0x0A53
|
||||
#define CMU_HS_P_AX2_L 0x0A54
|
||||
#define CMU_HS_P_AX2_H 0x0A55
|
||||
#define CMU_HS_P_AX3_L 0x0A56
|
||||
#define CMU_HS_P_AX3_H 0x0A57
|
||||
#define CMU_HS_P_AX4_L 0x0A58
|
||||
#define CMU_HS_P_AX4_H 0x0A59
|
||||
#define CMU_HS_P_AX5_L 0x0A5A
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||||
#define CMU_HS_P_AX5_H 0x0A5B
|
||||
#define CMU_HS_P_AX6_L 0x0A5C
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||||
#define CMU_HS_P_AX6_H 0x0A5D
|
||||
#define CMU_HS_P_AX7_L 0x0A5E
|
||||
#define CMU_HS_P_AX7_H 0x0A5F
|
||||
#define CMU_HS_P_AX8_L 0x0A60
|
||||
#define CMU_HS_P_AX8_H 0x0A61
|
||||
#define CMU_HS_P_AX9_L 0x0A62
|
||||
#define CMU_HS_P_AX9_H 0x0A63
|
||||
#define CMU_HS_P_AX10_L 0x0A64
|
||||
#define CMU_HS_P_AX10_H 0x0A65
|
||||
#define CMU_HS_P_AX11_L 0x0A66
|
||||
#define CMU_HS_P_AX11_H 0x0A67
|
||||
#define CMU_HS_P_AX12_L 0x0A68
|
||||
#define CMU_HS_P_AX12_H 0x0A69
|
||||
#define CMU_HS_P_AX13_L 0x0A6A
|
||||
#define CMU_HS_P_AX13_H 0x0A6B
|
||||
#define CMU_HS_P_AX14_L 0x0A6C
|
||||
#define CMU_HS_P_AX14_H 0x0A6D
|
||||
#define CMU_HS_P_H1_H14 0x0A6E
|
||||
#define CMU_HS_P_S1_S14 0x0A7C
|
||||
#define CMU_HS_P_GL 0x0A8A
|
||||
#define CMU_HS_P_MAXSAT_RGB_Y_L 0x0A8C
|
||||
#define CMU_HS_P_MAXSAT_RGB_Y_H 0x0A8D
|
||||
#define CMU_HS_P_MAXSAT_RCR_L 0x0A8E
|
||||
#define CMU_HS_P_MAXSAT_RCR_H 0x0A8F
|
||||
#define CMU_HS_P_MAXSAT_RCB_L 0x0A90
|
||||
#define CMU_HS_P_MAXSAT_RCB_H 0x0A91
|
||||
#define CMU_HS_P_MAXSAT_GCR_L 0x0A92
|
||||
#define CMU_HS_P_MAXSAT_GCR_H 0x0A93
|
||||
#define CMU_HS_P_MAXSAT_GCB_L 0x0A94
|
||||
#define CMU_HS_P_MAXSAT_GCB_H 0x0A95
|
||||
#define CMU_HS_P_MAXSAT_BCR_L 0x0A96
|
||||
#define CMU_HS_P_MAXSAT_BCR_H 0x0A97
|
||||
#define CMU_HS_P_MAXSAT_BCB_L 0x0A98
|
||||
#define CMU_HS_P_MAXSAT_BCB_H 0x0A99
|
||||
#define CMU_HS_P_ROFF_L 0x0A9A
|
||||
#define CMU_HS_P_ROFF_H 0x0A9B
|
||||
#define CMU_HS_P_GOFF_L 0x0A9C
|
||||
#define CMU_HS_P_GOFF_H 0x0A9D
|
||||
#define CMU_HS_P_BOFF_L 0x0A9E
|
||||
#define CMU_HS_P_BOFF_H 0x0A9F
|
||||
#define CMU_GLCSC_M_C0_L 0x0AA0
|
||||
#define CMU_GLCSC_M_C0_H 0x0AA1
|
||||
#define CMU_GLCSC_M_C1_L 0x0AA2
|
||||
#define CMU_GLCSC_M_C1_H 0x0AA3
|
||||
#define CMU_GLCSC_M_C2_L 0x0AA4
|
||||
#define CMU_GLCSC_M_C2_H 0x0AA5
|
||||
#define CMU_GLCSC_M_C3_L 0x0AA6
|
||||
#define CMU_GLCSC_M_C3_H 0x0AA7
|
||||
#define CMU_GLCSC_M_C4_L 0x0AA8
|
||||
#define CMU_GLCSC_M_C4_H 0x0AA9
|
||||
#define CMU_GLCSC_M_C5_L 0x0AAA
|
||||
#define CMU_GLCSC_M_C5_H 0x0AAB
|
||||
#define CMU_GLCSC_M_C6_L 0x0AAC
|
||||
#define CMU_GLCSC_M_C6_H 0x0AAD
|
||||
#define CMU_GLCSC_M_C7_L 0x0AAE
|
||||
#define CMU_GLCSC_M_C7_H 0x0AAF
|
||||
#define CMU_GLCSC_M_C8_L 0x0AB0
|
||||
#define CMU_GLCSC_M_C8_H 0x0AB1
|
||||
#define CMU_GLCSC_M_O1_1 0x0AB4
|
||||
#define CMU_GLCSC_M_O1_2 0x0AB5
|
||||
#define CMU_GLCSC_M_O1_3 0x0AB6
|
||||
#define CMU_GLCSC_M_O2_1 0x0AB8
|
||||
#define CMU_GLCSC_M_O2_2 0x0AB9
|
||||
#define CMU_GLCSC_M_O2_3 0x0ABA
|
||||
#define CMU_GLCSC_M_O3_1 0x0ABC
|
||||
#define CMU_GLCSC_M_O3_2 0x0ABD
|
||||
#define CMU_GLCSC_M_O3_3 0x0ABE
|
||||
#define CMU_GLCSC_P_C0_L 0x0AC0
|
||||
#define CMU_GLCSC_P_C0_H 0x0AC1
|
||||
#define CMU_GLCSC_P_C1_L 0x0AC2
|
||||
#define CMU_GLCSC_P_C1_H 0x0AC3
|
||||
#define CMU_GLCSC_P_C2_L 0x0AC4
|
||||
#define CMU_GLCSC_P_C2_H 0x0AC5
|
||||
#define CMU_GLCSC_P_C3_L 0x0AC6
|
||||
#define CMU_GLCSC_P_C3_H 0x0AC7
|
||||
#define CMU_GLCSC_P_C4_L 0x0AC8
|
||||
#define CMU_GLCSC_P_C4_H 0x0AC9
|
||||
#define CMU_GLCSC_P_C5_L 0x0ACA
|
||||
#define CMU_GLCSC_P_C5_H 0x0ACB
|
||||
#define CMU_GLCSC_P_C6_L 0x0ACC
|
||||
#define CMU_GLCSC_P_C6_H 0x0ACD
|
||||
#define CMU_GLCSC_P_C7_L 0x0ACE
|
||||
#define CMU_GLCSC_P_C7_H 0x0ACF
|
||||
#define CMU_GLCSC_P_C8_L 0x0AD0
|
||||
#define CMU_GLCSC_P_C8_H 0x0AD1
|
||||
#define CMU_GLCSC_P_O1_1 0x0AD4
|
||||
#define CMU_GLCSC_P_O1_2 0x0AD5
|
||||
#define CMU_GLCSC_P_O1_3 0x0AD6
|
||||
#define CMU_GLCSC_P_O2_1 0x0AD8
|
||||
#define CMU_GLCSC_P_O2_2 0x0AD9
|
||||
#define CMU_GLCSC_P_O2_3 0x0ADA
|
||||
#define CMU_GLCSC_P_O3_1 0x0ADC
|
||||
#define CMU_GLCSC_P_O3_2 0x0ADD
|
||||
#define CMU_GLCSC_P_O3_3 0x0ADE
|
||||
#define CMU_PIXVAL_M_EN 0x0AE0
|
||||
#define CMU_PIXVAL_P_EN 0x0AE1
|
||||
|
||||
#define CMU_CLK_CTRL_TCLK 0x0
|
||||
#define CMU_CLK_CTRL_SCLK 0x2
|
||||
#define CMU_CLK_CTRL_MSK 0x2
|
||||
#define CMU_CLK_CTRL_ENABLE 0x1
|
||||
|
||||
#define LCD_TOP_CTRL_TV 0x2
|
||||
#define LCD_TOP_CTRL_PN 0x0
|
||||
#define LCD_TOP_CTRL_SEL_MSK 0x2
|
||||
#define LCD_IO_CMU_IN_SEL_MSK (0x3 << 20)
|
||||
#define LCD_IO_CMU_IN_SEL_TV 0
|
||||
#define LCD_IO_CMU_IN_SEL_PN 1
|
||||
#define LCD_IO_CMU_IN_SEL_PN2 2
|
||||
#define LCD_IO_TV_OUT_SEL_MSK (0x3 << 26)
|
||||
#define LCD_IO_PN_OUT_SEL_MSK (0x3 << 24)
|
||||
#define LCD_IO_PN2_OUT_SEL_MSK (0x3 << 28)
|
||||
#define LCD_IO_TV_OUT_SEL_NON 3
|
||||
#define LCD_IO_PN_OUT_SEL_NON 3
|
||||
#define LCD_IO_PN2_OUT_SEL_NON 3
|
||||
#define LCD_TOP_CTRL_CMU_ENABLE 0x1
|
||||
#define LCD_IO_OVERL_MSK 0xC00000
|
||||
#define LCD_IO_OVERL_TV 0x0
|
||||
#define LCD_IO_OVERL_LCD1 0x400000
|
||||
#define LCD_IO_OVERL_LCD2 0xC00000
|
||||
#define HINVERT_MSK 0x4
|
||||
#define VINVERT_MSK 0x8
|
||||
#define HINVERT_LEN 0x2
|
||||
#define VINVERT_LEN 0x3
|
||||
|
||||
#define CMU_CTRL 0x88
|
||||
#define CMU_CTRL_A0_MSK 0x6
|
||||
#define CMU_CTRL_A0_TV 0x0
|
||||
#define CMU_CTRL_A0_LCD1 0x1
|
||||
#define CMU_CTRL_A0_LCD2 0x2
|
||||
#define CMU_CTRL_A0_HDMI 0x3
|
||||
|
||||
#define ICR_DRV_ROUTE_OFF 0x0
|
||||
#define ICR_DRV_ROUTE_TV 0x1
|
||||
#define ICR_DRV_ROUTE_LCD1 0x2
|
||||
#define ICR_DRV_ROUTE_LCD2 0x3
|
||||
|
||||
enum {
|
||||
PATH_PN = 0,
|
||||
PATH_TV,
|
||||
|
|
|
|||
Loading…
Reference in New Issue