arch/tile: catch up on various minor cleanups.
None of these changes fix any actual bugs, but are just various cleanups that fell out along the way. In particular, some unused #defines and includes are removed, PREFETCH_STRIDE is added (the default is right for our shipping chips, but wrong for our next generation), our tile-specific prefetching code is removed so the (identical) generic prefetching code can be used instead, a comment is fixed to be proper GPL and not just a "paste GPL here" token, a "//" comment is converted to "/* */", etc. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
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Chris Metcalf
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ef06f55a5c
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@ -21,11 +21,6 @@
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#define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/* bytes per L1 instruction cache line */
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#define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()
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#define L1I_CACHE_BYTES (1 << L1I_CACHE_SHIFT)
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#define L1I_CACHE_ALIGN(x) (((x)+(L1I_CACHE_BYTES-1)) & -L1I_CACHE_BYTES)
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/* bytes per L2 cache line */
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#define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE()
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#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
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@ -15,7 +15,6 @@
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#ifndef _ASM_TILE_IRQFLAGS_H
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#define _ASM_TILE_IRQFLAGS_H
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#include <asm/processor.h>
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#include <arch/interrupts.h>
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#include <arch/chip.h>
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@ -267,32 +267,20 @@ extern int hash_default;
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/* Should kernel stack pages be hash-for-home? */
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extern int kstack_hash;
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/* Does MAP_ANONYMOUS return hash-for-home pages by default? */
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#define uheap_hash hash_default
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#else
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#define hash_default 0
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#define kstack_hash 0
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#define uheap_hash 0
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#endif
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/* Are we using huge pages in the TLB for kernel data? */
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extern int kdata_huge;
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/*
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* Note that with OLOC the prefetch will return an unused read word to
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* the issuing tile, which will cause some MDN traffic. Benchmarking
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* should be done to see whether this outweighs prefetching.
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*/
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#define ARCH_HAS_PREFETCH
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#define ARCH_HAS_PREFETCHW
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#define ARCH_HAS_SPINLOCK_PREFETCH
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#define prefetch(ptr) __builtin_prefetch((ptr), 0, 3)
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#define prefetchw(ptr) __builtin_prefetch((ptr), 1, 3)
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#ifdef CONFIG_SMP
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#define spin_lock_prefetch(ptr) prefetchw(ptr)
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#else
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/* Nothing to prefetch. */
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#define spin_lock_prefetch(lock) do { } while (0)
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#endif
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#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
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#else /* __ASSEMBLY__ */
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@ -136,8 +136,6 @@ mb_incoherent(void)
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#define set_mb(var, value) \
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do { var = value; mb(); } while (0)
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#include <linux/irqflags.h>
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/*
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* Pause the DMA engine and static network before task switching.
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*/
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@ -150,11 +150,6 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti,
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#endif
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#define TS_POLLING 0x0004 /* in idle loop but not sleeping */
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#define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal */
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#define TS_EXEC_HASH_SET 0x0010 /* apply TS_EXEC_HASH_xxx flags */
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#define TS_EXEC_HASH_RO 0x0020 /* during exec, hash r/o segments */
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#define TS_EXEC_HASH_RW 0x0040 /* during exec, hash r/w segments */
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#define TS_EXEC_HASH_STACK 0x0080 /* during exec, hash the stack */
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#define TS_EXEC_HASH_FLAGS 0x00f0 /* mask for TS_EXEC_HASH_xxx flags */
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#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
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@ -547,7 +547,7 @@ void hv_assert_intr(HV_IntrMask assert_mask);
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*/
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HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt);
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#endif // !CHIP_HAS_IPI()
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#endif /* !CHIP_HAS_IPI() */
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/** Store memory mapping in debug memory so that external debugger can read it.
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* A maximum of 16 entries can be stored.
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@ -1,15 +1,15 @@
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/*
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* %LINUX_LICENSE%
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*
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*
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*
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*
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*
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*
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*
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*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* Tilera TILE Processor hypervisor console
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*/
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